MX29VW160BTC-90 - Macronix International Co., Ltd.

MX29VW160T/B

16M-BIT [2M x 8-BIT/1M x16-BIT]

SIMULTANEOUS READ/WRITE

SINGLE 3.0V OPERATION FLASH MEMORY

ADVANCE INFORMATION

FEATURES

• Two Memory Banks for Simultaneous Read/Write

operations

- Host system can program or erase in one bank and

simultaneously read from the other bank

- Zero latency between simultaneous Read/Write

operations

- Read-While-Erase/Program

• Extended Single-supply voltage range from 2.7V to

3.0V for read, erase and write operations

• JEDEC-standard EEPROM commands

• Minimum 100,000 write/erase cycles

• Fast Access time: 90ns

• Optimized block architecture:

- Bank A

- Eight 8K Byte (4K Word) blocks

- Three 64K Byte (32K Word) blocks

- Bank B

- Twenty-eight 64K Byte (32K Word) blocks

• Data polling and toggle bit feature for detection of

program or erase cycle completion

• Ready/Busy output (RY/BY): Hardware method for

detection of program or erase cycle completion

• Automatic standby mode: When addresses remain

stable,automatically switch themselves to low power

mode(1uA Typical)

• Auto erase operation

- Automatically erases any combination of the blocks

or the whole chip

- Fast erase time: 20ms typical for single block erase

and 50ms typical for chip erase and multi-block erase

• Auto page program operation

- Automatically programs and verifies data at speci-

fied addresses

- Internal address and data latches for 128 Bytes (64

Word) per page in each bank

- Fast program time: 4ms typical for page program

• Built-in 128 Bytes/64 Words page buffer in each bank

- Work as SRAM for temporary data storage

- Fast access to temporary data

• Low power dissipation (typical values at 8MHz)

- 40mA typical for Read While Write

- 20mA typical for Read

- 1uA typical for standby

• Hardware reset pin (RP)

- Reset internal state machine and put the device into

standby mode

• Hardware write protect pin (WP)

- Allows protection of the first two 8K Byte blocks,

regardless of their orginal protect status.

• Group Protection

- Hardware method of locking groups to prevent any

program or erase operation within that group

- Any group can be locked in-system or via program-

ming equipment

- Temporary group unprotect feature allows code

change in any previously locked group

•Erase Suspend/Erase Resume

- Suspends or resumes erasing blocks to allow read-

ing and programming in other bloc ks .

- It is not necessary to do erase suspend if reading

or programming b locks in the other bank

• Low Vcc write inhibit is equal to or less than 1.6V

• Compatible with JEDEC-standard pinouts

- 48-pin TSOP (I)

- 48-ball CSP

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

GENERAL DESCRIPTION

The MX29VW160T/B is a 16Mbit Flash memory

organized as either 2M-byte by 8-bit or 1M-word by

16-bit. T o provide simultaneous operation which can read

a data while program/erase,the 16Mbits of data is

divided into two banks of bank A ( 2M bit) and bank

B(14M bit). Bank A is organized by eight 8K-byte blocks

and three 64k-byte blocks. Bank B is organized by

twenty-eight 64K-b yte blocks .

To allow for simple in-system operation with very low

operation voltage, MX29VW160T/B can be operated with

a single 2.7V to 3.0V supply voltage.Manufactured with

MXIC's advanced nonvolatile memory technology, the

device offers access times of 90ns, and a low 1uA typi-

cal standby current.

The MX29VW160T/B command set is compatible with

the JEDEC single-power-supply flash standard.

Commands are written to the command register using

standard micro-processor write timings. MXIC's flash

memory augments EPROM functionality with an

internal state machine which controls the erase and

program circuitry. The device RY/BY pin provides a

convenient way to monitor when a program or erase

cycle is complete.

Programming the MX29VW160T/B is performed on a

page basis; 128 bytes of data are loaded into the device

and then programmed simultaneously . The typical Page

Program time is 4ms. The device can also be

reprogrammed in standard EPROM programmers.

Reading data out of the device is similar to reading from

an EPR OM or other flash.

Erase is accomplished by executing the Erase command

sequence. This will invoke the Auto Erase algorithm

which is an internal algor ithm that automatically times

the erase pulse widths and ver ifies proper cell margin.

This device features both chip erase and block erase.

Each block can be erased and programmed without

affecting other blocks. Using MXIC's advance design

technology, no preprogram is required (internally or

externally). As a result, the whole chip can be typically

erased and verified in as fast as 50ms.

A combined feature of Reset Pin (RP), a hardware

lockout bit, and software command sequences pro vide

complete data protection. First, software data

protection protects the device from inadvertent program

or erase. Two "unlock" write cycles must be presented

to the device before the program or erase command can

be accepted by the device. For hardware data protec-

tion, the RP pin provide protection against unwanted

command writes due to invalid system bus condition that

ma y occur during system reset and power up/do wn se-

quence. Finally, with a hardware loc kout bit f eature , the

device provides complete core security for the kernal

code required f or system initialization.

MXIC's flash technology reliably stores memory

contents after 100,000 erase and program cycles. The

MXIC's cell is designed to optimize the erase and

program mechanism. In addition, the combination of

advanced tunnel oxide processing and low internal

electric fields for erase and program operations produce

reliable cycling.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up

protection is prov ed for stresses up to 100 milliamps on

address and data pin from -1V to Vcc+1V.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

PINOUT

48-PIN TSOP(I) 12mm x 20mm

48-Ball CSP 8mm x 13mm x 1.2mm(Ball Pitch = 0.8 mm), Top View, Balls Facing Up

A BCDEFGH

1A3 A4A2A1A0CEOEGND

2 A7 A17 A6 A5 Q0 Q8 Q9 Q1

3 RY/BY WP A18 NC Q2 Q10 Q11 Q3

4 WE RP NC A19 Q5 Q12 Vcc Q4

5 A9 A8 A10 A11 Q7 Q14 Q13 Q6

6 A13 A12 A14 A15 A16 BYTE Q15/A-1 GND

PIN DESCRIPTION

SYMBOL PIN NAME

A0 ~ A19 Address Input

Q0 ~ Q14 Data Input/ Output

Q15/A-1 Q15 (word mode)/LSB addr. (byte

mode)

CE Chip Enable Input

OE Output Enable Input

WE Write Enable

WP Write Protect

RP Reset/Deep P ower-down

R Y/BY Ready/Busy Output

BYTE W ord/Byte Selection Input

Vcc Pow er Supply Pin (2.25V ~ 3.0V)

GND Ground Pin

NC No Internal Connection Pin

MX29VW160T/B

A16

BYTE

GND

Q15/A-1

Q14

Q13

Q12

Vcc

Q11

Q10

GND

A15

A14

A13

A12

A11

A10

A19

RY/BY

A18

A17

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Table 1 Block Architecture (Word Mode Addr. :A0~A19, BYTE Mode Addr.:A-1~A19)

Byte Mode (A-1 TO A19) Word Mode (A0 TO A19)

1FFFFF~1FE000 FFFFF~FF000 8K-Byte Block SA01 GA01 BANK A

1FDFFF~1FC000 FEFFF~FE000 8K-Byte Block SA02 GA02 BANK A

1FBFFF~1FA000 FDFFF~FD000 8K-Byte Block SA03 GA03 BANK A

1F9FFF~1F8000 FCFFF~FC000 8K-Byte Block SA04 GA04 BANK A

1F7FFF~1F6000 FBFFF~FB000 8K-Byte Block SA05 GA05 BANK A

1F5FFF~1F4000 FAFFF~FA000 8K-Byte Block SA06 GA06 BANK A

1F3FFF~1F2000 F9FFF~F9000 8K-Byte Block SA07 GA07 BANK A

1F1FFF~1F0000 F8FFF~F8000 8K-Byte Block SA08 GA08 BANK A

1EFFFF~1E0000 F7FFF~F0000 64K-Byte Block SA09 GA09 BANK A

1DFFFF~1D0000 EFFFF~E8000 64K-Byte Block SA10 GA09 BANK A

1CFFFF~1C0000 E7FFF~E0000 64K-Byte Block SA11 GA09 BANK A

1BFFFF~1B0000 DFFFF~D8000 64K-Byte Block SA12 GA10 BANK B

1AFFFF~1A0000 D7FFF~D0000 64K-Byte Block SA13 GA10 BANK B

19FFFF~190000 CFFFF~C8000 64K-Byte Block SA14 GA10 BANK B

18FFFF~180000 C7FFF~C0000 64K-Byte Block SA15 GA10 BANK B

17FFFF~170000 BFFFF~B8000 64K-Byte Block SA16 GA11 BANK B

16FFFF~160000 B7FFF~B0000 64K-Byte Block SA17 GA11 BANK B

15FFFF~150000 AFFFF~A8000 64K-Byte Block SA18 GA11 BANK B

14FFFF~140000 A7FFF~A0000 64K-Byte Block SA19 GA11 BANK B

13FFFF~130000 9FFFF~98000 64K-Byte Block SA20 GA12 BANK B

12FFFF~120000 97FFF~90000 64K-Byte Block SA21 GA12 BANK B

11FFFF~110000 8FFFF~88000 64K-Byte Block SA22 GA12 BANK B

10FFFF~100000 87FFF~80000 64K-Byte Block SA23 GA12 BANK B

0FFFFF~0F0000 7FFFF~78000 64K-Byte Block SA24 GA13 BANK B

0EFFFF~0E0000 77FFF~70000 64K-Byte Block SA25 GA13 BANK B

0DFFFF~0D0000 6FFFF~68000 64K-Byte Block SA26 GA13 BANK B

0CFFFF~0C0000 67FFF~60000 64K-Byte Block SA27 GA13 BANK B

0BFFFF~0B0000 5FFFF~58000 64K-Byte Block SA28 GA14 BANK B

0AFFFF~0A0000 57FFF~50000 64K-Byte Block SA29 GA14 BANK B

09FFFF~090000 4FFFF~48000 64K-Byte Block SA30 GA14 BANK B

08FFFF~080000 47FFF~40000 64K-Byte Block SA31 GA14 BANK B

07FFFF~070000 3FFFF~38000 64K-Byte Block SA32 GA15 BANK B

06FFFF~060000 37FFF~30000 64K-Byte Block SA33 GA15 BANK B

05FFFF~050000 2FFFF~28000 64K-Byte Block SA34 GA15 BANK B

04FFFF~040000 27FFF~20000 64K-Byte Block SA35 GA15 BANK B

03FFFF~030000 1FFFF~18000 64K-Byte Block SA36 GA16 BANK B

02FFFF~020000 17FFF~10000 64K-Byte Block SA37 GA16 BANK B

01FFFF~010000 0FFFF~08000 64K-Byte Block SA38 GA16 BANK B

00FFFF~000000 07FFF~00000 64K-Byte Block SA39 GA17 BANK B

MX29VW160T

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Byte Mode (A-1 TO A19) Word Mode (A0 TO A19)

1FFFFF~1F0000 FFFFF~F8000 64K-Byte Block SA01 GA01 BANK A

1EFFFF~1E0000 F7FFF~F0000 64K-Byte Block SA02 GA02 BANK A

1DFFFF~1D0000 EFFFF~E8000 64K-Byte Block SA03 GA02 BANK A

1CFFFF~1C0000 E7FFF~E0000 64K-Byte Block SA04 GA02 BANK A

1BFFFF~1B0000 DFFFF~D8000 64K-Byte Block SA05 GA03 BANK A

1AFFFF~1A0000 D7FFF~D0000 64K-Byte Block SA06 GA03 BANK A

19FFFF~190000 CFFFF~C8000 64K-Byte Block SA07 GA03 BANK A

18FFFF~180000 C7FFF~C0000 64K-Byte Block SA08 GA03 BANK A

17FFFF~170000 BFFFF~B8000 64K-Byte Block SA09 GA04 BANK A

16FFFF~160000 B7FFF~B0000 64K-Byte Block SA10 GA04 BANK A

15FFFF~150000 AFFFF~A8000 64K-Byte Block SA11 GA04 BANK A

14FFFF~140000 A7FFF~A0000 64K-Byte Block SA12 GA04 BANK A

13FFFF~130000 9FFFF~98000 64K-Byte Block SA13 GA05 BANK A

12FFFF~120000 97FFF~90000 64K-Byte Block SA14 GA05 BANK A

11FFFF~110000 8FFFF~88000 64K-Byte Block SA15 GA05 BANK A

10FFFF~100000 87FFF~80000 64K-Byte Block SA16 GA05 BANK A

0FFFFF~0F0000 7FFFF~78000 64K-Byte Block SA17 GA06 BANK A

0EFFFF~0E0000 77FFF~70000 64K-Byte Block SA18 GA06 BANK A

0DFFFF~0D0000 6FFFF~68000 64K-Byte Block SA19 GA06 BANK A

0CFFFF~0C0000 67FFF~60000 64K-Byte Block SA20 GA06 BANK A

0BFFFF~0B0000 5FFFF~58000 64K-Byte Block SA21 GA07 BANK A

0AFFFF~0A0000 57FFF~50000 64K-Byte Block SA22 GA07 BANK A

09FFFF~090000 4FFFF~48000 64K-Byte Block SA23 GA07 BANK A

08FFFF~080000 47FFF~40000 64K-Byte Block SA24 GA07 BANK A

07FFFF~070000 3FFFF~38000 64K-Byte Block SA25 GA08 BANK A

06FFFF~060000 37FFF~30000 64K-Byte Block SA26 GA08 BANK A

05FFFF~050000 2FFFF~28000 64K-Byte Block SA27 GA08 BANK A

04FFFF~040000 27FFF~20000 64K-Byte Block SA28 GA08 BANK A

03FFFF~030000 1FFFF~18000 64K-Byte Block SA29 GA09 BANK B

02FFFF~020000 17FFF~10000 64K-Byte Block SA30 GA09 BANK B

01FFFF~010000 0FFFF~08000 64K-Byte Block SA31 GA09 BANK B

00FFFF~00E000 07FFF~07000 8K-Byte Block SA32 GA10 BANK B

00DFFF~00C000 06FFF~06000 8K-Byte Block SA33 GA11 BANK B

00BFFF~00A000 05FFF~05000 8K-Byte Block SA34 GA12 BANK B

009FFF~008000 04FFF~04000 8K-Byte Block SA35 GA13 BANK B

007FFF~006000 03FFF~03000 8K-Byte Block SA36 GA14 BANK B

005FFF~004000 02FFF~02000 8K-Byte Block SA37 GA15 BANK B

003FFF~002000 01FFF~01000 8K-Byte Block SA38 GA16 BANK B

001FFF ~000000 00FFF~00000 8K-Byte Block SA39 GA17 BANK B

MX29VW160B

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Block Diagram

Control

Input

Logic

Write State

Machine (WSM) Command Interface

Command Data

Latch

I/O Buffer

Program/

Erase

high

Voltage

Generator

Sense Amplifier

MUX

Address

Latch &

Buffer

MUX Y-Pass Gate

Page Buffer

Bank B

(32KW/64KB x28)

Y-Decoder X-Decoder

Bank A

4KW/8KB x 8

32KW/64KB x 3

Page Buffer

Y-Pass Gate

X-Decoder Y-Decoder

MUX

RY/BY

A0~A19 A-1

WSM

Q0~Q15/A-1

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

BUS OPERATIONS

Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles . These b us operations are summarized belo w.

* : Valid Sector Address must be provided when doing block protect Ve rify mode.

Legend : L = Logic Low = VIL, H = Logic High = VIH ,X = VIL or VIH, VID = 8.5~10.5V ,Refer to DC Characteristics for Voltage

loads.

Notes:

1. X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH.

2. RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-do wn mode , R Y/BY

will be at VOH, if it is tied to Vcc through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM

operation is in progress.

3. RP< GND+0.2V ensures the lowest consumption current.

4. A0 and A1 at VIL provide manufacturer ID code. A0 at VIH and A1 at VIL provide ID code. A0 at VIL, A1 at VIH and with

appropriate block address provide Block Protect Code.(Refer to Table 4)

5.Command or different Erase operations, Data program operations or Group protect operation can only be successfully com-

pleted through proper command sequence.

6. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode.

7.RY/BY may be at VOL while the WSM is busy performing various operations.

8.VID = 8.5V-10.5V

9. Q15/A-1 = VIL, Q0-Q7 = D0-D7 out. Q15/A-1 = VIH, Q0-Q7 = D8-D15 out.

10. When WP=VIL, the two outer most 8K-Byte blocks be protected.

When WP=VIH, all blocks remain orginal protect status.

When WP=VID, all blocks be unprotected.

MODE CE OE WE RP WP A0 A1 A6 A9 Q0~Q7 Q8~Q14 Q15/A-1 Notes

Read L L H H L/H A0 A1 A6 A9 DOUT DOUT DOUT 1,2,7

Output Disable L H H H X X X X X HighZ HighZ HighZ 1,6,7

Standby H X X H X X X X X HighZ HighZ HighZ 1,6,7

Hardware Standby X X X L X X X X X HighZ HighZ HighZ 1,3

Manufacturer ID L L H H L/H L L X VID C2H 00H 0B 4,8

Device ID L L H H L/H H L X VID 67/68H 00H 0B 4,8

Block Protect Ver ify * L L H H H L H X VID C2H 00H 0B

Write L H L H L/H/VID A0 A1 A6 A9 DIN DIN DIN 1,5,6,10

Table 2.2 MX29VW160T/B Bus Operations for W or d-Wide Mode (Byte = VIH)

MODE CE OE WE RP WP A0 A1 A6 A9 Q0~Q7 Q8~Q14 Q15/A-1 Notes

Read L L H H L/H A0 A1 A6 A9 DOUT HighZ A-1 1,2,7,9

Output Disable L H H H X X X X X HighZ HighZ X 1,6,7

Standby H X X H X X X X X HighZ HighZ X 1,6,7

Hardware Standby X X X L X X X X X HighZ HighZ X 1,3

Manufacturer ID L L H H L/H L L X VID C2H HighZ X 4,8

Device ID L L H H L/H H L X VID 67/68H HighZ X 4,8

Block Protect Ver ify * L L H H H L H X VID C2H HighZ X

Write L H L H L/H/VID A0 A1 A6 A9 DIN High Z A-1 1,5,6,10

Table 2.1 MX29VW160T/B Bus Operations f or Byte-Wide Mode (Byte = VIL)

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

COMMAND DEFINITIONS

Table 3 Command Definitions

Bus Cycles

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1 RA RD

Reset 1 XXXH F0H

Manufacturer ID Word 4 555H AAH 2AAH 55H 555H 90H X00H 00C2H

Byte AAAH 555H AAAH X00H C2H

Device ID Word 4 555H AAH 2AAH 55H 555H 90H X01H 0067H/0068H*

Byte AAAH 555H AAAH X02H 67H/68H*

Block Protect Word 4 555H AAH 2AAH 55H 555H 90H X02H XX01H/XX00H*

Verify Byte AAAH 555H AAAH X04H 01H/00H*

Group Protect Word 6 555H AAH 2AAH 55H 555H 60H 555H AAH 2AAH 55H GA 20H

Byte AAAH 555H AAAH AAAH 555H

Chip Unprotect Word 6 555H AAH 2AAH 55H 555H 60H 555H AAH 2AAH 55H 555H 40H

Byte AAAH 555H AAAH AAAH 555H AAAH

Page Program Word 555H AAH 2AAH 55H 555H A0H PA PD

Single Block Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 20H

Erase Byte AAAH 555H AAAH AAAH 555H

Multi Block Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Erase Byte AAAH 555H AAAH AAAH 555H

Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte AAAH 555H AAAH AAAH 555H AAAH

Erase Suspend 1 XXXH B0H

Erase Resume 1 XXXH 30H

Notes:

1. *00H Represents unprotect block & *01H represents protect block in the 4th Bus cycle data of "Block Protect Ver ify".

2. Address bit A11-A19 = X = "Don't care" f or all address commands e xcept f or Progr am Address (PA) and Block Address (SA).

555H and 2AAH address command codes stand for He x number starting from A0 to A10 in word mode and A-1 to A10 in byte

mode.

3.Bus operations are defined in Table 2.

4. RA = Address of the memory location to be read.

PA = Address of the memor y location to be programmed. Address are located on the falling edge of the WE pulse.

SA = Address of the block to be erase. The combination of A12-A19 will select any block(Refer to Table 1).

GA = Group address to be protect. The combination of A12-A19 will select any group.

5.RD = Data read from location RA during read operation.

PD = Data to be Programmed at location PA. Data is latched on the r ising edge of WE.

6.Only Q0-Q7 command data is taken, Q8 to Q15 = Don't care.

*Refer to Table 4.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

FUNCTIONAL DESCRIPTION

SIMUL TANEOUS OPERA TION

The MX29VW160T/B provides the simultaneous read/write

function. The de vice is capable of reading data from one

bank and simultaneously erasing (so as, programming,

erase-suspend reading, and erase suspend programming)

data from the other bank. The bank selection can be se-

lected b y bank address (A17 to A19) with zero latency.

The MX29VW160T/B contains two data banks which

are bank A (8K-Byte x 8, 64K-Byte x 3) and Bank B

(64K-Byte x 28). Following table describes the detail

simultaneous operation.

Simultaneous Operation Table

Bank-B standby Read Single Multiple block Multiple block Chip Erase Erase Page Group Silicon

mode block erase erase erase suspend resume program protect/ ID

Bank-A erase (only 1 bank) ( 2 banks) unprotect read

Standby O - - - - - - - - - -

Read mode - X O O X - O O O X -

Single block erase - O - - - - - - X X -

Multiple block erase - O - - - - - - X - -

(only 1 bank)

Multiple block erase - X - - O - O O X X -

( 2 banks)

Chip erase - - - - - O - - - - -

Erase suspend - O - - O - - - - X O

Erase resume - O - - O - - - - X -

Page program - O X X X - - - - X -

Group protect/ - X X - X - X X X - -

unprotect

Silicon ID read - - - - - - O - - - -

Legend : "o"=Oka y,"X"= Not allow, "-"= Not availab le .

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

READ ARRAY MODE

The MX29VW160T/B must satisfy two control functions

to obtain data output. CE is the power control and should

be used f or a de vice selection. OE is the output control

and should be used to gate data to the output pins if a

de vice is selected.(Figure 11)

Address access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from state the falling edge

of CE to valid data at the output pins. (Assuming the

addresses have been stable for at least tACC - tCE time.)

When reading out a data without changing addresses

after power-up, it is necessary to input hardware reset

or to change CE pin from "H" to "L".

READ/RESET COMMAND

The Read or Reset operation is initiated by wr iting the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve arra y data from

the memory. The device remains enable for reads until

the command register contents are altered.

The device will automatically power-up in the read/reset

state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will

retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs

during the power transition. Refer to the AC Read

Characteristics and Waveforms (Figure 12) for the

specific timing parameters .

READ ID MODE

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible while

the device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high v oltage. Howe v er, m ultiplexing high v oltage onto

address lines is not generally desired system design

practice.

The MX29VW160T/B contains a Silicon-ID-Read Op-

eration to supplement traditional PROM programming

methodology. The operation is initiated by writing the

Read Silicon ID command sequence into the command

A1=VIL, A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 67H f or MX29VW160T, 68H for MX29VW160B.

The Silicon-ID-Read Operation also covers the block

protection verification. A read cycle with A1=VIH, A0=

"Don't care" returns data of 00H for"unprotected bloc k"

and 01H f or "protected b lock".

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Table 4.1 Read ID Mode Table

*01H f or "protected b loc k" addresses and 00H f or "unprotected b lock" addresses .

TYPE A12 to A19 A6 A1 A0 A-1 Code (HEX)

Manuf acturer ID X X L L X C2H

MX29VW160T Byte X X L H X 67H

Device ID Word X 0067H

MX29VW160B Byte X X L H X 68H

Word X 0068H

Block Protection Verify Block Address X H X X 01H/00H*

TYPE Code (HEX)Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Manufacturer’s ID C2H A-1/0 0 0 0 000011000010

MX29VW160T Byte 67H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 1 0 0 1 1 1

Device ID Word 0067H 0 0 0 0 000001100111

MX29VW160B Byte 68H A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 1 0 1 0 0 0

Word 0068H 0 0 0 0 000001101000

Block Protection Verify 0 1H /00H** A-1/0 0 0 0 000000000001/0

Notes: * Manufacture Code = C2 H, Device Code = 67H/68H when BYTE = VIL

Manufacture Code = 00C2H,Device Code =0067H/0068H when BYTE = VIH

** Outputs 01H at protected block address ,00H at unprotected block address.

Table 4.2 Extended Read ID Mode Table

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

PROGRAM MODE

PA GE PR OGRAM

The MX29VW160T/B is page programmable with one

128-Byte/ 64-W ord page buff er in each bank. To initiate

Page program mode, a three-cycle command sequence

is required. There are two "unlock" wr ite cycles. These

are followed by writing the page program command A0H.

Any attempt to write to the device without the three-cycle

command sequence will not start the internal Write State

Machine (WSM), no data will be written to the device .

After three-cycle command sequence is given, a Byte/

Word load is performed by applying a low pulse on the

WE or CE input with CE or WE low (respectively) and

OE high. The address is latched on the falling edge of

CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE. Maximum of 128-Byte/

64-Word of data may be loaded into each page. Data

loading activity is terminated by issuing same address

load twice.

BYTE-WIDE LO AD/W ORD-WIDE LO AD

Byte (Word) loads are used to enter the 128 bytes (64

words) of a page to be programmed or the software

codes for data protection. A byte load (word load) is

performed by applying a low pulse on the WE or CE

input with CE or WE low respectiv ely, and OE high. The

address is latched on the falling edge of CE or WE,

whichever occurs last. The data is latched by the first

rising edge of CE or WE.

Either byte-wide load or word-wide load is deter mined

(Byte = VIL or VIH is latched) on the falling edge of the

WE (or CE) during the 3rd command write cycle.

AUTOMATIC PROGRAM ALGORITHM

Any page to be programmed should have the page in

the erased state first, i.e. performing block erase is

suggested before page programming can be performed.

The de vice is progr ammed on a page basis. If a byte of

data within a page is to be changed, data f or the entire

page must be loaded into the device. Any byte that is

not loaded during the programming of its page will be

still in the erased state (i.e. FFH). Once the b ytes of the

page are loaded into the device, they are simultaneously

programmed during the internal programming period.

After the first data byte has been loaded into the de vice,

successive bytes are entered in the same manner. A6

to A19 specify the page address, i.e., the device is page-

aligned on 128-byte boundary . The page addresses must

be valid (Page Address A6-A19 is latched at the 4th bus

write-cycle)during each high to low transition of WE or

CE. A-1 to A5 specify the byte address during the page.

The byte ma y be loaded in any order; sequential loading

is not required. The load period will also end if the same

address is consecutively loaded twice. For the last two

same address, the first address and data will be treated

as normal data to be programmed. The second one must

keep the same address and data as the first one .

The status of program cycle can be determined by

checking the Q7 (Data Polling), Q6 (Toggle Bit), or R Y/

BY.

The automatic programming operation is completed

when Q6 stops toggling (See Table 5 of Hardware Se-

quence Flags.)

WRITE OPERATION STATUS

Detailed in Table 5 are all the status flags that can

determine the status of the bank for the current mode

operation. The read operation from the bank where is

not operating Automatic algorithm returns a data of

memory cell. These bits offer a method f or determining

whether a Automatic Algorithm is completed properly.

The information on Q2 is address sensitive. This means

that if an address from an erasing block is consecutively

read, then the Q2 bit will toggle. However, Q2 will not

toggle if an address from a non-erasing block is

consecutively read. This allows the user to determine

which bloc ks are er asing and which are not.

The status flag is not output from bank (non-busy bank)

not executing Automatic Algorithm. For example, there

is bank (busy bank) which is now executing Automatic

Algorithm. When the read sequence is (a)"busy bank”

(b)"non-busy bank" and (c )"busy bank" the Q6 is tog-

gling in the case (a) and (c ). In case of (b), the data of

memory cell is output. In the erase-suspend read mode

with the same read sequence, Q6 will not be toggled in

the (a), and (c ).

In the erase suspend read mode, Q2 is toggled in the

(a) and (c ). In case of (b), the data of memory cell is

output.

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Table 5. Har dware Sequence Flags Table

Status Q7 Q6 Q5 Q3 Q2 RY/BY

A utomatic Program Algorithm Q7 Toggle 0 N/A No Toggle 0

A utomatic Erase Algorithm 0 Toggle 0 1 Toggle* 0

Erase Erase Suspend Read 1 No Toggle 0 N/A Toggle 1

In Progress Suspend (Erase-Suspend Bloc k)

Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase-Suspend Bloc k)

Erase Suspend Program Q7 Toggle 0 N/A N/A 0

(Non-Erase-Suspend Bloc k)

A utomatic Program Algorithm Q7 Toggle 1 0 1 0

Exceeded A utomatic Erase Algorithm 0 Toggle 1 1 N/A 0

Time Erase Erase Suspend Program Q7 Toggle 1 0 N/A 0

Limits Suspend (Non-Erase-Suspend Block)

Mode

*. Successive reads from the erasing block will cause Q2 to toggle. Reading from non-erase block address will indicate logic

"1" at the Q2 bit.

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ERASE MODE

AUT OMATIC CHIP ERASE

The MX29VW160T/B does not require pre-program

operation prior to erase operation. Chip erase is a

six-bus cycle operation. There are two "unlock" write

cycles. These are follow ed b y writing the "set-up" com-

mand (80H). Two more "unlock" write cycles are then

f ollow ed by the Chip Erase command (10H).

The system can determine the status of the erase

operation by using Q7 (Data Polling), Q6 (Toggle Bit), or

RY/BY. The chip erase begins on the rising edge of the

last CE or WE, whichever happens first in the command

sequence and terminates when the data on Q7 is (See

Write Operation Status section.) at which time the

de vice returns to read the mode.

AUTOMATIC BLOCK ERASE

The MX29VW160T/B does not require pre-program op-

eration prior to erase operation. Block erase is a six-bus

cycle operation. There are two "unlock" write cycles.

These are followed by writing the "set-up" command

(80H). Two more "unlock" write cycles are then follo wed

by the Block Erase command (20H for single-block erase,

30H for multi-block erase). The system is not required to

provide any controls or timings during these operations.

When erasing a block or blocks the remaining un-se-

lected blocks are not affected. The block address is

latched on the falling edge of CE or WE whiche ver hap-

pens later, while the command (data) is latched on the

rising edge of CE or WE whichever happens first.After

issue same address (A12-A19) twice ,the device will stop

block address loading and star t erase operation when

at multi-b lock er ase mode.

Before issued the same address twice to the device,

any command other than Erase Suspend (B0H) or multi

block Erase (30H) will reset the device to read mode

and ignore the pre vious command string.

The system can determine the status of the erase

operation by using Q7 (Data Polling), Q6 (Toggle Bit), or

RY/BY.

ERASE SUSPEND AND RESUME

The Erase Suspend command ,B0H allows the user to

interrupt a Block Erase operation and then perform data

reads from or program to a block not being erased. .This

command is applicable ONLY during the Block Erase

operation. The Erase Suspend command will be ignored

if written during the Chip Erase operation or Auto Pro-

gram Algorithm.

Writing the Erase Suspend command (B0H) during the

multiple block erase operation (before issue same ad-

dress twice to terminate the block address loading and

to start the erase operation) results immediate termina-

tion of the address loading and suspension of the erase

operation.

Writing the Erase Resume command (30H) resumes the

erase operation.

When the Erase Suspend command is written during

the Block Erase operation, the device will take a maxi-

mum of 300us to suspend the erase operation. When

the devices have entered the erase suspended mode,

the RY/BY output pin will be at HighZ . The user must

use the Q6 (or RY/BY pin) to determine if the erase

operation has been suspended. Further writes of the

Erase Suspend command are ignored.

To resume the operation of Block Erase, the Resume

command (30H) should be written . Any further writes of

the Resume command at this point will be ignored. An-

other Erase Suspend command can be written after the

chip has resumed erasing.

STANDBY MODE

MX29VW160T/B can be set into Standby mode with two

different approaches. One is using both CE and RP pins

and the other one is using RP pin only.

When using both pins of CE and RP, a CMOS Standby

mode is achieved with both pins held at Vcc ± 0.3V. Under

this condition, the current consumed is less than 1uA

(typ .). During Auto Algorithm operation, Vcc activ e cur-

rent (Icc2) is required e ven CE = "H".The de vice can be

read with standard access time (tCE) from either of these

standb y modes.

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

AUTOMATIC STANDBY MODE

MX29VW160T/B is capable to provide the Automatic

Standby Mode to restrain power consumption during

read-out of data. This mode can be used effectively with

an application requested low power consumption such

as handy terminals.

To active this mode, MX29VW160T/B automatically

switch themselves to low power mode when

MX29VW160T/B addresses remain stable during access

time of 250ns. It is not necessary to control CE, WE,

and OE on the mode. Under the mode, the current con-

sumed is typically 1uA (CMOS le vel).

During Simultaneous operation, Vcc active current (Icc2)

is required.Since the data are latched during this mode,

the data are read-out continuously. If the addresses are

changed, the mode is canceled automatically and

MX29VW160T/B read-out the data for changed ad-

dresses.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the de vices are disabled. This will cause the output pins

to be in a high impedance state.

DATA PROTECTION

The MX29VW160T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transitions. During power up the device automatically

resets the internal state machine in the Read Array mode.

Also, with its control register architecture, alteration of

the memory contents only occurs after successful

completion of specific command sequences.

The device also incorporates several features to

prevent inadvertent write cycles resulting from Vcc

pow er-up and pow er-down tr ansitions or system noise.

TEMPORARY CHIP UNPROTECT

This feature allows temoprary unprotection of previously

protected group to change data in-system. The Tempo-

rary Chip Unprotect mode is activated by setting the RP

pin to VID(8.5V -10.5V). During this mode, f ormerly pro-

tected groups can be programmed or erased as un-pro-

tected group. Once VID is remove from the RP pin,all

the previously protected group are protected again.Figure

1 shows the algorithm, for this feature.

GROUP PR OTECTION

To activate this mode,a six-bus cycle operation is re-

quired. there are two "unlock" write cycle. There are fo l-

lowed by writing the setup command.Two more "unlock"

write cycles are then followed by the lock group com-

mand-20H. Group address(A12~A19) is latched on the

falling edge of CE or WE of the sixth cycle of the com-

mand sequence. The automatic Lock operation begins

on the rising edge of the last WE pulse in the command

sequence and terminates when the Q6 stops toggling(or

RY/BY =1) at which time the device stays at the read

arra y mode.

The devcie remains enabled for read array mode until

the CIR contents are altered by a valid command se-

quence (Refer to the table 3 ).

CHIP UNPROTECT

It is also possible to unprotect all chip,same as the first

five write command cycle in activating chip protection

mode followed by the unprotect group command -40H,

the automatic unprotect operation begins on the rising

edge of the last WE pulse in the command sequence

and terminates when the Q6 stops toggling (or RY/BY

=1) at with time the device stays at the read array

mode.(Refer to table 3 ).Note that all chip are unprotected

after chip unprotection completed.

The device remains enable for read array mode until the

CIR content are altered by a v alid command sequence.

When using only RP, a CMOS standby mode is achieved

with RP input held at Vss ± 0.3V Under this condition the

current is consumed less than 1uA (typ.). Once the RP

pin is taken high,the device is bac k to activ e without re-

cov ery delay.

In the standby mode the outputs are in the high imped-

ance state, independent of the OE input.

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

VERIFY BLOCK PROTECT

To verify Protect status of the block,operation is initi-

ated by writing Silicon ID read command into the com-

mand register. Following the command write ,a read cycle

from address XXX2H(A1=VIH) and Group Address

(A15~A19) returns data of 00H for " unprotected block".

A read cycle from XXX2H(A1=VIH) and group address

(A15~A19) returns data of 01H for "protected bloc k".

RP VIL VIH VID

VIL Hardware Standby The two outer most 8K-Byte be protected, The two outer most 8K-Byte blocks be protected,

all other blocks remains at original protect all other blocks be unprotected.

status.

VIH Hardware Standby All blocks remain at origined protect status. All blocks be unprotected.

VID Hardware Standby All blocks be unprotected. All blocks be unprotected.

Figure 1 Temporary Chip Unprotect Operation

RP vs WP T ruth Table

Start

RP = VID (Note 1)

Perform Erase or Program Operation

RP= VIH

Temporary Chip Unprotect Completed(Note 2)

Note : 1. All protected groups are temporary unprotected.

VID=8.5V~10.5V

2. All previously protected groups are protected again.

Operation Completed

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 2 Group Protection Algorithm (Word Mode)

Start

PLSCNT = 0

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 60H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 20H Group Address

Group Protect Operation Terminated

Write Silicon ID Read Command

& Read Data with A1=VIH,

A15-A19=Group Address

PLSCNT =32 ?

Data = 01H ?

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 60H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 20H Block Address

RY/BY = 1?

Group Protected,Operation

Done,Device Stays at

Read Array Mode

Increment PLSCNT,

To Protect Group Again

Device Failed

Yes

RY/BY = 1?

Read RY/BY

* Group Address : A15~A19

Confirm Group

Protection Status

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 3 Chip Unprotection Algorithm (W ord Mode)

Start

PLSCNT = 0

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 60H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 40H Address 555H

RY/BY = 1?

Unprotect Chip

Operation Terminated

Write Silicon ID Read

Command & Read Data

with A1=VIH,A12~A19

= Group Address

PLSCNT = 32?

For all Chip

Data = 00H ?

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 60H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 40H Address 555H

RY/BY = 1?

Chip Unprotected,Operation

Done,Device Stays at

Read Array Mode

Increment PLSCNT,

To Unprotect Chip Again

Device Failed

Yes

Read RY/BY

Read Data for

all Chip

Read RY/BY

Note : *All chip are unprotected after chip unprotection completed.

Confirm Chip

Unprotection Status

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typ.) on CE or WE will not

initiate a write cycle.

LOGIC INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =

VIH, or WE = VIH. To initiate a write cycle CE and WE

must be a logical "0" while OE is a logical "1".

PO WER-UP SEQUENCE

The MX29VW160T/B powers up in the Read only mode.

In addition, the memor y contents may only be altered

after successful completion of the predefined command

sequences.

PO WER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its Vcc and GND.

Q7: Data P olling

The MX29VW160T/B features Data Polling as a method

to indicate to the host system that the Automatic Pro-

gram or Erase algorithms are either in progress or com-

pleted.

While the Automatic Programming algorithm is in op-

eration, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data Polling f eature is v alid after ter-

minating load operation f or automatic program.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1" The Data Polling feature is valid after the rising

edge of the sixth WE pulse of six write pulse sequences

f or automatic chip/b lock er ase.

The Data P olling feature is active during Automatic Pro-

gram/Erase algorithm (see section Q3 Block Erase Sta-

tus Bit ).

R Y/BY : Read y/Busy

The RY/BY is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program

algorithm is in progress or complete. The RY/BY status

is valid after the rising edge of the final WE pulse in the

command sequence. Since RY/BY is an open-drain

output, several RY/BY pins can be tied together in

parallel with a pull-up resistor to Vcc.

If the output is low (Busy), the de vice is actively er asing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready), the

device is ready to ready to read array data (including

during the Erase Suspend mode), or is in the standby

mode.

Table 5 sho ws the outputs for RY/BY.

Q6: Toggle Bit I

Toggle Bit I on Q6 indicates whether an Automatic

Program or Er ase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE pulse in the

command sequence (prior to the program or erase

operation), and during the block er ase time-out period.

During an Automatic Program or Erase algorithm

operation, successive read cycles to any address cause

Q6 to toggle. The system may use either OE or CE to

control the read cycles. When the operation is complete,

Q6 stops toggling.

After an erase command sequence is written, if all blocks

selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected blocks

are protected, the Automatic Erase algorithm erases the

un-protected blocks, and ignores the selected blocks that

are protected.

The system can use Q6 and Q2 together to determine

whether a block is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling. When

the device enters the Erase Suspend mode, Q6 stops

toggling. How ever, the system must also use Q2 to de-

termine which blocks are erasing or erase-suspended.

Alternativ ely, the system can use Q7.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

If a program address falls within a protected block, Q6

toggles for approximately 1us after the program

command sequence is written, then returns to reading

arra y data.

Q6 also toggles during the erase-suspend-program

mode, and stops toggling once the A utomatic Prog r am

algorithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

Q2: Toggle Bit II

The Toggle Bit II on Q2, when used with Q6, indicates

whether a particular bloc k is actively erasing (that is the

Automatic Erase algorithm is in process), or whether

that bloc k is erase-suspended. Toggle Bit II is valid after

the rising edge of the final WE pulse in the command

sequence.

Q2 toggles when the system reads at addresses within

those blocks that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the b loc k is

actively erasing or is erase-suspended. Q6, by compari-

son, indicates whether the device is actively erasing or

is erase-suspended, but cannot distinguish which blocks

are selected for erasure. Thus, both status bits are re-

quired f or blocks and mode inf ormation. Refer to table 5

to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/Q2

Whene ver the system initially begins reading toggle bit

status, it must read Q7~Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the de vice has com-

pleted the progr am or erase operation. The system can

read arra y data on Q7~Q0 on the f ollo wing read cycle .

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

also should note whether the value of Q5 is high (see

the section on Q5). If it is, the system should then deter-

mine again whether the toggle bit is toggling, since the

toggle bit may have stopped toggling just as Q5 went

high. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading arra y data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this case,

the system must start at the beginning of the algorithm

when it returns to determine the status of the operation.

Q5: Exceeded Timing Limits

Q5 will indicate if the program or erase time has

exceeded the specified limits (internal pulse count).

Under these conditions Q5 will produce a "1" This is a

time-out condition which indicates that the program or

erase cycle was not successfully completed. Data

P olling and T oggle Bit are the only operating functions of

the device under this condition.

If this time-out condition occurs during block erase op-

eration, it is specifiesd that a particular block is bad and

it may not be reused. However , other blocks are still func-

tional and may be used f or progr am or erase operation.

The device m ust be reset to use other b locks. Write the

Reset command sequence to the device, and then ex -

ecute program or erase command sequence. This al-

lows the system to continue to use the other active blocks

in the device .

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of bloc ks are bad.

The Q5 time-out condition may also appear if a user

tries to program a non b lank location without erasing. In

this case the device locks out and ne v er completes the

Automatic algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops

toggling. Once the device has exceeded timing limits,

the Q5 bit will indicate a logical "1" Please note that this

is not a device failure condition since the device was

incorrectly used.

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Q3: Block Erase Status Bit

The MX29VW160T/B provides three difference erase

operation :(1) chip erase. (2) single block erase,and (3)

mutil-block erase. The device will automatically start erase

operation after erase command completed when doing

(1) and (2). For the case of (3), toggling the same ad-

dress (A12 to A19 ) twice is necessary to terminate the

bloc k address loading and start the erase operation . No

extra time-out is needed to terminate the block address

loading or complete the erase operation .

During the period of issuing the erase command,Q3 will

remain low until the erase oper ation starts.Data polling

and Toggle Bit are valid after the initial block erase com-

mand sequence.

If Data P olling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the block address loading window

is still open. If Q3 is high (logical "1" the internally con-

trolled erase cycle has begun; attempts to write subse-

quent commands to the device will be ignored until the

erase operation is completed as indicated b y Data P oll-

ing or Toggle Bit. If Q3 is low (logical "0", the de vice will

be accept additional block erase command. To insure

the command has been accepted, the system software

should check the status of Q3 prior to and following each

subsequent block erase command. If Q3 were high on

the second status check, the command may not have

been accepted.Note that during the block address load-

ing period,any command other than Multiple Block Erase

(30H) or Erase Suspend (B0H) will reset the device to

read array mode.

WP : Write Protect Pin

When system provides VIL to the WP pin, the tw o outer

most 8K-Byte blocks (SA01 and SA02 of MX29VW160T

or SA38 and SA39 of MX29VW160B) will be protected

from progr am and erase oper ations.

When WP=VIH, the two outer most 8K-Byte b locks and

all other blocks will remain at (or back to) their original

protect status.

When WP=VID, the whole device will be unprotected.

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P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 4 Data Polling Algorithm

Read (Q0 to Q7)

Start

Q7 = Data ?

Q5 = 1 ?

Read (Q0 to Q7)

Q7 = Data ?

exceeded timing limits Pass

Yes

NOTE : Q7 is rechecked even if Q5 = "1" because Q7 may change simultaneously with Q5.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 5 Toggle Bit Algorithm

START

Read Q7-Q0

Q5= 1?

Read Q7-Q0

Twice

Program/Erase

operation Not

Complete,Write

Reset Command

Program/Erase

operation Complete

Toggle bit =

Toggle?

Toggle Bit =

Toggle ?

YES

Note:The system should recheck the toggle bit even if Q5="1"

because the toggle bit may stop toggling as Q5 changes

to "1".See the subsections on Q6 and Q2 for more

information.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Strat

Write erase Command

Sequence (See below)

Data polling/Toggle Bit

Successfull Command

Erase Completed

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H Block Address/20H

2AAH/55H

555H/AAH

2AAH/55H

555H/AAH

Block Address/30H

2AAH/55H

555H/AAH

2AAH/55H

555H/AAH

Chip Erase Command Sequence*

(Address/Command): Single-Block Erase Command Sequence

(Address/Command): Multi-Block Erase Command Sequence

(Address/Command):

Same Address

(A12-A19)

Toggling

twice ?

Yes

555H/80H 555H/80H

Figure 6 Automatic Erase Alogorithm (W ord Mode)

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Figure 7 Automatic Page Program Flow Chart (W ord Mode)

Start

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Loading End?

Page Program Completed

Reload the last address

Check Device Status

Q6 = Toggle ?

Q7 = Data ?

Program

another page ?

Operation Done,Device

Stays at Read Array Mode

To Continue Other Operations,

Stays at Read Array Mode

Program Error

Yes

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Table 6 DC CHARACTERISTICS

SYMBOL DESCRIPTIONS MIN. TYP. MAX. UNITS TEST CONDITIONS

IIL Input Load Current 1 uA Vcc = Vcc Max

VIN = Vcc or GND

ILO Output Leakage Current 10 uA Vcc = Vcc Max

VIN = Vcc or GND

ISB1 Vcc Standby Current (CMOS) 1 1 0 uA Vcc = Vcc Max

CE = VIH

ISB2 Vcc Standby Current (TTL) 5 mA Vcc = Vcc Max

CE = VIH

ICC1 Vcc Read Current 2 0 2 7 mA Vcc = Vcc Max

f = 8MHz, IOUT = 0mA

ICC2 Vcc Erase/ Suspend Current 2 0 35 mA CE = VIH

Block Erase Suspend

ICC3 Vcc Program Current 2 0 3 5 mA Program in Progress

ICC4 Vcc Erase Current 8 1 5 mA Erase in Progress

ICC5 Vcc Read/Write Current (Note 1) 2 5 4 5 mA Read/Write in Progress

ICC6 Vcc Read/Erase Current (Note 1) 2 5 4 5 mA Read/Erase in Progress

VIL Input Low V oltage -0.5 0.8 V

VIH Input High V oltage 0.7 x Vcc Vcc+0.3 V

V OL Output Low V oltage 0.45 V IOL = 2.1mA

Vcc = Vcc Min

V O H Output High V oltage Vcc-0.4 V IOH = -100uA

Vcc = Vcc Min

0.85Vcc V IOH = -2mA

Vcc = Vcc Min

VID V oltage f or Read ID Mode 8.5 1 0 10.5 V

Table 7 AC CHARACTERISTICS - READ OPERATIONS

SYMBOL DESCRIPTIONS MIN. MAX. UNIT CONDITIONS

tACC Address to Output Delay 9 0 ns CE=OE=VIL

tCE CE to Output Delay 9 0 ns OE=VIL

tOE OE to Output Delay 5 5 ns CE=VIL

tDF OE High to Output High Z (Note 1) 40 ns CE=VIL

tOH Address to Output Hold 0 ns CE=OE=VIL

Note 1: Not 100% Tested.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

WAVEFROM INPUT OUTPUT

Must Be Steady

May Be Chang

from H to L

May change

from L to H

"H" or "L" Any

Change Permitted

Does Not Apply

Will Be Steady

Will be Changing

from H to L

Will be Changing

from L to H

Changing

State Unknow

Center Line is High-

Impedance "Off" Stste

Figure 9 Switching T est Circuits

Figure 8 Key to Switching Waveforms

Test Specifications

Test Condition Unit

Output Load 1TTL

Output Load Capacitance,CL (in cluding jig capacitance) 30 pF

Input rise & fall time 5 ns

Input pulse Level 0~3.0 V

Input timing measurement reference levels 1.5 V

Output timing measurement reference levels 1.5 V

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

2.7K ohm +3.3V

CL=30pF Including jig capacitance

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 11 A C Wa vef orm f or Read Operations

Figure 10 Switching Test W a veforms

tACC

Address Stable

Output V alid

High Z

Output

Address

tRC

tOE

tOEH

tCE

tDF

tOH

High Z

1.5V TEST POINTS 1.5V

3.0V

0V INPUT OUTPUT

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 12 A C W avef orm f or Har dware Reset/Read Operations

Table 8 A C CHARA CTERISTICS-WRITE/ERASE/PR OGRAM OPERATION

SYMBOL DESCRIPTIONS MIN. MAX. UNIT CONDITIONS

tWC Write Cycle Time 9 0 ns

tAS Address Setup Time 0 ns

tAH Address Hold Time 6 5 ns

tDS Data Setup Time 6 5 ns

tDH Data Hold Time 0 ns

tOES Output Enable Setup Time 0 ns

tCES CE Setup Time 0 ns

tGHWL Read Recover Time Before Write 0 ns

tCS CE Setup Time 0 ns

tCH CE Hold Time 0 ns

tWP Write Pulse Width 6 5 ns

tWPH Write Pulse Width High 3 5 ns

tVCS CE setup Before VCC Ready 0 ns

tRB RY/BY recov ery time 0 ns

tRP RP pulse width 5 0 ns

tRH RP high time before read 5 0 ns

t R C Read cycle time 90 ns

tBUSY WE pin High to busy mode 70 ns

tREAD Y Reset pin Low to Read mode 5 0 us

tACC

Address Stable

Output V alid

High Z

Output

Address

tRC

tRP tRH tCE

tOH

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 13 A utomatic P a ge Program Timing W avef orm(Word Mode)

555H PA

(A0~A19) PA

(A0~A5) Last PA

(A0~A5)

A0H PD PD Last

PD Last

PD Status Status

tAS

tWC

tAH

tWP

tCS tCH

tWPH

tDH

tDS

RY/BY

Data

Address

Page Program Sequence (Last two cycle)

Legend :PA : Program addr. PD : Program data

Note : 1.A6~A19 for page addr.

2.It is necessary to write the last PA twice to terminate PD loading operation.

Status:Q7: Data Polling,Q6: toggle bit I,Q5:exceeded timing limits,Q3: Block Erase Status bit ,Q2: toggle bit II.

3rd cycle

Program

Operation

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 14 A C W avef orm Chip/Bloc k Erase Operations (Word Mode)

AAH 55H 80H AAH 55H

10H/

30H/20H

2AAH

555H

2AAH

555H

Address

Data

tVCS

tDH

tDS

tGHWL tWP tWPH

tCS tCH

tWC tAS tAH

Vcc

Notes: 1. SA is the sector address for sector Erase Address = 555H(Word),AAAH(Byte) for Chip Erase.

= A12~A19 for Block Erase.

2.These Waveform are for the word mode.(The address differ from byte mode.)

3.It is necessary to write the last SA twice to terminate SA loading operation for multi-block erase.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 15 AC Wa vef orms f or Data P olling Automatic Algorithm Operations

Q0 to Q6 =

Output Flag Q0 to Q6

Valid Data

Q7 Q7 = Valid

Data

Q0 to Q6

RY/BY

tDF

tOE

tCH

tOEH

tCE

tBUSY

*:Q7 = Valid Data (The device has completed the automatic operation).

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 16 AC W a vef orm f or Toggle Bit 1 during A utomatic Algorithm Operation

DATA Toggle

Data Toggle

Data Stop

Toggling Output

Valid

tAHTtASO tAHT tAS

tCEPH

tOEPH

tOEH

tDH tOE

tBUSY

tCE

tOEH

Toggle Data

RY/BY

Q6-Q2

Address

*: Q6 stops toggling (The Device has completed the Automatic operation).

SYMBOL DESCRIPTIONS MIN. MAX. UNIT

tAHT Address hold time from CE or OE high during toggle bit polling 0 ns

tASO Address setup time to OE low during toggle bit polling 1 5 n s

tCEPH Chip enable high during toggle bit polling

tOEPH Output enable high during toggle bit polling 2 0 ns

tOEH Output enable hold time 1 0 ns

tELFL/ELFH CE to BYTE switching low or high 5 ns

tFHQV BYTE switching high to output active 120 ns

tFLQZ BYTE switching low to output High-Z 3 0 ns

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 17 RY/BY Timing Diagram during Pr ogram/Erase Operation

Figure 18 RP/RY/BY Timing Diagram

Figure 19 Timing Diagram for W ord Mode Configuration

Data Output

(Q0 to Q7) Data Output

(Q0 to Q14)

Q15

A-1

tELFH tFHQV

Q15/A-1

Q0 to Q14

BYTE

tBUSY

Entire programming or

erase operations

The rising edge of the last write pulse

RY/BY

tRP

tREADY

tRB

RY/BY

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 21 A C Wa vef orm f or Gr oup Pr otection (Word Mode)

Figure 20 Timing Diagram for Byte Mode Configuration

Q15 A-1

Data Output

(Q0 to Q14) Data Output

(Q0 to Q7)

tELFL

tFLQZ

BYTE

Q0 to Q14

Q15/A-1

Address

Data

RY/BY

2AAH GA

(A12~A19)

55H 20H Status

GA : Group Address

Group Protuct Command Sequence (Last two cycles)

5th cycle 6th cycle

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 22 AC Waveform For Chip Unprotection (W ord Mode)

Address

Data

RY/BY

2AAH 555H

55H 40H Status

Chip Un-Protuct Command Sequence (Last two cycles)

5th cycle 6th cycle

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 23 ID Code Read Timing Wavef orm

VID

VIH

VIL

VIH

VIL

VCC

VIH

VIL

A2-A8

A10-A16

DATA

Q0-Q15

DATA OUT DATA OUT

C2H/00C2H 67H/68H(Byte)

0067H/0068H(Word)

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tOH

tDF

tOH

tOE

tCE

tACC tACC

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 24 Back to Bac k Read/Write Timing Diagram

Valid

Output Valid

Input Valid

Output Valid

Output

Valid

Input Status

BA1 BA2

(555H) BA1 BA2

(PA) BA1 BA2

(PA)

tRC

tRCtRCtRC tWC tWC

Read

Command

Read

Read Command

tAS tAH tACC

tCE

tOE

tGHWL tWP tOEH tDF

tDS tDH tDF

tAHT tAS

tCEPH

Output

Address

NOTE : This is example of read for Bank 1 and Embedded Alogorithm (Program) for Bank 2.

BA1 :Address of Bank 1.

BA2 : Address of Bank 2.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Figure 25 Q2 Vs Q6

Enter

Embedded

Erasing Erase

Suspend

Enter

Suspend

Program Erase

Resume

Erase Erase

Complete

Erase

Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Toggle

Q2 and Q6

with OE or CE

NOTE : Q2 toggles only when read at an address within an erasing or erase-suspended block.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

RATING VALUE

Ambient T emperature 0°C to 70°C (Comm.)

-40°C to 85°C (Ind.)

Vcc Supply Voltage 2.7V to 3.0V

T able 9 ERASE AND PROGRAMMING PERFORMANCE (1) (2)

LIMITS

PARAMETER MIN. TYP.(3) MAX. UNITS

Single/Block Erase Time 20 1 6 0 ms

Multi Block Er ase Time 50 400 ms

Chip Erase Time 50 400 ms

Page Programming Time 4 120 ms

Chip Programming Time 6 4 192 sec.

Erase/Program Cycles 100,000 Cycle

MIN. MAX. UNITS

Input Voltage with respect to GND on all pins except I/O pins -1.0 10.5 V

Input Voltage with respect to GND on I/O pins -1.0 Vcc+1.0 V

Current -100 +100 mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

Table 10 LATCHUP CHARACTERISTICS

Table 11 ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature -40°C to 85°C

Storage T emperature -65°C to 125°C

Applied Input Voltage -0.5V to Vcc + 4.5

Applied Output Voltage -0.5V to Vcc +0.6

Vcc to Ground P otential -0.5V to 4.5V

A9,RP,WP -0.5V to 12.5V

Table 12 OPERATING RANGES

Note: 1.Sampled, not 100% tested.

2.Excludes external system level over head

3.Typical values measured at 25 °C , nominal voltage.

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

Or dering Information

P art No . Access Temperature Pac kage

Time(ns) Range Type Ball Type Ball Pitch

MX29VW160TTC-90 90 Comm. 48 Pin TSOP

MX29VW160TTI-90 90 Ind. 48 Pin TSOP

MX29VW160TXBC-90 9 0 Comm. 48 Ball CSP BGA 0.80mm

MX29VW160TXBI-90 9 0 Ind. 48 Ball CSP BGA 0.80mm

Note:

1. T op Boot Block as an sample.For Bottom Boot Block ones,MX29VW160TXXX will be changed to MX29VW160BXXX)

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

PACKAGE INFORMATION

48-PIN TSOP

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

48-Ball CSP

MX29VW160T/B

P/N:PM0567 REV. 0.9.4, JUN. 06, 2001

REVISION HISTORY

Revision Description Page Date

0.3 CSP package size:7mmx12mm ---> 8mmx13mmx1.2mm P3 NO V/04/1998

Add in ICC6:Vcc Read/Erase Current P25

Remov e tBA CC & tBHZ P25

Remov e LGA Package P41

0.4 Change Sector structure of the 2Mb-Bank from 16KBx4+ P1, 4, 5, 8 NOV/19/1998

8KBx8+32KBx4 to 8KBx8+64KBx1

Add in WP pin P1, 3, 5, 6, 14, 20

Change VIP range from 9.5V~10.5V to 8.5V~10.5V P6, 14, 15, 25

0.5 Vcc r ange change to 2.25V~3.0V P1, 2, 3, 40 NO V/27/1998

0.6 Change Group Addr.: A12~A19 P8, 15, 17, 18, 35 DEC/03/1998

Correct ID data P11

0.7 Block architecture description correction P2 FEB/12/1999

0. 8 Modify typing P4, 5,9, 11,1 3,1 6 MAY/17/1999

Modify AC Characteristic description P28,29,32,33,37

Modify Erase/Program Performance P40

Modify Absolute Maximun Rating P40

Remove MX29VW160TXAC-12/TXAI-12 P41

0. 9 Update the fast access speed from 120ns to 90ns P1,2 MAR/22/2000

Remove the "byte program" words P8,30,40

To added RWW erase/program test Algorithm P26,27

To added tBUSY/tREADY timing at AC Characteristics Table P2 9

Content Change Group unprotect--->Chip unprotect P15,16,18,36

0.9.1 Add Package Information P42,43 OCT/30/2000

0.9.2 Modify 48-Pin CSP P ackage Information P43 NOV/20/2000

0.9.3 Modify Table 7. AC Characteristics--tACC:120ns-->90ns P26 FEB/23/2001

tCE:120ns-->90ns

Modify Table 8. AC Characteristics--tWC:120ns-->90ns P29

tRC:120ns-->90ns

0.9.4 1.Modify Extented Single-supply voltage range from 2.25 to P1,2,40 JUN/06/2001

3.0V --> from 2.7 to 3.0V

2.Modify Test Specifications P2 7

3.Modify Figure 10. Switching Test Waveforms P28

4. Modify P ackage Inf ormation P42,43

MX29VW160T/B

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