IPU06N03LB IPS06N03LB
OptiMOS®2 Power-Transistor
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target applications
• N-channel - Logic level
• Excellent gate charge x RDS(on) product (FOM)
• Very low on-resistance RDS(on)
• Superior thermal resistance
• 175 °C operating temperature
• dv/dt rated
• Pb-free lead plating; RoHS compliant
Maximum ratings, at Tj=25 °C, unless otherwise specified
Parameter Symbol Conditions Unit
Continuous drain current IDTC=25 °C2) 50 A
TC=100 °C 50
Pulsed drain current ID,pulse TC=25 °C3) 200
Avalanche energy, single pulse EAS ID=50 A, RGS=25 210 mJ
Reverse diode dv/dtdv/dt
ID=50 A, VDS=20 V,
di/dt=200 A/µs,
Tj,max=175 °C
6 kV/µs
Gate source voltage4) VGS ±20 V
Power dissipation Ptot TC=25 °C 94 W
Operating and storage temperature Tj, Tstg -55 ... 175 °C
IEC climatic category; DIN IEC 68-1 55/175/56
1) J-STD20 and JESD22
Value
VDS 30 V
RDS(on),max 5.8 m
ID50 A
Product Summary
PG-TO251-3PG-TO251-3-11
Type Package Marking
IPU06N03LB PG-TO251-3 06N03LB
IPS06N03LB PG-TO251-3-11 06N03LB
Rev. 0.4 page 1 2008-04-23
IPU06N03LB IPS06N03LB
Parameter Symbol Conditions Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case RthJC - - 1.6 K/W
SMD version, device on PCB RthJA minimal footprint - - 62
6 cm2 cooling area5) --40
Electrical characteristics, at Tj=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V(BR)DSS VGS=0 V, ID=1 mA 30 - - V
Gate threshold voltage VGS(th) VDS=VGS, ID=40 µA 1.2 1.6 2
Zero gate voltage drain current IDSS
VDS=30 V, VGS=0 V,
Tj=25 °C - 0.1 1 µA
VDS=30 V, VGS=0 V,
Tj=125 °C - 10 100
Gate-source leakage current IGSS VGS=20 V, VDS=0 V - 10 100 nA
RDS(on) VGS=4.5 V, ID=50 A - 7.3 9.1 m
VGS=10 V, ID=50 A - 4.9 5.8
Gate resistance RG- 1.2 -
Transconductance gfs
|VDS|>2|ID|RDS(on)max,
ID=50 A 41 83 - S
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Values
2) Current is limited by bondwire; with an RthJC=1.6 K/W the chip is able to carry 95 A.
3) See figure 3
4) Tj,max=150 °C and duty cycle D<0.25 for VGS<-5 V
Rev. 0.4 page 2 2008-04-23
IPU06N03LB IPS06N03LB
Parameter Symbol Conditions Unit
min. typ. max.
Dynamic characteristics
Input capacitance Ciss - 2400 3200 pF
Output capacitance Coss - 860 1150
Reverse transfer capacitance Crss - 110 170
Turn-on delay time td(on) - 7 10 ns
Rise time tr-69
Turn-off delay time td(off) -2740
Fall time tf- 4.2 6.3
Gate Char
g
e Characteristics6)
Gate to source charge Qgs - 7.4 9.9 nC
Gate charge at threshold Qg(th) - 3.9 5.1
Gate to drain charge Qgd - 4.9 7.3
Switching charge Qsw - 8.4 12
Gate charge total Qg-1925
Gate plateau voltage Vplateau - 3.1 - V
Gate charge total, sync. FET Qg(sync)
VDS=0.1 V,
VGS=0 to 5 V -1622nC
Output charge Qoss VDD=15 V, VGS=0 V -1926
Reverse Diode
Diode continous forward current IS- - 50 A
Diode pulse current IS,pulse - - 200
Diode forward voltage VSD
VGS=0 V, IF=50 A,
Tj=25 °C - 0.92 1.2 V
Reverse recovery charge Qrr
VR=15 V, IF=IS,
diF/dt=400 A/µs - - 10 nC
6) See figure 16 for gate charge parameter definition
TC=25 °C
Values
VGS=0 V, VDS=15 V,
f=1 MHz
VDD=15 V, VGS=10 V,
ID=25 A, RG=2.7
VDD=15 V, ID=25 A,
VGS=0 to 5 V
Rev. 0.4 page 3 2008-04-23
IPU06N03LB IPS06N03LB
1 Power dissipation 2 Drain current
Ptot=f(TC)ID=f(TC); VGS10 V
3 Safe operating area 4 Max. transient thermal impedance
ID=f(VDS); TC=25 °C; D=0 ZthJC=f(tp)
parameter: tpparameter: D=tp/T
1 µs
10 µs
100 µs
1 ms
10 ms
DC
1
10
100
1000
0.1 1 10 100
VDS [V]
ID [A]
limited by on-state
resistance
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
0.001
0.01
0.1
1
10
0000001
tp [s]
ZthJC [K/W]
0
10
20
30
40
50
60
70
80
90
100
0 50 100 150 200
TC [°C]
Ptot [W]
0
10
20
30
40
50
60
0 50 100 150 200
TC [°C]
ID [A]
10-6 10-5 10-4 10-3 10-2 10-1 100
Rev. 0.4 page 4 2008-04-23
IPU06N03LB IPS06N03LB
5 Typ. output characteristics 6 Typ. drain-source on resistance
ID=f(VDS); Tj=25 °C RDS(on)=f(ID); Tj=25 °C
parameter: VGS parameter: VGS
7 Typ. transfer characteristics 8 Typ. forward transconductance
ID=f(VGS); |VDS|>2|ID|RDS(on)max gfs=f(ID); Tj=25 °C
parameter: Tj
3 V 3.2 V 3.5 V 3.8 V 4.1 V
4.5 V
10 V
0
5
10
15
20
25
0 20 40 60 80 100 120
ID [A]
RDS(on) [m]
25 °C
175 °C
0
10
20
30
40
50
60
70
80
90
100
012345
VGS [V]
ID [A]
0
20
40
60
80
100
120
0 20406080
ID [A]
gfs [S]
2.8 V
3 V
3.2 V
3.5 V
3.8 V
4.1 V
4.5 V
10 V
-10
10
30
50
70
90
110
130
150
0123
VDS [V]
ID [A]
Rev. 0.4 page 5 2008-04-23
IPU06N03LB IPS06N03LB
9 Drain-source on-state resistance 10 Typ. gate threshold voltage
RDS(on)=f(Tj); ID=50 A; VGS=10 V VGS(th)=f(Tj); VGS=VDS
parameter: ID
11 Typ. Capacitances 12 Forward characteristics of reverse diode
C=f(VDS); VGS=0 V; f=1 MHz IF=f(VSD)
parameter: Tj
typ
98 %
0
1
2
3
4
5
6
7
8
9
10
11
12
-60 -20 20 60 100 140 180
Tj [°C]
RDS(on) [m]
40 µA
400 µA
0
0.5
1
1.5
2
2.5
-60 -20 20 60 100 140 180
Tj [°C]
VGS(th) [V]
Ciss
Coss
Crss
10
100
1000
10000
0 5 10 15 20 25 30
VDS [V]
C [pF]
25 °C
175 °C
25°C 98%
175°C 98%
1
10
100
1000
0.0 0.5 1.0 1.5 2.0
VSD [V]
IF [A]
Rev. 0.4 page 6 2008-04-23
IPU06N03LB IPS06N03LB
13 Avalanche characteristics 14 Typ. gate charge
IAS=f(tAV); RGS=25 VGS=f(Qgate); ID=25 A pulsed
parameter: Tj(start) parameter: VDD
15 Drain-source breakdown voltage 16 Gate charge waveforms
VBR(DSS)=f(Tj); ID=1 mA
5 V
15 V
20 V
0
2
4
6
8
10
12
0 10203040
Qgate [nC]
VGS [V]
20
22
24
26
28
30
32
34
36
38
-60 -20 20 60 100 140 180
Tj [°C]
VBR(DSS) [V]
V
GS
Q
gate
V
gs(th)
Q
g(th)
Q
gs
Q
gd
Q
sw
Q
g
25 °C
100 °C
150 °C
1
10
100
1 10 100 1000
tAV [µs]
IAV [A]
Rev. 0.4 page 7 2008-04-23
IPU06N03LB IPS06N03LB
PG-TO251-3: Outline
Packaging:
Rev. 0.4 page 8 2008-04-23
IPU06N03LB IPS06N03LB
PG-TO251-3-11: Outline
Packaging:
Rev. 0.4 page 9 2008-04-23
IPU06N03LB IPS06N03LB
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
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conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
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including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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Rev. 0.4 page 10 2008-04-23