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FEATURES APPLICATIONS
TPS732xx
GNDEN NR
IN OUT
VIN VOUT
Optional
Optional Optional
Typical Application Circuit for Fixed-Voltage Versions
DESCRIPTION
DCQ PACKAGE
SOT223
(TOP VIEW)
1 2 3 4 5
IN OUTGND
NR/FBEN
TAB IS GND
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
CAP-FREE NMOS 250-mA LOW DROPOUT REGULATORWITH REVERSE CURRENT PROTECTION
•Portable/Battery-Powered Equipment•Controlled Baseline
•Post-Regulation for Switching Supplies– One Assembly/Test Site, One Fabrication
•Noise-Sensitive Circuitry such as VCOsSite
•Point of Load Regulation for DSPs, FPGAs,•Extended Temperature Performance of
ASICs, and Microprocessors–55 °C to 125 °C•Enhanced Diminishing ManufacturingSources (DMS) Support•Enhanced Product-Change Notification•Qualification Pedigree
(1)
•Stable with No Output Capacitor or Any Valueor Type of Capacitor•Input Voltage Range: 1.7 V to 5.5 V•Ultralow Dropout Voltage:40 mV Typ at 250 mA•Excellent Load Transient Response—with orwithout Optional Output Capacitor•New NMOS Topology Provides Low Reverse
The TPS732xx family of low-dropout (LDO) voltageLeakage Current
regulators uses a new topology: an NMOS passelement in a voltage-follower configuration. This•Low Noise: 30 µV
RMS
Typ (10 kHz to 100 kHz)
topology is stable using output capacitors with low•0.5% Initial Accuracy
ESR and even allows operation without a capacitor.•1% Overall Accuracy (Line, Load, and
It also provides high reverse blockage (low reverseTemperature)
current) and ground pin current that is nearlyconstant over all values of output current.•Less Than 1 µA Max I
Q
in Shutdown Mode•Thermal Shutdown and Specified Min/Max
The TPS732xx uses an advanced BiCMOS processCurrent Limit Protection
to yield high precision while delivering low dropoutvoltages and low ground pin current. Current•Available in Multiple Output Voltage Versions
consumption, when not enabled, is under 1 µA and– Fixed Outputs of 1.2 V to 5 V
ideal for portable applications. The low output noise– Adjustable Outputs from 1.2 V to 5.5 V
(30 µV
RMS
with 0.1 µF C
NR
) is ideal for poweringVCOs. These devices are protected by thermal– Custom Outputs Available
shutdown and foldback current limit.
(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION RATINGS
(1)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
XX is the nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable
(3)
).TPS732 xxyyyz YYY is the package designator.Zis the package quantity.
(1) For the most current specification and package information, see the Package Option Addendum located at the end of this data sheet orsee the TI website at www.ti.com .(2) Output voltages from 1.2 V to 4.5 V in 50-mV increments are available through the use of innovative factory EEPROM programming;minimum order quantities may apply. Contact factory for details and availability.(3) For fixed 1.2 V operation, tie FB to OUT.
over operating junction temperature range unless otherwise noted
(1)
V
IN
range –0.3 V to 6 VV
EN
range –0.3 V to 6 VV
OUT
range –0.3 V to 5.5 VPeak output current Internally limitedOutput short-circuit duration IndefiniteContinuous total power dissipation See Dissipation Ratings TableAmbient temperature range, T
A
–55 °C to 150 °CStorage temperature range –65 °C to 150 °CESD rating, HBM 2 kVESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristicsis not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
T
A
≤25 °C T
A
= 70 °C T
A
= 85 °C T
A
= 125 °CDERATING FACTORBOARD PACKAGE R
ΘJC
R
ΘJA
POWER POWER POWER POWERABOVE T
A
= 25 °C
RATING RATING RATING RATING
Low-K
(2)
DBV 64 °C/W 255 °C/W 3.9 mW/ °C 450 mW 275 mW 215 mW 58 mWHigh-K
(3)
DBV 64 °/W 180 °C/W 5.6 mW/ °C 638 mW 388 mW 305 mW 83 mW
(1) See Power Dissipation in the Applications section for more information related to thermal design.(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch ×3 inch, two-layer board with 2-ounce copper traces on topof the board.(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch ×3 inch, multilayer board with 1-ounce internal power andground planes and 2-ounce copper traces on the top and bottom of the board.
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ELECTRICAL CHARACTERISTICS
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
Over operating temperature range (T
A
= –55 °C to +125 °C), V
IN
= V
OUT(nom)
+ 0.5 V
(1)
, I
OUT
= 10 mA, V
EN
= 1.7 V, andC
OUT
= 0.1 µF, unless otherwise noted. Typical values are at T
A
= 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range
(1)
1.7 5.5 VV
FB
Internal reference (TPS73201) T
A
= 25 °C 1.198 1.2 1.21 VOutput voltage range (TPS73201)
(2)
V
FB
5.5 – V
DO
VNominal T
A
= 25 °C±0.5%V
OUT
Accuracy
(1)
V
OUT
+ 0.5 V ≤V
IN
≤5.5 V;V
IN
, I
OUT
, and T –1% ±0.5% +1%10 mA ≤I
OUT
≤250 mA∆V
OUT
%/ ∆V
IN
Line regulation
(1)
V
OUT(nom)
+ 0.5 V ≤V
IN
≤5.5 V 0.01 %/V1 mA ≤I
OUT
≤250 mA 0.002∆V
OUT
%/ ∆I
OUT
Load regulation %/mA10 mA ≤I
OUT
≤250 mA 0.0005Dropout voltage
(3)V
DO
I
OUT
= 250 mA 40 150 mV(V
IN
= V
OUT
(nom) – 0.1V)Z
O
(DO) Output impedance in dropout 1.7 V ≤V
IN
≤V
OUT
+ V
DO
0.25 ΩI
CL
Output current limit V
OUT
= 0.9 ×V
OUT(nom)
250 425 600 mAI
SC
Short-circuit current V
OUT
= 0 V 300 mAI
REV
Reverse leakage current
(4)
(–I
IN
) V
EN
≤0.5 V, 0 V ≤V
IN
≤V
OUT
0.1 15 µAI
OUT
= 10 mA (I
Q
) 400 550I
GND
Ground pin current µAI
OUT
= 250 mA 650 950I
SHDN
Shutdown current (I
GND
) V
EN
≤0.5 V, V
OUT
≤V
IN
≤5.5 0.02 1 µAI
FB
FB pin current (TPS73201) .1 .45 µAf = 100 Hz, I
OUT
= 250 mA 58Power-supply rejection ratioPSRR dB(ripple rejection)
f = 10 kHz, I
OUT
= 250 mA 37C
OUT
= 10 µF, No C
NR
27 ×V
OUTOutput noise voltageV
N
µV
RMSBW = 10 Hz to 100 kHz
C
OUT
= 10 µF, C
NR
= 0.01 µF 8.5 ×V
OUT
V
OUT
= 3 V, R
L
= 30 Ωt
STR
Startup time 600 µsC
OUT
= 1 µF, C
NR
= 0.01 µFV
EN
(HI) Enable high (enabled) 1.7 V
IN
VV
EN
(LO) Enable low (shutdown) 0 0.5 VI
EN
(HI) Enable pin current (enabled) V
EN
= 5.5 V 0.02 0.1 µAShutdown, Temperature increasing 160T
SD
Thermal shutdown temperature °CReset, Temperature decreasing 140T
A
Operating ambient temperature –55 125 °C
(1) Minimum V
IN
= V
OUT
+ V
DO
or 1.7 V, whichever is greater.(2) TPS73201 is tested at V
OUT
= 2.5 V.(3) V
DO
is not measured for the TPS73214, TPS73215, or TPS73216, since minimum V
IN
= 1.7 V.(4) Fixed-voltage versions only; see the Applications section for more information.
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0
1
2
3
4
5
6
100 110 120 130 140 150 160
Continuous Tj(°C)
Years Estimated Life
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
A. T
j
=θ
JA
×W + T
A
(at standard JESD 51 conditions)
Figure 1. Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
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Servo
Error
Amp
Ref
27kΩ
8kΩ
Current
Limit
Charge
Pump
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80kΩ
VOUT
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
R1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
R2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1 + R2)/R2 × 1 .204;
R1R2 ≅ 19kΩ for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Charge
Pump
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80kΩ
8kΩ
27kΩ
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
FUNCTIONAL BLOCK DIAGRAMS
Figure 2. Fixed Voltage Version
Figure 3. Adjustable Voltage Version
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PIN ASSIGNMENTS
DCQ PACKAGE
SOT223
(TOP VIEW)
1 2 3 4 5
IN OUTGND
NR/FBEN
TAB IS GND
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
TERMINAL FUNCTIONS
TERMINAL
SOT23 SOT223 3 ×3 SON
DESCRIPTIONNAME (DBV) (DCQ) (DRB)PIN NO. PIN NO. PIN NO.
IN 1 1 8 Unregulated input supplyGND 2 3 4, Pad Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low putsEN 3 5 5 the regulator into shutdown mode. See the Shutdown section under ApplicationsInformation for more details. EN can be connected to IN if not used.Fixed voltage versions only—connecting an external capacitor to this pin bypassesNR 4 4 3
noise generated by the internal bandgap, reducing output noise to very low levels.Adjustable voltage version only—this is the input to the control loop error amplifier,FB 4 4 3
and is used to set the output voltage of the device.OUT 5 2 1 Output of the Regulator. There are no output capacitor requirements for stability.
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TYPICAL CHARACTERISTICS
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN −VOUT (V)
+125_C+25_C
−40_C
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
100
80
60
40
20
0
VDO (mV)
0 50 100 150 200 250
IOUT (mA)
+125_C
+25_C
−40_C
TPS73225DBV
100
80
60
40
20
0
VDO (mV)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73225DBV
IOUT = 250mA
30
25
20
15
10
5
0
Percent of Units (%)
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dVOUT/dT (ppm/_C)
IOUT = 10mA
All Voltage Versions
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
For all voltage versions at T
J
= 25 °C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted.
LOAD REGULATION LINE REGULATION
Figure 4. Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 6. Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
Figure 8. Figure 9.
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1000
900
800
700
600
500
400
300
200
100
0
IGND (µA)
0 50 100 150 200 250
IOUT (mA)
VIN = 5.5V
VIN = 4V
VIN = 2V
800
700
600
500
400
300
200
100
0
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
500
450
400
350
300
250
200
150
100
50
0
Current Limit (mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOUT (V)
TPS73233
ICL
ISC
1
0.1
0.01
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
VENABLE = 0.5V
VIN = VOUT + 0.5V
600
550
500
450
400
350
300
250
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN (V)
600
550
500
450
400
350
300
250
Current Limit (mA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 °C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 10. Figure 11.
CURRENT LIMIT vs V
OUT
GROUND PIN CURRENT in SHUTDOWN(FOLDBACK) vs TEMPERATURE
Figure 12. Figure 13.
CURRENT LIMIT vs V
IN
CURRENT LIMIT vs TEMPERATURE
Figure 14. Figure 15.
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40
35
30
25
20
15
10
5
0
PSRR (dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VIN −VOUT (V)
Frequency = 100kHz
COUT = 10µF
CNR = 0.01µF
10k10
90
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
100 1k 100k 1M 10M
Frequency (Hz)
IOUT = 1mA
COUT = 1µF
IOUT = Any
COUT = 0µF
VIN = VOUT + 1V
IOUT = 1mA
COUT = Any
IOUT = 1mA
COUT = 10µF
IOUT = 100mA
COUT = Any
IOUT = 100mA
COUT = 10µF
IO=100mA
CO=1µF
60
50
40
30
20
10
0
VN(RMS)
COUT (µF)
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 °C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted.
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs V
IN
– V
OUT
Figure 16. Figure 17.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITYC
NR
= 0 µF C
NR
= 0.01 µF
Figure 18. Figure 19.
RMS NOISE VOLTAGE vs C
OUT
RMS NOISE VOLTAGE vs C
NR
Figure 20. Figure 21.
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10µs/div
50mV/tick
50mV/tick
50mV/tick
50mA/tick
VIN = 3.8V COUT = 0µF
COUT = 1µF
COUT = 10µF
10mA
250mA
VOUT
VOUT
VOUT
IOUT
10µs/div
50mV/div
50mV/div
1V/div
VOUT
VOUT
VIN
IOUT = 250mA
5.5V
4.5V
dVIN
dt = 0.5V/µs
COUT = 0µF
COUT = 100µF
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
6
5
4
3
2
1
0
−1
−2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
IENABLE (nA)
−50 −25 0 25 50 75 100 125
Temperature (°C)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 °C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted.
TPS73233 TPS73233LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 22. Figure 23.
TPS73233 TPS73233TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 24. Figure 25.
TPS73233
POWER UP / POWER DOWN I
ENABLE
vs TEMPERATURE
Figure 26. Figure 27.
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60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5V
COUT = 0µF
R1= 39.2kΩ
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
IFB (nA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
5µs/div
100mV/div
100mV/div
VOUT
VOUT
VIN
4.5V
3.5V
COUT = 0µF
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
10µs/div
100mV/div
100mV/div
VOUT
VOUT
IOUT
250mA
10mA
COUT = 0µF
CFB = 10nF
R1= 39.2kΩ
COUT = 10µF
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
TYPICAL CHARACTERISTICS (continued)For all voltage versions at T
J
= 25 °C, V
IN
= V
OUT(nom)
+ 0.5 V, I
OUT
= 10 mA, V
EN
= 1.7 V, and C
OUT
= 0.1 µF, unless otherwisenoted.
TPS73201 TPS73201RMS NOISE VOLTAGE vs C
ADJ
I
FB
vs TEMPERATURE
Figure 28. Figure 29.
TPS73201 TPS73201LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 30. Figure 31.
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APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITOR
OUTPUT NOISE
TPS732xx
GNDEN NR
IN OUT
VIN VOUT
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional bypass
capacitor to reduce
output noise.
VN+32mVRMS (R1)R2)
R2+32mVRMS VOUT
VREF
(1)
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
(2)
TPS732xx
GNDEN FB
IN OUT
VIN VOUT
VOUT =×1.204
(R1+ R2)
R1
R1CFB
R2
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional capacitor
reduces output noise
and improves
transient response.
VN(mVRMS)+8.5ǒmVRMS
VǓ VOUT(V)
(3)
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
The TPS732xx belongs to a family of new generationLDO regulators that use an NMOS pass transistor to
REQUIREMENTSachieve ultra-low-dropout performance, reversecurrent blockage, and freedom from output capacitor
Although an input capacitor is not required forconstraints. These features, combined with low noise
stability, it is good analog design practice to connectand an enable input, make the TPS732xx ideal for
a 0.1 µF to 1 µF low ESR capacitor across the inputportable applications. This regulator family offers a
supply near the regulator. This counteracts reactivewide selection of fixed output voltage versions and
input sources and improves transient response,an adjustable output version. All versions have
noise rejection, and ripple rejection. A higher-valuethermal and over-current protection, including
capacitor may be necessary if large, fast rise-timefoldback current limit.
load transients are anticipated or the device islocated several inches from the power source.Figure 32 shows the basic circuit connections for thefixed voltage models. Figure 33 gives the
The TPS732xx does not require an output capacitorconnections for the adjustable output version
for stability and has maximum phase margin with no(TPS73201).
capacitor. It is designed to be stable for all availabletypes and values of capacitors. In applications whereV
IN
– V
OUT
< 0.5 V and multiple low ESR capacitorsare in parallel, ringing may occur when the product ofC
OUT
and total ESR drops below 50 n ΩF. Total ESRincludes all parasitic resistances, including capacitorESR and board, socket, and solder joint resistance.In most applications, the sum of capacitor ESR andtrace resistance will meet this requirement.
A precision band-gap reference is used to generatethe internal reference voltage, V
REF
. This reference isthe dominant noise source within the TPS732xx andFigure 32. Typical Application Circuit for
it generates approximately 32 µV
RMS
(10 Hz toFixed-Voltage Versions
100 kHz) at the reference output (NR). The regulatorcontrol loop gains up the reference noise with thesame gain as the reference voltage, so that the noisevoltage of the regulator is approximately given by:
Since the value of V
REF
is 1.2V, this relationshipreduces to:
for the case of no C
NR
.
An internal 27 k Ωresistor in series with the noisereduction pin (NR) forms a low-pass filter for theFigure 33. Typical Application Circuit for
voltage reference when an external noise reductionAdjustable-Voltage Versions
capacitor, C
NR
, is connected from NR to ground. ForC
NR
= 10 nF, the total noise in the 10 Hz to 100 kHzR
1
and R
2
can be calculated for any output voltage
bandwidth is reduced by a factor of ~3.2, giving theusing the formula shown in Figure 33 . Sample
approximate relationship:resistor values for common output voltages areshown in Figure 3 . For the best accuracy, make theparallel combination of R
1
and R
2
approximately 19kΩ.
for C
NR
= 10nF.
12
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BOARD LAYOUT RECOMMENDATION TO
TRANSIENT RESPONSE
INTERNAL CURRENT LIMIT
SHUTDOWN
dVńdt +VOUT
COUT 80kWøRLOAD
(4)
DROPOUT VOLTAGE
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
This noise reduction effect is shown as RMS Noise For large step changes in load current, theVoltage vs C
NR
in the Typical Characteristics section. TPS732xx requires a larger voltage drop from V
IN
toV
OUT
to avoid degraded transient response. TheThe TPS73201 adjustable version does not have the
boundary of this transient dropout region isnoise-reduction pin available. However, connecting a
approximately twice the dc dropout. Values of V
INfeedback capacitor, C
FB
, from the output to the FB
– V
OUT
above this line insure normal transientpin reduces output noise and improve load transient
response.performance.
Operating in the transient dropout region can causeThe TPS732xx uses an internal charge pump to
an increase in recovery time. The time required todevelop an internal supply voltage sufficient to drive
recover from a load transient is a function of thethe gate of the NMOS pass element above V
OUT
.
magnitude of the change in load current rate, theThe charge pump generates ~250 µV of switching
rate of change in load current, and the availablenoise at ~2 MHz; however, charge-pump noise
headroom (V
IN
to V
OUT
voltage drop). Undercontribution is negligible at the output of the regulator
worst-case conditions [full-scale instantaneous loadfor most values of I
OUT
and C
OUT
.
change with (V
IN
– V
OUT
) close to dc dropout levels],the TPS732xx can take a couple of hundredmicroseconds to return to the specified regulationIMPROVE PSRR AND NOISE
accuracy.PERFORMANCE
To improve ac performance such as PSRR, outputnoise, and transient response, it is recommended
The low open-loop output impedance provided by thethat the PCB be designed with separate ground
NMOS pass element in a voltage followerplanes for V
IN
and V
OUT
, with each ground plane
configuration allows operation without an outputconnected only at the GND pin of the device. In
capacitor for many applications. As with anyaddition, the ground connection for the bypass
regulator, the addition of a capacitor (nominal valuecapacitor should connect directly to the GND pin of
1µF) from the output pin to ground reducesthe device.
undershoot magnitude but increase duration. In theadjustable version, the addition of a capacitor, C
FB
,from the output to the adjust pin also improves thetransient response.The TPS732xx internal current limit helps protect theregulator during fault conditions. Foldback helps to
The TPS732xx does not have active pulldown whenprotect the regulator from damage during output
the output is overvoltage. This allows applicationsshort-circuit conditions by reducing current limit when
that connect higher voltage sources, such asV
OUT
drops below 0.5 V. See Figure 12 in the Typical
alternate power supplies, to the output. This alsoCharacteristics section for a graph of I
OUT
vs V
OUT
.
results in an output overshoot of several percent ifthe load current quickly drops to zero when acapacitor is connected to the output. The duration ofovershoot can be reduced by adding a load resistor.The Enable pin is active high and is compatible with
The overshoot decays at a rate determined by outputstandard TTL-CMOS levels. V
EN
below 0.5 V (max)
capacitor C
OUT
and the internal/external loadturns the regulator off and drops the ground pin
resistance. The rate of decay is given by:current to approximately 10 nA. When shutdowncapability is not required, the Enable pin can be
(Fixed voltage version)connected to V
IN
. When a pullup resistor is used,and operation down to 1.8 V is required, use pullupresistor values below 50 k Ω.
The TPS732xx uses an NMOS pass transistor toachieve extremely low dropout. When (V
IN
– V
OUT
) isless than the dropout voltage (V
DO
), the NMOS passdevice is in its linear region of operation and theinput-to-output resistance is the R
DS-ON
of the NMOSpass element.
13Submit Documentation Feedback
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dVńdt +VOUT
COUT 80kWø(R1)R2)øRLOAD
(5)
REVERSE CURRENT
POWER DISSIPATION
THERMAL PROTECTION
PD+(VIN *VOUT) IOUT
(6)
Package Mounting
TPS73201-EP , , TPS73215-EPTPS73216-EP , TPS73218-EP , TPS73225-EPTPS73230-EP , TPS73233-EP , TPS73250-EP
SGLS346 – JUNE 2006
(Adjustable voltage version) 35 °C above the maximum expected ambientcondition of your application. This produces aworst-case junction temperature of 125 °C at thehighest expected ambient temperature andworst-case load.
The internal protection circuitry of the TPS732xx hasThe NMOS pass element of the TPS732xx provides
been designed to protect against overloadinherent protection against current flow from the
conditions. It was not intended to replace properoutput of the regulator to the input when the gate of
heatsinking. Continuously running the TPS732xx intothe pass device is pulled low. To ensure that all
thermal shutdown will degrade device reliability.charge is removed from the gate of the passelement, the enable pin must be driven low beforethe input voltage is removed. If this is not done, the
The ability to remove heat from the die is different forpass element may be left on due to stored charge on
each package type, presenting differentthe gate.
considerations in the PCB layout. The PCB areaAfter the enable pin is driven low, no bias voltage is
around the device that is free of other componentsneeded on any pin for reverse current blocking. Note
moves the heat from the device to the ambient air.that reverse current is specified as the current
Performance data for JEDEC low-K and high-Kflowing out of the IN pin due to voltage applied on
boards are shown in the Power Dissipation Ratingsthe OUT pin. There will be additional current flowing
table. Using heavier copper increases theinto the OUT pin due to the 80-k Ωinternal resistor
effectiveness in removing heat from the device. Thedivider to ground (see Figure 2 and Figure 3 ).
addition of plated through-holes to heat-dissipatinglayers also improves the heat-sink effectiveness.For the TPS73201, reverse current may flow whenV
FB
is more than 1 V above V
IN
.
Power dissipation depends on input voltage and loadconditions. Power dissipation is equal to the productof the output current times the voltage drop acrossthe output pass element (V
IN
to V
OUT
):Thermal protection disables the output when thejunction temperature rises to approximately 160 °C,allowing the device to cool. When the junction
Power dissipation can be minimized by using thetemperature cools to approximately 140 °C, the
lowest possible input voltage necessary to assureoutput circuitry is again enabled. Depending on
the required output voltage.power dissipation, thermal resistance, and ambienttemperature, the thermal protection circuit may cycleon and off. This limits the dissipation of the regulator,protecting it from damage due to overheating.
Solder pad footprint recommendations for theTPS732xx are presented in Application BulletinAny tendency to activate the thermal protection
Solder Pad Recommendations for Surface-Mountcircuit indicates excessive power dissipation or an
Devices (AB-132), available from the Texasinadequate heatsink. For reliable operation, junction
Instruments web site at www.ti.com.temperature should be limited to 125 °C maximum.To estimate the margin of safety in a completedesign (including heatsink), increase the ambienttemperature until the thermal protection is triggered;use worst-case loads and signal conditions. For goodreliability, thermal protection should trigger at least
14
Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS73201MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73215MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73216MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73218MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73225MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73230MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73233MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73250MDBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-01XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-02XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-03XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-04XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-05XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-06XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-07XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/06644-08XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2009
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73201-EP, TPS73215-EP, TPS73216-EP, TPS73218-EP, TPS73225-EP, TPS73230-EP, TPS73233-EP,
TPS73250-EP :
•Catalog: TPS73201,TPS73215,TPS73216,TPS73218,TPS73225,TPS73230,TPS73233,TPS73250
•Automotive: TPS73201-Q1,TPS73225-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73201MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73215MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73216MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73218MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73225MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73230MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73233MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73250MDBVREP SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73201MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73215MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73216MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73218MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73225MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73230MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73233MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73250MDBVREP SOT-23 DBV 5 3000 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 2
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