THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Features
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance up to
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
D14-Bit Resolution
D3- and 8-MSPS Speed Grade
DDifferential Nonlinearity (DNL) ±0.6 LSB Typ
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DIntegral Nonlinearity (INL) ±1.5 LSB Typ
DInternal Reference
DDifferential Inputs
DProgrammable Gain Amplifier
DμP-Compatible Parallel Interface
DTiming Compatible With TMS320C6000 DSP
D3.3-V Single Supply
DPower-Down Mode
DMonolithic CMOS Design
Applications
DxDSL Front Ends
DCommunication
DIndustrial Control
DInstrumentation
DAutomotive and Selected Military
14 15
WR
OE
DGND
DGND
CLK
DVDD
DVDD
D0
D1
D2
DVDD
DGND
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
IN−
AVDD
VBG
CML
REF+
REF−
AGND
AGND
DGND
OV
D13
D12
17 18 19 20
A0
A1
NC
NC
47 46 45 44 4348 42
IN+
AV
AGND
AGND
AGND
D5
D4
D3
DGND
D9
D8
D7
D6
40 39 3841
21 22 23 24
37
13
CS
D11
D10
PHP PACKAGE
(TOP VIEW)
DD
AVDD
DVDD
DVDD
DVDD
NC − No internal connection
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The THS1408 is a 14-bit, 3/8-MSPS single-supply analog-to-digital converter (ADC), with an internal reference,
differential inputs, programmable input gain, and an on-chip sample and hold amplifier.
Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The
THS1408 is designed for use with 3.3-V systems, and with a high-speed μP-compatible parallel interface, making
it the first choice for solutions based on high-performance DSPs like the TI TMS320C6000 series.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°CPQFP − PHP THS1408MPHPEP THS1408ME
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional block diagram
PGA
0..7 dB
REF
14-Bit
ADC Buffer
14 15
CONTROL
LOGIC
REF+
REF−
IN+
IN−
D[13:0] + OV bit
A[1:0]
6
CLK
1.5 V
BG
VBG
CS
WR
OE
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
A[1:0] 40, 41 IAddress input
AGND 7,8, 44,
45, 46
Analog ground
AVDD 2, 43, 47 Analog power supply
CLK 32 I Clock input
CML 4 Reference midpoint. This pin requires a 0.1-μF capacitor to AGND.
CS 37 I Chip select input. Active low
DGND 9, 15, 25,
33, 34
Digital ground
DVDD 14, 20, 26,
30, 31, 42
Digital power supply
D[13:0] 11, 12, 13,
16, 17, 18,
19, 21, 22,
23, 24, 27,
28, 29
I/O Data inputs/outputs
NC 38, 39 No connection, do not use. Reserved
IN+ 48 I Positive differential analog input
IN− 1 I Negative differential analog input
OE 35 I Output enable. Active low
OV 10 O Out of range output
REF+ 5 O Positive reference output. This pin requires a 0.1-μF capacitor to AGND.
REF− 6 O Negative reference output. This pin requires a 0.1-μF capacitor to AGND.
VBG 3 I Reference input. This pin requires a 1-μF capacitor to AGND.
WR 36 I Write signal. Active low
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, (AVDD to AGND) 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, (DVDD to DGND) 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VBG − 0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range − 0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range − 0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: Q suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
TYP UNIT
Thermal resistance, junction-to-ambient, ΘJA 28.8 °C/W
Thermal resistance, junction-to-case, ΘJC 0.79 °C/W
†Thermal resistance is modeled data, is not production tested, and is given for informational purposes only.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DVDD 3 3.3 3.6 V
High level digital input, VIH 2 3.3 V
Low level digital input, VIL 00.8 V
Load capacitance, CL5 15 pF
Clock frequency, fCLK 0.1 8 8 MHz
Clock duty cycle 45% 50% 55%
Operating free air temperature
Q suffix −40 25 125
°C
Operating free-air temperature M suffix −55 25 125 °C
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
IDDA Analog supply current AVDD = 3.6 V 81 90 mA
IDDD Digital supply current DVDD = 3.6 V 5 10 mA
Power AVDD = DVDD = 3.6 V 270 360 mW
Power down current 20 μA
DC Characteristics
Resolution 14 Bits
DNL Differential nonlinearity ±0.6 ±1 LSB
THS1408 at 3 MSPS
Best fit
±2
±4
INL
THS1408 at 3 MSPS Best fit ±2±4
LSB
INL Integral nonlinearity THS1408 at 8 MSPS Best fit ±3.5 ±10.5 LSB
Offset error IN+ = IN−, PGA = 0 dB 0.3 %FSR
Gain error PGA = 0 dB 1.75 %FSR
AC Characteristics
ENOB Effective number of bits 11.2 11.5 Bits
fi = 100 kHz −81
THD Total harmonic distortion fi = 1 MHz −78 dB
THD
Total
harmonic
distortion
fi = 4 MHz −77
dB
fi = 100 kHz 72
SNR Signal-to-noise ratio fi = 1 MHz 70 72 dB
SNR
Signal to noise
ratio
fi = 4 MHz 71
dB
fi = 100 kHz 70
SINAD Signal-to-noise ratio + distortion fi = 1 MHz 69 70 dB
SINAD
Signal to noise
ratio
+
distortion
fi = 4 MHz 70
dB
fi = 100 kHz 80
SFDR Spurious free dynamic range fi = 1 MHz 71 80 dB
SFDR
Spurious
free
dynamic
range
fi = 4 MHz 80
dB
Analog input bandwidth 140 MHz
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 3.3 V (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Voltage
VBG
Bandgap voltage, internal mode 1.425 1.5 1.575 V
VBG Input impedance 40 kΩ
Positive reference voltage, REF+ 2.5 V
Negative reference voltage, REF− 0.5 V
Reference difference, ΔREF, REF+ − REF− 2 V
Accuracy, internal reference 5%
Temperature coefficient 40 ppm/°C
Voltage coefficient 200 ppm/V
Analog Inputs
Positive analog input, IN+ 0AVDD V
Negative analog input, IN− 0AVDD V
Analog input voltage difference ΔAin = IN+ − IN−, Vref = REF+ − REF− −Vref Vref V
Input impedance 25 kΩ
PGA range 0 7 dB
PGA step size 1 dB
PGA gain error ±0.25 dB
Digital Inputs
VIH High-level digital input 2 V
VIL Low-level digital input 0.8 V
Input capacitance 5 pF
Input current ±1μA
Digital Outputs
VOH High-level digital output IOH = 50 μA 2.6 V
VOL Low-level digital output IOL = 50 μA 0.4 V
IOZ Output current, high impedance ±10 μA
Clock Timing (CS low)
fCLK Clock frequency 0.1†8 8 MHz
tdOutput delay time 25 ns
Latency 9.5 Cycles
†This parameter is not production tested.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
sample timing
The core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results appear on the
digital output 9.5 clock cycles after the input signal was sampled.
S9 S10
S11 S12
CLK
Data
Out
Analog
Input
C1 C2 C3
tw(CLK) tw(CLK)
td
Figure 1. Sample Timing
The parallel interface of the ADC features 3-state buffers, making it possible to directly connect it to a data bus. The
output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and
the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available
at address 0.
The timing of the control signals is described in the following sections.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
read timing (15-pF load)
PARAMETER MIN TYP MAX UNIT
tsu(OE−ACS) Address and chip select setup time 4 ns
ten Output enable 15 ns
tdis Output disable 10 ns
th(A) Address hold time 1 ns
th(CS) Chip select hold time 0 ns
NOTE: All timing parameters refer to a 50% level.
DATA
ADDRESS
CS
OE
D[13:0]
O V
A[1:0] X X
tsu(OE−ACS) ten
th(CS)
tdis
th(A)
Figure 2. Read Timing
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
write timing (15-pF load)
PARAMETER MIN TYP MAX UNIT
tsu(WE−CS) Chip select setup time 4 ns
tsu(DA) Data and address setup time 29 ns
th(DA) Data and address hold time 0 ns
th(CS) Chip select hold time 0 ns
twH(WE) Write pulse duration high 15 ns
NOTE: All timing parameters refer to a 50% level.
DATA
ADDRESS
CS
WE
D[13:0]
AX X
X
X
tsu(WE−CS) tsu(DA)
th(CS)
th(DA)
Figure 3. Write Timing
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
268
270
272
274
276
278
280
282
284
0.1 1 10
Power − mW
f − Frequency − MHz
POWER
vs
FREQUENCY
Figure 4
0
10
20
30
40
50
60
70
80
90
0 50 100 150 200 250 300
− Supply Current − mA
t − Time − ns
SUPPLY CURRENT
vs
TIME
ICC
Figure 5
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−100
−140
0.1 0.4 0.7 1
Output − dB
−40
−20
f − Frequency − MHz
FAST FOURIER TRANSFORM
0
1.3
−60
−80
−120
fs = 3 MSPS,
fI = 1 MHz,
−1 dB
Figure 6
−60
−140
0.1 0.4 0.7 1 1.6 1.9 2.5
Output − dB
−40
−20
f − Frequency − MHz
FAST FOURIER TRANSFORM
0
2.8 3.1 3.7 4
−80
−100
−120
1.3 2.2 3.4
fs = 8 MSPS,
fI = 1 MHz,
−1 dB
Figure 7
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−0.5
−2
0 2048 4096 6144 8192 10240
INL − Integral Nonlinearity − LSB
1
1.5
Samples
INTEGRAL NONLINEARITY
2
12288 14336 16384
0.5
0
−1
−1.5
fs = 3 MSPS
Figure 8
−2
−4
2
3
4
1
0
−1
−3
0 2048 4096 6144 8192 10240
INL − Integral Nonlinearity − LSB
Samples
INTEGRAL NONLINEARITY
12288 14336 16384
fs = 8 MSPS
Figure 9
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−0.2
−1
0 2048 4096 6144 8192 10240
DNL − Differential Nonlinearity − LSB
0.6
0.8
Samples
DIFFERENTIAL NONLINEARITY
1
12288 14336 16384
0.4
0.2
0
−0.4
−0.6
−0.8
fs = 3 MSPS
Figure 10
−0.2
−1
0 2048 4096 6144 8192 10240
DNL − Differential Nonlinearity − LSB
0.6
0.8
Samples
DIFFERENTIAL NONLINEARITY
1
12288 14336 16384
0.4
0.2
0
−0.4
−0.6
−0.8
fs = 8 MSPS
Figure 11
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
−90
−88
−86
−84
−82
−80
−78
−76
−74
−72
−70
10 100 1000 1500
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
fs = 3 MSPS,
fI at −1 dB
Figure 12
−90
−88
−86
−84
−82
−80
−78
−76
−74
−72
−70
10 100 1000 4000
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
fs = 8 MSPS,
fI at −1 dB
Figure 13
60
62
64
66
68
70
72
74
76
78
80
10 100 1000 1500
SNR − Signal-to-Noise Ratio − dB
f − Frequency − Hz
SIGNAL-TO-NOISE RATIO
vs
FREQUENCY
fs = 3 MSPS,
fI at −1 dB
Figure 14
60
62
64
66
68
70
72
74
76
78
80
10 100 1000 4000
SNR − Signal-to-Noise Ratio − dB
f − Frequency − Hz
SIGNAL-TO-NOISE RATIO
vs
FREQUENCY
fs = 8 MSPS,
fI at −1 dB
Figure 15
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
registers
The device contains several registers. The A register is selected by the values of bits A1 and A0:
A1 A0 Register
0 0 Conversion result
0 1 PGA
1 0 Offset
1 1 Control
Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default
values (where applicable) show the state after a power-on reset.
Table 1. Conversion Result Register, Address 0, Read
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function MSB ... … … … … … … … … … … … LSB
The output can be configured for two’s complement or straight binary format (see D11/control register).
The output code is given by:
2s complement: Straight binary:
−8192 at ΔIN = −ΔREF 0 at ΔIN = −ΔREF
0 at ΔIN = 0 8192 at ΔIN = 0
8191 ΔIN = −ΔREF − 1 LSB 16383 at ΔIN = −ΔREF − 1 LSB
1LSB+2DREF
16384
Table 2. PGA Gain Register, Address 1, Read/Write
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X X X X X X X G2 G1 G0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The PGA gain is determined by writing to G2−0.
Gain (dB) = 1dB × G2−0. max = 7dB. The range of G2−0 is 0 to 7.
Table 3. Offset Register, Address 2, Read/Write
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X X MSB … … … … … … LSB
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 4. Control Register, Address 3, Read
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES
Table 5. Control Register, Address 3, Write
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWD: Power down 0 = normal operation 1 = power down
REF: Reference select 0 = internal reference 1 = external reference
FOR: Output format 0 = straight binary 1 = 2s complement
TM2−0: Test mode 000 = normal operation
001 = both inputs = REF−
010 = IN+ at Vref/2, IN− at REF−
011 = IN+ at REF+, IN− at REF−
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF−, IN− at Vref/2
111 = IN+ at REF−, IN− at REF+
OF: Offset correction 0 = enable 1 = disable
RES Reserved Must be set to 0.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving the analog input
The ADC has a fully differential input. A differential input is advantageous with respect to SNR, SFDR, and THD
performance because the signal peak-to-peak level is 50% of a comparable single-ended input.
There are three basic input configurations:
DFully differential
DTransformer coupled single-ended to differential
DSingle-ended
fully differential configuration
In this configuration, the ADC converts the difference (ΔIN) of the two input signals on IN+ and IN−.
100 pF IN+
IN−
22 Ω
100 pF
22 Ω
THS1408
Figure 16. Differential Input
The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve
as first order low pass filters to attenuate out of band noise.
The input range on both inputs is 0 V to AVDD. The full-scale value is determined by the voltage reference. The
positive full-scale output is reached, if ΔIN equals ΔREF, the negative full-scale output is reached, if ΔIN equals
−ΔREF.
ΔIN [V] OUTPUT
−ΔREF − full scale
0 0
ΔREF + full scale
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
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APPLICATION INFORMATION
transformer coupled single-ended to differential configuration
If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled.
The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus increasing
the ADC ac performance.
100 pF IN+
IN− CML
R
100 pF
22 Ω
22 Ω
+1 μF 0.1 μF
THS1408
Figure 17. Transformer Coupled
The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output:
IN [VPEAK]OUTPUT [PEAK]
−ΔREF − full scale†
0 0
ΔREF + full scale†
†n = 1 (winding ratio)
The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R
= n2 Rs, where Rs is the source impedance and n is the transformer winding ratio.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
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APPLICATION INFORMATION
single-ended configuration
In this configuration, the input signal is level shifted by ΔREF/2.
IN+
IN−
REF+
REF−
+
−
10 kΩ
100 pF
100 pF
10 kΩ
22 Ω
10 kΩ10 kΩ
10 kΩ + 10 kΩ
THS1408
Figure 18. Single-Ended With Level Shift
The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale output:
ΔIN+ [V] OUTPUT
−ΔREF − full scale
0 0
ΔREF + full scale
Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be
trimmed by varying the values of the resistors.
Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve (best
linearity around zero) and, therefore, may introduce unacceptable distortion. For ac signals, an alternative is
described in the following section.
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
AC-coupled single-ended configuration
If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 4 is not
necessary.
IN+
IN−
REF+
REF−
+
−10 nF
10 kΩ
10 kΩ
10 kΩ
10 kΩ
100 pF
100 pF
22 Ω
10 kΩ10 kΩ
THS1408
Figure 19. Single-Ended With Level Shift
Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within the
linear region of the op-amp transfer function, thus increasing the overall ac performance.
IN [VPEAK]OUTPUT [PEAK]
−ΔREF − full scale
0 0
ΔREF + full scale
Compared to the transformer-coupled configuration, the swing on IN− is twice as big, which can decrease the ac
performance (SNR, SFD, and THD).
THS1408-EP
14-BIT, 3/8 MSPS DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE AND PGA
SGLS129B − JULY 2002 − REVISED FEBRUARY 2010
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal/external reference operation
The THS1408 ADC can either be operated using the built-in band gap reference or using an external precision
reference in case very high dc accuracy is needed.
The REF+ and REF+ outputs are given by:
REF )+ VBGǒ1)2
3Ǔand REF– +VBGǒ1– 2
3Ǔ
If the built-in reference is used, VBG equals 1.5 V, which results in REF+ = 2.5 V, REF− = 0.5 V and ΔREF = 2 V.
The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band gap
reference is then disconnected and can be substituted by a voltage on the VBG pin.
programmable gain amplifier
The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing to the
PGA gain register (address 1). The range is 0 to 7 dB in steps of one dB.
out of range indication
The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs
exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data
outputs and therefore subject to the same pipeline delay.
offset compensation
With the offset register it is possible to automatically compensate system offset errors, including errors caused by
additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register), the
value in the offset register (address 2) is automatically subtracted from the output of the ADC.
In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0 must
be read by the host processor and written to the offset register (address 2).
test modes
The ADC core operation can be tested by selecting one of the available test modes (see control register description).
The test modes apply various voltages to the differential input depending on the setting in the control register.
digital I/O
The digital inputs and outputs of the THS1408 ADC are 3-V CMOS compatible. In order to avoid current feed back
errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series resistors (100
Ω) on the digital outputs can improve the performance by limiting the current during output transitions.
The parallel interface of the THS1408 ADC features 3-state buffers, making it possible to directly connect it to a data
bus. The output buffers are enabled by driving the OE input low.
Refer to the read and write timing diagrams in the parameter measurement information section for information on
read and write access.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS1408MPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
V62/03608-03XE ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS1408-EP :
•Catalog: THS1408
•Military: THS1408M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 8-Feb-2010
Addendum-Page 1
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