CY7C1370A-100AC - Cypress Semiconductor Corp.

PRELIMINARY

512Kx36/1Mx18 Pipelined SRAM with NoBL™ Architecture

CY7C1370A

CY7C1372A

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

July 6, 2000

Features

• Zero Bus Latency, no dead cycles between write and

read cycles

• F ast clock speed: 167, 150, 133, and 100 MHz

• Fast access time: 3.4, 3.8, 4.2, 5.0 ns

• Internally synchronized reg ist ered output s eli m inate

the need to cont rol OE

• Single 3.3V –5% and +5% power supply VDD

• Sep arate VDDQ for 3.3V or 2.5V I/O

• Single WE (READ/WRITE) control pin

• Positive clock-edge triggered, address, data, and con-

trol signal registers for f ull y pipel ined applications

• Interleaved or linear 4-word b urst cap ability

• Individual byte write (BWSa - BW Sd) control (may be

tied L OW)

•CEN

pin to enabl e clock and suspend operations

• Three chip enables for simple depth expansion (TQFP

P ackage Onl y)

• JTAG boundary scan (B GA P ackage Only)

• Available in 119-ball bump BGA and 100-pin TQFP pack-

ages

Functional Description

The CY7C1370A and CY7C1372A SRAMs are designed to

eliminate dead cycles when transitions from READ to WRITE

or vi ce ver sa. These SRAMs are opt imized f or 100 percent bus

utilization and achieve Zero Bus Latency. They integrate

524,288x36 and 1,048,576x18 SRAM cells, respectively, with

adv ance d sy nchronou s periphe r al ci rcuit ry and a 2- bit counter

for internal burst operation. The Synchronous Burst SRAM

family employs high-speed, low-power CMOS designs using

adv ance d tripl e-la y er pol ysili con, doubl e-lay er metal technol o-

g y. Each memory cell cons ists of fou r transi stors and two hi gh-

valued resistors.

All synchronous inputs are gated by register s controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs i nclude all addresses, all data inputs, depth-expansion

Chip Enables (CE1, CE2, and CE3), cycle start input (AD V/LD),

Clock Enable (CEN), Byte Write Enables (BWSa, BWSb,

BWSc, and BW Sd), a nd Read-W rite Contro l (WE). B WSc and

BWSd apply to CY7C1370A only.

Address and control signals are applied to the SRAM during

one clock cycle, and t wo cycles later, its associated data oc-

curs, either read or write.

A Clock Enable (CEN) pin allows operation of the

CY7C1370A/CY7C1372A to be suspended as long as neces -

sary. All synchronous inputs are ignored when CEN is HIGH

and the internal device r egisters will hol d their pre vious v alues .

There are three chip enable pins (CE1, CE2, CE3) that allow

the user to deselect the device when desired. If any one of

these three ar e not active wh en AD V/LD is LOW , no new mem-

or y operation can be initiated and any burst cycle in progress

is stopped. Howe ver , any pending data transf ers (read or write)

will be completed. The data bus will be in high-impedance

state two cycles after the chip is deselected or a wri te cycle is

initiated.

The CY7C 1370A and CY7C1 372A h a ve an on- chip 2- bit burs t

counter. In the burst mode, the CY7C1370A and CY7C1372A

provide four cycles of data for a single address presented to

the SRAM. The order of the burst sequence is defined by the

MODE input pin. The MODE pin selects between linear and

interlea ved burst sequence. T he AD V/LD si gnal is use d to load

a new external address (ADV/LD=LOW) or increment the in-

ternal burst counter (ADV/L D=HIGH)

Output enable (OE) and burst sequence select (MODE) are

the asynchronous signals. OE can be used to disable the out-

puts at an y giv en tim e. ZZ ma y be tied t o LO W if it is not used .

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of oper atio n.

CLK

CEN

BWSx

CE1

CE2

256KX36/

MEMORY

ARRAY

Logic Block Diagram

DQx

Data-In REG.

CONTROL

and WRITE

LOGIC

ADV/LD

Mode

DPx

CY7C1370 CY7C1372

DQX

DPX

BWSX

512KX18

X = 18:0 X = 19:0

X = a, b, c , d X = a, b

X = a, b

X = a, b, c, d

OUTOUT

REGISTERS

and LOGI C

CY7C1370A

CY7C1372A

PRELIMINARY

Selec tio n Guide

167 MHz 150 MHz 133 MHz 100 MHz

Maximum Access Time (ns) 3.4 3.8 4.2 5.0

Maxim um Operating Current (mA) Com’l350 310 280 250

Maximum CM O S Standby Curr ent (mA) 30 30 30 30

Shaded areas contain advance information.

Pin Configurations

DNU

DDQ

DQb

DDQ

DQb

DQa

DDQ

DQa

DDQ

DQc

DDQ

DQc

DQd

DDQ

DQd

DDQ

BWSa

CLK

CEN

100

ADV/LD

DNU

CY7C1370A

100-Pin TQ FP Packages

DNU

DDQ

DPa

DQa

DDQ

DQa

DDQ

DQa

DDQ

DQb

DDQ

DQb

DDQ

DQb

DPb

DDQ

BWSb

BWSa

CLK

CEN

100

ADV/LD

MODE

DNU

CY7C1372A

BWSd

MODE

BWSc

DQc

DPc

DQd

DPd

DQd

DPb

DQb

DQa

DPa

DQb

(512K x 36) (1M x 18)

BWSb

DNU

CY7C1370A

CY7C1372A

PRELIMINARY

Pin Configurations (continued)

2345671

DQa

VDDQ

DQc

DQd

DQc

DQd

AA AAAV

DDQ

NC A

VDDQ

64M

DQc

DQd

TMS

VDD

DPd

ADV/LD ANCNC

VDD AANC

VSS VSS

NC DPb DQb

DQb

DQa

DQb

DQa DQa

DNUTDI TDO VDDQ

TCK

VSS

VDD(1)

VSS

MODE

CE1VSS

OE VSS VDDQ

BWScA VSS

WE VDDQ

VDD VDD(1) VDD

VSS

CLK

NC BWSa

CEN VSS VDDQ

VSS

NCA

A0 VSS

VDD NC

CY7C1370A (512K x 36) - 7 x 17 BGA

DPc DQb

A 32M

DQc DQb

DQc

DQc DQc DQb DQb

DQa DQa

DQa

DPa

DQd DQd

BWSd

119-Ball Bump BGA

BWSb

2345671

U32M

DQa

VDDQ

NC NCDQb

DQb

AA AAAV

DDQ

NC A

VDDQ

64M

DQb

TMS

VDD

DPb

ADV/LD ANCNC

VDD AANC

VSS VSS

NC NCDPa DQa

DQa

DQa DQa

DNUTDI TDO VDDQ

TCK

VSS

VDD(1)

VSS

MODE

CE1VSS NC

OE VSS VDDQ

BWSbA V

SS NC

VSS

WE NC

VDDQ

VDD VDD(1) VDD

NCVSS

CLK

NC NCBWSa

CEN VSS NC VDDQ

VSS NC

A0 VSS NC

VDD NC

CY7C1372A (1M x 18) - 7 x 17 B GA

CY7C1370A

CY7C1372A

PRELIMINARY

Pin Definitions (100-Pin TQFP)

x18 Pin Locati on x36 Pin Locati on Name I/O Type Description

37, 36, 32–35,

44–50, 80–84, 99,

100

37, 36, 32–35,

44–50, 81-84, 99,

100

Input-

Synchronous Address Inputs used to select one of the 266,144 ad-

dress locations . Sampled at the rising edge of the CLK.

93, 94 93, 94, 95, 96 BWSa

BWSb

BWSc

BWSd

Input-

Synchronous Byte Write S elect Inputs , ac tiv e LO W. Qualif ied wi th WE

to conduct writes to the SRAM. Sampled on the rising

edge of CLK. BWSa controls DQa and DPa, BW Sb con-

trols DQb and DPb, BWSc controls DQc and DPc, BWSd

controls DQd and DPd.

88 88 WE Input-

Synchronous Write Enable Input, active LO W. Sampl ed on the rising

edge of CLK if CEN is act ive LO W. This signal m ust be

asserted LOW to i nit iate a write sequence.

85 85 ADV/LD Input-

Synchronous Advanc e/Load Input used to adv ance the on-chip ad-

dress counter or loa d a new address . When HIGH (and

CEN is asserted LOW) the internal burst counter is ad-

vanced. When LOW, a new address can be loaded into

the device for an access. After being deselected, ADV/LD

should be driven LOW in ord er to load a new address.

89 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to

the device. CLK is qualified with CEN. CLK is on ly re c-

ognized if CEN is activ e LOW.

98 98 CE1Input-

Synchronous Chip Enable 1 Input, activ e LOW. Sampled on the rising

edge of CLK. Used in conjunction with CE2 and CE3 to

select/d eselect the device.

97 97 CE2Input-

Synchronous Chip Enabl e 2 Input, ac tiv e HIGH. Sampled on the rising

edge of CLK. Used in conjunction with CE1 and CE3 to

select/d eselect the device.

92 92 CE3Input-

Synchronous Chip Enable 3 Input, activ e LOW. Sampled on the rising

edge of CLK. Used in conjunction with CE1 and CE2 to

select/d eselect the device.

86 86 OE Input-

Asynchronous Outpu t Enab le, ac tive LO W. Com bined wit h t he synch ro-

nous logi c bloc k inside t he device to c ontrol the direction

of the I/O pins. When LOW, the I/O pins ar e all owed to

behave as outputs. When deasserted HIGH, I/O pins are

three- stated, and act as in put data pins. O E is mas ke d

during the data portion of a write sequence, during the

firs t cl ock when emerging from a desele cted state and

when the device has been deselected.

87 87 CEN Input-

Synchronous Clock Enable Input, active LO W. When asserted LO W

the clock sig nal is re cognized b y the SRAM. When deas-

serted HIGH the clock sign al is mask ed. Since deasse rt-

ing CEN does not dese lect t he device , CEN can be use d

to extend the previous cycl e when requir ed.

(a)58, 59, 62, 63,

68, 69, 72–73

(b)8, 9, 12, 13, 18,

19, 22–23

(a)52, 53, 56–59,

62, 63,

(b)68, 69, 72–75,

78, 79

(d)18, 19, 22–25,

28, 29

DQa

DQb

DQc

DQd

I/O-

Synchronous Bid ir ectio nal Data I/O l ines. As input s, the y f eed int o an

on-chip data regi ster that is triggered by the rising edge

of CLK. As outputs, they deliver the data contained in the

memory locati on speci f ied b y A [17:0] during t he pr evi ous

clock rise of the read cycl e. The direction of the pins is

controlled by OE and the internal control logic. When OE

is asserted LOW, the pins can beha ve as outputs . When

HIGH, DQa–DQd are placed in a three-state condition .

The outputs are automatic all y three -st ated during the

data portion of a write sequence, duri ng the first clock

when emerging from a dese lected state , and when the

device is deselected, regard less of the stat e of OE.

CY7C1370A

CY7C1372A

PRELIMINARY

74, 24 51, 80, 1, 30 DPa

DPb

DPc

DPd

I/O-

Synchronous Bidirectional Data P arity I/O lines. Functionally , these sig-

nals are identical to DQ[ 31:0]. During write sequences,

DPa is controlled by BWSa, DPb i s cont roll ed by BWS b,

DPc is controll ed by BWSc, and DPd is controlled b y

BWSd.

31 31 MODE Input

Strap Pin Mode Inp ut. Selects the b urst order of the device. Tied

HIGH selects the interleaved b urst order. P ull ed LOW

select s the li near b urst or der . MODE should not change

states during operatio n. Whe n left fl oating MODE will de-

faul t HIGH, to an inte rleaved burst order.

15, 16, 41, 65, 66,

91 15, 16, 41, 65, 66,

91 VDD Power Supply Power supply input s to the core of the de vice.

4, 11, 20, 27, 54,

61, 70, 77 4, 11, 20, 27, 54,

61, 70, 77 VDDQ I/O P o wer

Supply Power supply for the I/O circuitry.

5, 10, 17, 21, 26,

40, 55, 60, 67, 71,

76, 90

5, 10, 17, 21, 26,

40, 55, 60, 67, 71,

76, 90

VSS Ground Ground for the de vice. Should be connected to ground of

the system.

14 14 NC - No connects. Reserved for address expansion to 512K

depths.

38, 39, 42, 43 38, 39, 42, 43 DNU -Do Not Use pins. These pins should be left fl oating.

Pin Definitions (100-Pin TQFP) (continued)

x18 Pin Locati on x36 Pin Locati on Name I/O Type Description

Pin Definitions (119 BGA)

x18 Pin Locati on x36 Pin Location Name I/O Type Description

P4, N4, A2, A3, A4,

A5, A6, B3, B5, C2,

C3, C5, C6, G4, R2,

R6, T2, T3, T5, T6

P4, N4, A2, A3, A4,

A5, A6, B3, B5, C2,

C3, C5, C6, R2, R6,

G4, T3, T4, T5

Input-

Synchronous Address Inputs us ed to select one of the 266,144

address loc ation s. Sampl ed at the risin g edge of the

CLK.

L5, G3 L5, G5, G3, L3 BWSa

BWSb

BWSc

BWSd

Input-

Synchronous Byte W rite Select Inputs, active LOW. Qualified with

WE to c onduct writes to th e SRAM. Sampled on the

risi ng edge of CLK. BW Sa controls DQa and DPa,

BWSb con tr ols DQb and DPb, BWSc cont rols DQc

and DPc, BWSd controls DQd and DPd.

H4 H4 WE Input-

Synchronous Write Enable Input, active LOW. Sam pled on the ris-

ing edge of CLK if CEN i s active LOW. Th is si gnal

must be asserted LOW to initiate a write sequence.

B4 B4 ADV/LD Input-

Synchronous Advance/L oad Input used to advance t he on-chip ad -

dress counter or load a new address. When HIGH

(and CEN is asserted LOW ) the internal b urst

counter is advanced. When LOW , a new address can

be loaded into the device for an access. After bei ng

deselect ed, ADV/LD shoul d be driven LOW in orde r

to load a new addres s.

K4 K4 CLK Input-Clock Clock Input. Used to capture all synchr onous input s

to the de vice. CLK is qualif ied with CEN. CLK is only

recogniz ed if CEN is active LOW.

E4 E4 CE1Input-

Synchronous Chip Enable 1 Inp ut, active LOW. Sampled on the

risi ng edge of CLK.

CY7C1370A

CY7C1372A

PRELIMINARY

F4 F4 OE Input-

Asynchronous Output Enable, acti ve LOW. Comb ined with t he syn-

chronous logic block inside the dev ice to control the

direction of the I/O pi ns. When LO W , the I/O pins are

allo wed to behave as outputs. When deasserted

HIGH, I/O pins are three-stated, and act as input data

pins. OE is mas ked during the data portion of a write

sequence , during th e first cloc k when emer ging from

a deselected state and when the device has been

deselected.

M4 M4 CEN Input-

Synchronous Clock Enable Input, active LO W. When asserted

LO W the clock signal is re cognized by the SRAM.

When deasserted HIGH the cloc k signal is masked.

Since deasserting CEN does not deselect the device,

CEN can be used t o e xt end the pr e vious cycl e whe n

required.

(a)P7, N6, L6, K7,

H6, G7, F6, E7

(b)N1, M2, L1, K2,

H1 , G2 , E2 , D 1

(a)P7, N7, N6, M6,

L 7 , L 6 , K7, K6

(b)D7, E7, E6, F6,

G7, G6, H7, H6

(c)D1, E1, E2, F2,

G1, G2, H1, H2

(d)P1, N1, N2, M2,

L 1 , L 2 , K1, K2

DQa

DQb

DQc

DQd

I/O-

Synchronous Bidi r ect io na l Da ta I /O l i nes . A s in p uts , the y f ee d in to

an on-ch ip data r egister that is triggered by the risin g

edge of CLK. As outputs, they deliver the data con-

tained in the memory location specified by A[17:0] dur-

ing the previous cl ock rise of the read cycle. The di-

rection of the pins is controlled by OE and the internal

control logic. When OE is asserted LOW, the pins can

behave as outputs. When HIGH, DQa–DQd are

placed i n a three -state co ndition. The outputs are au -

tomatically three-stated duri ng the data p ortion of a

write sequence, during the first clock when emerging

from a deselected state, and when the device is de-

selected, regardless of the state of OE.

D6, P2 P6, D6, D2, P2 DPa

DPb

DPc

DPd

I/O-

Synchronous Bidirectional Data Parity I/O lines. Functionally , these

signal s are identical to DQ[31:0]. During write se-

quences, DPa is cont rol led by BWSa, DPb is con-

t roll e d by BWSb, DPc is controlled by BWS c, and

DPd is contr oll ed by BWSd.

R3 R3 MODE Input

Strap pin Mode Input. Sel ects the burst or der of the device.

Tied HIGH selects the interleaved burst order. Pulled

LOW selects the linear burst order. MODE should not

change states during operation. When left f loating

MODE will default HIGH, to an interleaved burst

order.

C4, J2, J4, J6, R4 C4, J2, J4, J6, R4 VDD Power Supply P ower supp ly inputs to the core of the device.

A1, A7, F1, F7, J1,

J7, M1, M7, U1, U7 A1, A7, F1, F7, J1 ,

J7, M1, M 7 , U 1 , U7 VDDQ I/O P o wer

Supply Power supply for the I /O circuitry.

D3, D5, E3, E5, F3,

F5, G5, H3, H5, K3,

K5, L3, M3, M5, N3,

N5, P3, P5, R5

D3, D5, E3, E5, F3,

F5, H3, H5, K3, K5,

M3, M5, N3, N5, P3,

P5, R5

VSS Ground Ground for the device. Should be connected to

ground of the system.

J3, J5 J3, J5 VDD(1) Input-

Asynchronous These pi ns have t o be ti ed to a voltage le vel > VIH.

They need not be tied to VDD.

U5 U5 TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit . Del ivers data on

the negative edge of TCK.

U3 U3 TDI JTAG serial

input

Synchronous

Serial data-I n to the JTA G cir cuit. Sam pled on the

risi ng edge of TCK.

Pin Definitions (119 BGA) (continued)

x18 Pin Locati on x36 Pin Location Name I/O Type Description

CY7C1370A

CY7C1372A

PRELIMINARY

U2 U2 TMS Test Mode

Select

Synchronous

This pin controls the Test Access P ort state machine.

Sampled on the rising edge of TCK.

U4 U4 TCK JTAG-Clock Cloc k input to the JTAG circuitry.

A4, T6, T1 A4, T4, T2 16M,

32M,

64M

- No connects. Reserved for address expansion.

B1, B2, B7, C1, C7,

D2, D4, D7, E1, E6,

F2, G1, G6, H2, H7,

K1, K 6 , L2 , L 4 , L7 ,

M6, N2, N7, P1, P6,

R1, R5, R7,T7

B2, B7, C7, D4, L4,

L7, R1, R5, R7,

T1,T7

NC - No connects.

U6 U6 DNU - Do not use pins.

Pin Definitions (119 BGA) (continued)

x18 Pin Locati on x36 Pin Location Name I/O Type Description

CY7C1370A

CY7C1372A

PRELIMINARY

Introduction

Functional Overview

The CY7C1370A/CY7C1372A are synchronous-pipelined

Burst NoBL SRAMs designed specifically to eliminate wait

states during Write/Read transitions. All synchronous inputs

pass through input registers controlled by the rising edge of

the clock. The clock signal is qualified with the Clock Enable

input signal (CEN). If CEN is HIGH, the clock signal is not

recog nized and al l int ernal s tates ar e maintai ned. Al l synchr o-

nous operations are qu ali fied wit h CEN. All data outputs pass

through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (tCO) is

3.8 ns (150-MH z device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the cloc k. If Cloc k

Enable (CEN) is active LOW and AD V/LD is asserted LOW , the

address presented to the device will be latched. The access

can eithe r be a r ead or write oper ati on, depending on the sta-

tus of the Write Enable (WE). BWS[d:a] can be used to conduct

byte write oper ations.

Write operations are qualified by the Write Enable (WE). All

write s are simpli fied with on-chi p sy nchronou s s elf-ti med writ e

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable ( OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the devi ce has been de-

sele cted in or der to l oad a new addr ess f or t he nex t oper ati on.

Singl e Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is as serted LO W, ( 2) CE1, CE2,

and CE3 are ALL asser ted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LO W. Th e address presented to th e address inputs is lat ched

into t he Address Register and presented to the memory core

and control logi c. The control logic determine s that a read ac-

cess is in pr ogress and allows th e requested dat a to propa gate

to t he inp ut of the output regi ste r . At the rising edg e of the n e xt

clock the requested data is allowed to propagate through the

output r egister and ont o the data bus within 3.8 ns (150-M Hz

device) provided OE is active LOW. After the first clock of the

read access the output buffers are controlled by OE and the

inte rnal c o nt ro l lo g ic . O E must be driven LOW in order for the

device to drive out the requested data. During the second

clock, a subsequent operation (Read/Write/Deselect) can be

initiated. Deselecting the device is also pipelined. Therefore,

when the SRAM is deselected at clock rise by one of the chi p

enable signals, its output will three-state following the next

cl o ck rise.

Burst Read Accesses

The CY7C1370A/CY7C1372A have an on-chip burst counter

that allows the user the ability to supply a single addr ess and

conduct up to four Reads without reasserting the address in-

puts. ADV/LD mu st be driven LOW in order to load a new ad-

dress into th e SRAM, as descri bed in the Single Read Ac cess

section above. The sequence of the burst counter is deter-

mined by the MODE input signal. A LOW input on MODE se-

lects a linear burst mode, a HIGH selects an int erlea ved burst

sequence. Both burst counters use A0 and A1 in the burst

sequence, and will wrap-around when incremented suffi cient-

ly. A HIGH input on ADV/LD will increment the internal burst

counter regardless of the state of chip enables inputs or WE.

WE is lat ched at the beginning of a b urst cycle. Therefore, the

type of access (Read or Write) is maintained throughout the

burst sequence .

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,

and CE3 are ALL asserted act ive, and (3) the write si gnal WE

is asserted LOW. The address presented to Ax is loaded into

the Address Register. The write signals are latched into the

Control Logic block.

On the subsequent clock rise the data lines are automatically

three- stated regardl ess of t he state of the OE input signal. This

allows the exter nal logic to present the data on DQ and DQP

(DQa,b,c,d/DPa,b,c,d for CY7C1370A and DQa,b/DPa,b for

CY7C1372A). In addition, the address for the subsequent ac-

cess ( Read/ Write/Des elect ) is latch ed int o the Ad dres s Regis -

ter (pr ovided the appropriate cont rol signals ar e asserted) .

On the next clock rise the data presented to DQ and DP

(DQa,b,c,d/DPa,b,c,d for CY7C1370A & DQa,b/DPa,b for

CY7C1372A) (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the wri te is complete.

The data written during the Write operation is controlled by

BWS (BWSa,b,c,d for CY7C1370A & BWSa,b for CY7C1372A)

signal s. The CY7 C1370A/CY7C1372 A pr ovid es b yte write ca -

pability that is described in the Write Cycle Description table.

Asser ting the Wri te Enable input (WE) with the selected Byte

W rite Sele ct ( BWS) input will selecti vely write to only the de-

sired bytes. Bytes not selected during a byte write operation

will remain u naltered. A Synchronous self-timed write m echa-

nism has been provided to simplify the write operations. Byte

write capability has been included in order to greatly simplify

Read/Modif y/Write sequences, which can be reduced to sim-

ple byte write operations.

Because the CY7C1370A/CY7C1372A is a common I/O de-

vice, data should not be driven into the device while the out-

puts are active. The Output Enable (OE) can be deasserted

HIGH before presenting data to the DQ and DP

(DQa,b,c,d/DPa,b,c,d for CY7C1370A & DQa,b/DPa,b for

CY7C1372A) inp uts. Doing so will three-s tate the output driv -

ers. As a saf ety precaution, DQ and DP (DQa,b,c,d/DPa,b,c,d for

CY7C1370A & DQa,b/DPa,b fo r CY7C1372A) ar e automat ical -

ly three- sta ted during the dat a porti on of a write cycl e , regard -

less of t he state of OE.

Burst Write Accesses

The CY7C1370A/CY7C1372A has an on-chip burst counter

that allows the user the abi lity t o supply a singl e address and

conduct up t o four WRITE operations without reasserting the

address inputs. ADV/LD must be dri ven LOW in order to load

the initial address, as described in the Single Write Access

section above. When ADV/LD is driven HIGH on the subse-

quent clock rise, the chip enables (CE1, CE2, and CE3) and

WE inputs are ignored and the burst counter i s incremented.

The correct BWS (BWSa,b,c,d for CY7C1370A & BWSa,b for

CY7C1372A) inputs must be driven in each cycle of the burst

write in order to write the correct bytes of data.

CY7C1370A

CY7C1372A

PRELIMINARY

Notes:

1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =

Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BWSx. See Write Cycle Description table for details.

3. The DQ and DP pins are controlled by the current cycle and the OE signal.

4. CEN = 1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

Cyc le Description Truth Tabl e[1, 2, 3, 4, 5, 6]

Operation Address

Used CE CEN ADV/

LD/ WE BWSxCLK Comments

Deselected External 1 0 L X X L-H I/Os th ree-state f ollowing nex t

recognized clock.

Suspend - X 1 X X X L-H Clock ignored, al l operations

suspended.

Begin Read External 0 0 0 1 X L-H Address latched.

Begin Writ e External 0 0 0 0 Valid L-H Address lat ched, data presented

tw o valid clocks l a t e r.

Burst Read

Operation Internal X 0 1 X X L-H Burst Read opera tion. Pre vi ous ac-

cess was a Read operation. Ad-

dresses inc remented internally in

conjunct ion with the stat e of Mode.

Burst Write

Operation Internal X 0 1 X Valid L-H Burst W rit e operation. Previous ac-

cess was a Writ e operation. Ad-

dresses inc remented internally in

conjunct ion with the stat e of

MODE. Bytes written are deter-

mined by BWS[d:a].

Interleaved B u rst S eq u en ce

First

Address Second

Address Third

Address Fourth

Address

A[1:0] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Sequence

First

Address Second

Address Third

Address Fourth

Address

A[1:0] A[1:0] A[1:0] A[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

CY7C1370A

CY7C1372A

PRELIMINARY

Wr i te C ycl e D escri p t i o n [1]

Function (CY7C1370A) WE BWSdBWScBWSbBWSa

Read 1XXXX

Write - No bytes written 01111

Write Byt e 0 - (DQa and DPa) 01110

Write Byt e 1 - (DQb and DPb) 01101

Write Bytes 1, 0 01100

Write Byt e 2 - (DQc and DPc) 01011

Write Bytes 2, 0 01010

Write Bytes 2, 1 01001

Write Bytes 2, 1, 0 01000

Write Byt e 3 - (DQd and DPd) 00111

Write Bytes 3, 0 00110

Write Bytes 3, 1 00101

Write Bytes 3, 1, 0 00100

Write Bytes 3, 2 00011

Write Bytes 3, 2, 0 00010

Write Bytes 3, 2, 1 00001

Write All Bytes 00000

Functi on (CY7C1372A) WE BWSbBWSa

Read 1 x x

W r ite - No By te s Writt en 0 1 1

Write Byte 0 - (DQa and DPa ) 0 1 0

Write Byte 1 - (DQb and DPb) 0 0 1

W r ite Bo th By te s 0 0 0

CY7C1370A

CY7C1372A

PRELIMINARY

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1370A/CY7C1372A incorporates a serial boundary

scan Test Access Port (TAP) in the BGA package only. The

TQFP packa ge do es n ot off er thi s funct i onali ty. This port ope r-

ates in accorda nce with I EEE Standard 1 149.1-1900, but does

not have the set of functions required for full 1149.1 compli-

ance . Thes e functi ons from the IEEE speci fica tion ar e e xcl ud-

ed becau se their inclusion pl aces an added dela y in the c riti cal

speed path of the SRAM. Note that the TAP controller func-

tions in a manner that does not conflict with the operation of

other de vices usi ng 1149.1 full y complian t TAPs . The TAP op-

erates using JEDEC standard 3.3V I/O logic levels.

Disabling the JTAG Featur e

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are in-

ternally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a r eset sta te whi ch will not interfere with the oper-

ation of the device.

Test Access Po rt (TAP) - Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the risi ng edge of TCK. All outputs are dri ven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to gi ve commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pull ed up internall y, resulti ng in a logic HIGH l evel .

Test Data-In (TDI)

The TDI pin is used to seri ally input information into the regis-

ters and can be connected to the input of any of the registers .

The register between TDI and TDO is chosen by the instruc-

tion that is loaded into the TAP instruction register. For infor-

mation on loading the instruction register, see the TAP Con-

troller State Diagram. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (M SB) on any register.

Test Data Out (TDO)

The TDO output pin is used to serially clo ck data-out from the

registers. The output is active depending upon the current

stat e of the TAP state machi ne (see TAP Control ler State Dia-

gr am). The outpu t changes on t he f alli ng edge of TCK. TDO is

connected to the Least Significant Bit (LSB) of any reg ist er.

P erform ing a TAP Reset

A Reset is per formed by f orcing TMS HIGH (VDD) f or f ive risin g

edges of TCK. This RESET does not affect the operation of the

SRAM a nd ma y be per f ormed while the SRAM i s oper at ing. At

power-up, the TAP is reset internally to ensure that TDO

come s up in a Hig h-Z state.

TAP Registers

Regist ers are connected between the TDI and TDO pins and

all ow data t o be s canne d int o and out of the SRAM t est ci rcui t-

ry. Only one register can be selected at a time through the

instruction registers. Data is serially loaded into the TDI pin on

the rising edge of TCK. Data is output on the TDO pin on the

falli ng edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

regis ter. This regist er is loaded when it is pl aced between the

TDI and TDO pins as shown in the TAP Controller Block Dia-

gram. Upon power-up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as de-

scribed i n the previous section.

When the TAP controller is in the Captu reIR s tate, the two least

signi fican t bits are loaded wi th a binary “01” pattern to allo w fo r

fault isolation of the board level seria l te st path.

Bypass Register

To s ave time when seri all y shifting data through register s, it is

sometimes advantageous to skip certain states. The bypass

regis ter i s a sing le-bi t reg ister that can be placed betw een TD I

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruct ion is execu ted.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The x36 configurat ion has a 69-bit-long r eg-

ister, and the x18 confi guration has a 69-bit-long regi ster.

The boundary scan register is loaded with the cont ents of the

RAM Input and Output ring when the TAP contro ller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controll er is moved to t he Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ri ng.

The Boundary Scan Order tables show th e order in which the

bits are conn ected. Each bit cor responds to one of the bum ps

on the SRAM pac kage. The MSB of the regi ster is connected

to TDI, and the LSB is con nected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM a nd can be shi fted out when the TAP control ler

is in the Shi ft-DR sta te. The I D regis ter has a ve ndor code and

other i nformation described in the Ide nti fic ati on Register Def i-

niti ons table.

TAP Ins truction Set

Eight different instructions are possible with the three-bit in-

struct ion register. All combina tions are listed i n the Instruc tion

Code table. Three of these instructions are listed as RE-

SERVED and shoul d not be used. The other five instructions

are described in detail below.

The TAP controller used in this SRAM i s not full y com pliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully impl emented. The TAP controlle r can-

not be used to l oad address, data, or control signals int o the

SRAM and cannot preload the Input or Output buffers. The

CY7C1370A

CY7C1372A

PRELIMINARY

SRAM d oes not implement t he 1149. 1 comman ds EXT EST or

INTEST or the PRELOAD portion of SAMPLE / PRELOAD;

rat her it performs a capt ure of the Inputs and Out put ring whe n

these instructions are executed.

Inst ructi ons are load ed into the TAP controll er durin g the Shif t-

IR state when the instruction register is placed between TDI

and TDO . During t his state, instructions are shifted thr ough the

instruction regist er t hrough the TDI and TDO pins . To ex ecute

the in struction onc e it is shi fted in, the TAP contr oller needs t o

be mo ved into the Updat e-IR sta te.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be ex-

ecuted whenever the instruction register is loaded with all 0s.

EXTEST is not implemented in the TAP controller, and there-

fore this device is not com pli ant to the 1149.1 sta ndard.

The TAP controller does recognize an all-0 inst ruction. When

an EXTEST inst ruction is loaded into the i nstruction register,

the SRAM responds as if a SAMPLE / PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE / PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE i nstruction causes a v endor -speci fic, 32-bit code

to be loaded into the instruction register. It also places the

inst ruction regi ster between the TDI and TDO pins and allows

the I DCODE to be sh ift ed out of t he de vic e when the TAP con-

troller enters the Shift-DR state. The IDCODE instruction is

loade d into the inst ruction regist er upon p ower- up or whene v er

the TAP contr oller is given a test logic reset state.

SAMPLE Z

The SAM PLE Z ins truction caus es the b oundary s can regi ster

to be connec ted between the TDI and TDO pins when the TAP

contr oller is in a Shi ft-DR stat e. It also pl aces all SRAM outputs

in to a H i g h - Z state.

SAMPLE / PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandato ry instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1 compliant .

When the SAMPLE / PRELOAD instructions are loaded into

the i nstruction register and the TAP controller is in t he Capture -

DR state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be a wa re that the TAP cont roll er clock can onl y

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possible

that during t he Capture-DR stat e, an input or output will under-

go a tra nsiti on. The TAP ma y th en try to c apture a sig nal whil e

in transition (m etastable stat e) . This will not harm the device,

but there is no guarantee as to the value that will be captured.

Repeatable result s m ay not be possible.

To guarantee that the boundar y scan register will capt ure the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller 's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and si mply ignor e the v alue of t he CK an d CK# cap tured i n the

boundary scan regi ster.

Once the da ta i s captu red, i t is p ossib l e to shi ft out the dat a by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register betw een the TDI and TDO pins.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the Update-

DR state while performing a SAMPLE / PRELOAD instruction

will have the same effect as the Pause-DR command.

Bypass

When t he BYPASS instruction is loaded in the instruction reg -

ister and the TAP is placed in a Shift-DR state, the bypass

regis ter is place d between the TDI and TDO pin s. The advan-

tage of the BYPASS instruct ion is that i t shortens the b oundary

scan path when multiple device s are connected together on a

board.

Reserved

These instructions are not implemented but are reserved for

futur e use. Do not use these instructions.

CY7C1370A

CY7C1372A

PRELIMINARY

TAP Controller State Diagram

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Note: The 0/1 next to each state represents the va lue at TMS at the rising edge of TCK.

CY7C1370A

CY7C1372A

PRELIMINARY

TAP C o n trol le r Block D i ag ra m

012..

3031

Boundary Scan Regist er

Identificati on Registe r

012..

012

Instruction Register

Bypass Registe r

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

TAP Electrical Characteristics Ove r the Operating Range[7, 8]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Outp ut HIGH Voltage IOH = −2.0 mA 2.1 V

VOH2 Outp ut HIGH Voltage IOH = −100 µA2.0 V

VOL1 Output LO W Volt age IOL = 2.0 mA 0.7 V

VOL2 Output LO W Volt age IOL = 100 µA0.2 V

VIH Input HIGH Voltage 2.0 VDD+0.3 V

VIL Input LOW Voltage −0.3 0.7 V

IXInput Load Current GND ≤ VI ≤ VDDQ −55µA

Notes:

7. All Voltage referenced to Ground

8. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot: VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V f o r t<200 ms.

CY7C1370A

CY7C1372A

PRELIMINARY

TAP AC Swi tch i n g Ch aracter i stics Over the Operating Range[9, 10]

Parameter Description Min. Max Unit

tTCYC TCK Clock Cycle Time 100 ns

tTF TCK Clock Frequency 10 MHz

tTH TCK Clock HIGH 40 ns

tTL TCK Clock LOW 40 ns

Set-up Times

tTMSS TMS Set- up to TCK Clock Rise 10 ns

tTDIS T DI S e t-up to TC K Clo ck R is e 10 ns

tCS Capture Set-up to TCK Rise 10 ns

Hold Times

tTMSH TMS Hold aft er TCK Clock Rise 10 ns

tTDIH TDI Hold after Clock Rise 10 ns

tCH Capture Hold after clock rise 10 ns

Output Ti mes

tTDOV TCK Clock LOW to TDO Valid 20 ns

tTDOX TCK Clock LOW to TDO Invalid 0ns

Notes:

9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register .

10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

CY7C1370A

CY7C1372A

PRELIMINARY

TAP Timing and Test Conditions

(a)

TDO

CL=20 pF

Z0=50Ω

GND

1.25V

Test Clock

Test M ode Select

TCK

TMS

Te st D ata-In

TDI

Test Data-Out

TDO

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOX tTDOV

50Ω

2.5V

ALL INPUT PULSES

1.25V

CY7C1370A

CY7C1372A

PRELIMINARY

Identif ication Register Defini ti ons

Instruction Fi eld

Value

DescriptionCY7C1370A CY7C1372A

Revision Number

(31:29) 000 Version num be r.

Cypress D evice ID

(28:12) TBD TBD Defines the type of SRAM.

Cypress JEDEC ID

(11:1) TBD Allows unique identificati on of SRAM vendor.

ID Regist er Pre sence

(0) 1Indicate the presence of an ID register.

Scan Regi ster si z es

Instruction 3

Bypass 1

ID 32

Boundary Scan 70 (CY7C1370A)

51 (CY7C1372A)

Identification Codes

Instruction Code Description

EXTEST 000 Captu res the Input/Output ring content s. Places the boundary scan regist er

between the TDI and TDO . F orces all SRAM outputs to High- Z state. This

instructi on is not 1149 .1 compliant.

IDCODE 001 Loads t he ID register with the v endor ID code and places the register b e-

tween TDI and TDO. This oper ation does not affect SRAM operation.

SAMPLE Z 010 Captures the I nput/Output contents. Places the boundary scan register be-

tween TDI and TDO. Forces all SRAM outpu t drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Ca ptures the Inp ut/Out put ring cont ents. Places the bound ary scan regist er

between TDI and TDO. Does not affect the SRAM operation. This instruction

does not implement 1149.1 preload function and is therefore not 1149.1

compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register bet ween TDI and TDO. This operation does not

affect SRAM operation.

CY7C1370A

CY7C1372A

PRELIMINARY

Boundary Scan Order (512K x 36)

Bit # Signal

Name Bump

ID Bit # Signal

Name Bump

1 A 2R 36 CE3 6B

2 A 3T 37 BWSa 5L

3 A 4T 38 BWSb 5G

4 A 5T 39 BWSc 3G

5 A 6R 40 BWSd 3L

6 A 3B 41 CE2 2B

7 A 5B 42 CE1 4E

8DPa 6P 43 A3A

9DQa 7N 44 A2A

10 DQa 6M 45 DPc 2D

11 DQa 7L 46 DQc 1E

12 DQa 6K 47 DQc 2F

13 DQa 7P 48 DQc 1G

14 DQa 6N 49 DQc 1D

15 DQa 6L 50 DQc 1D

16 DQa 7K 51 DQc 2E

17 NC 7T 52 DQc 2G

18 DQb 6H 53 DQc 1H

19 DQb 7G 54 SN 5R

20 DQb 6F 55 DQd 2K

21 DQb 7E 56 DQd 1L

22 DQb 6D 57 DQd 2M

23 DQb 7H 58 DQd 1N

24 DQb 6G 59 DQd 2P

25 DQb 6E 60 DQd 1K

26 DPb 7D 61 DQd 2L

27 A6A 62 DQd 2N

28 A5A 63 DPd 1P

29 A4G 64 MODE 3R

30 A4A 65 A2C

31 ADV/LD 4B 66 A3C

32 OE# 4F 67 A5C

33 CEN# 4M 68 A6C

34 WE# 4H 69 A1 4N

35 CLK 4K 70 A0 4P

Boundary Scan Order (1M x 18)

Bit # Signal

Name Bump

ID Bit # Signal

Name Bump

1 A 2R 36 DQb 2E

2 A 2T 37 DQb 2G

3 A 3T 38 DQb 1H

4 A 5T 39 SN 5R

5 A 6R 40 DQb 2K

6 A 3B 41 DQb 1L

7 A 5B 42 DQb 2M

8DQa 7P 43 DQb 1N

9DQa 6N 44 DPb 2P

10 DQa 6L 45 MODE 3R

11 DQa 7K 46 A2C

12 NC 7T 47 A3C

13 DQa 6H 48 A5C

14 DQa 7G 49 A6C

15 DQa 6F 50 A1 4N

16 DQa 7E 51 A0 4P

17 DPa 6D

18 A6T

19 A6A

20 A5A

21 A4G

22 A4A

23 ADV/LD 4B

24 OE 4F

25 CEN 4M

26 WE 4H

27 CLK 4K

28 CE3 6B

29 BWSa 5L

30 BWSb 3G

31 CE2 2B

32 CE1 4E

33 A3A

34 A2A

35 DQb 1D

CY7C1370A

CY7C1372A

PRELIMINARY

Maximum Ratings

(Above which the usefu l l ife ma y be impaired. For use r gui de-

li nes, not tested .)

Storage Temper ature ... .. ......... ..... ..... ..... ....–65°C to +15 0 °C

Ambient Temperature wi th

Power Applied.............................................–55°C to +12 5 °C

Supply Voltage on VDD Relative to GND........ –0. 5V to +3.6V

DC Voltage Applied to Outputs

in High Z State[12] ............................... –0.5V to VDDQ + 0.5V

DC Input Voltage[12]............................ –0.5V to V DDQ + 0.5V

Cu r re n t in to Outp ut s (L OW ) ..... ..... ....... ..... ..... ..... ....... .. 20 mA

Static Discharge Voltage.......... ..... .. ........ .. ..... .. ..... ... >2001V

(per MIL- STD-883, Method 3015)

Latch-Up Current... .. ..... ............ ..... .. ........ ......... ..... . >200 mA

Operating Range

Range Ambient

Temperature[11] VDD VDDQ

Com’l 0°C to +7 0 °C 3.3V + 10%/

–5% 2.5 – 5% – VDD

Electrical Characteristics Ov er th e Ope rating Range

Parameter Description Test Conditions Min. Max. Unit

VDD Power Suppl y Voltage 3.135 3.465 V

VDDQ I/O Supply Voltage 3.3 V I/O 2.375 VDD V

VOH Outp ut HIGH Voltage VDD = Min., IOH = –1.0 mA 2.5V 1.7 V

VDD = Min., IOH = –1.0 mA 3.3V 2.0 V

VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA, either VDDQ 0.4 V

VIH Input HIGH Voltage 2.0 VDD + 0.3V V

VIL Input LOW Voltage –0.5 0.8 V

IXInput Load Current GND < VI < VDDQ 5mA

Input Current of MODE 30 mA

IOZ Output Leakage

Current GND < VI < VDDQ, Output Disabled 5mA

IDD VDD O perating Suppl y VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC 6.0-ns cycle, 167 MHz 350 mA

6.7-ns cycle, 150 MHz 310 mA

7.5-ns cycle, 133 MHz 280 mA

10-ns cycle, 100 MHz 250 mA

ISB1 Automatic CE

Power-Down

Current—TTL Inputs

Max. VDD, Device Deselected,

VIN > VIH or V IN < VIL

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MHz 130 mA

6.7-ns cycle, 150 MHz 110 mA

7.5-ns cycle, 133 MHz 95 mA

10-ns cycle, 100 MHz 80 mA

ISB2 Automatic CE

Power-Down

Current—CM O S Inputs

Max. VDD, Device Deselected, VIN

< 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speed grades 30 mA

ISB3 Automatic CE

Power-Down

Current—CM O S Inputs

Max. VDD, Device Deselected, or

VIN < 0.3V or VIN > VDDQ – 0. 3V

f = fMAX = 1/tCYC

6.0-ns cycle, 167 MHz 120 mA

6.7-ns cycle, 150 MHz 100 mA

7.5-ns cycle, 133 MHz 85 mA

10-ns cycle, 100 MHz 90 mA

ISB4 Automatic CS

Power-Down

Current—TTL Inputs

Max. VDD, Device Deselected,

VIN > VIH or V IN < VIL, f = 0 All Spee ds 20 mA

Shaded areas contain advance information.

Notes:

11. TA is the case temperature.

12. Minimum voltage equals -2.0V for pulse durations of less than 20 ns.

13. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions.

CY7C1370A

CY7C1372A

PRELIMINARY

Capacitance[15]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = VDDQ = 3.3V 4pF

CCLK Clock In put Capacitance 4pF

CI/O Input/Output Capaci tance 6.4 pF

AC Test Loads and Waveforms

OUTPUT

R=317Ω

R=351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL=50Ω

Z0=50Ω

VL= 1.5V

3.3V ALL INPUT PULSES[14]

VCC

GND

90%

10% 90%

10%

<1V/ns <1V/ns

(c)

Thermal Resistance[15]

Descri pti on Test Conditi ons Symbol TQFP Typ. Uni ts

Thermal Resist ance (J unc-

tion to Ambient) Still Air, soldered on a 4.25 x 1.125 i nch, 4-layer

printed circuit board QJA 25 °C/W

Thermal Resist ance (J unc-

tion to Case) QJC 9°C/W

Notes:

14. Input waveform should have a slew rate of > 1 V/ns.

15. Tested initially and after any design or process change that may affec t these parameters.

CY7C1370A

CY7C1372A

PRELIMINARY

Switching Characteristics Over the Operating Range[16]

-167 -150 -133 -100

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

Clock

tCYC Clock Cycle Time 5.9 6.7 7.5 10.0 ns

FMAX Max imum Operating Frequency 167 150 133 100 MHz

tCH Clock HIGH 2.4 2.6 3.0 3.5 ns

tCL Clock LOW 2.4 2.6 3.0 3.5 ns

Output Ti mes

tCO Data Output Valid Af ter CLK Rise 3.4 3.8 4.2 5.0 ns

tEOV OE LOW to Output Valid[15, 17, 19] 3.4 3.8 4.2 5.0 ns

tDOH Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns

tCHZ Clock to High-Z[ 15, 16, 17, 18 , 19] 1.5 3.0 1.5 3.0 1.5 3.5 1.5 3.5 ns

tCLZ Clock t o Low- Z[15, 16, 17, 18, 19] 1.5 1.5 1.5 1.5 ns

tEOHZ OE HIGH to Output High- Z[ 16, 17, 19] 3.0 3.0 3.5 3.5 ns

tEOLZ OE LOW to Output Low-Z[16, 17, 19] 0 0 0 0 ns

Set-Up Times

tAS Add ress Set-Up Befo re CLK Rise 1.5 1.5 1.5 1.5 ns

tDS Data I npu t S e t- U p B e fore C LK Ri s e 1.5 1.5 1.5 1.5 ns

tCENS CEN Set-Up Before CLK Rise 1.5 1.5 1.5 1.5 ns

tWES WE, BW S x Set-Up Before CLK Rise 1.5 1.5 1.5 1.5 ns

tALS ADV/LD Set-Up Before CLK Rise 1.5 1.5 1.5 1.5 ns

tCES Chip Select Set-Up 1.5 1.5 1.5 1.5 ns

Hold Times

tAH Add ress Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tWEH WE, BW x Hold After CLK Rise 0.5 0.5 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 0.5 ns

tCEH Chip Select Hol d After CLK Ris e 0.5 0.5 0.5 0.5 ns

Shaded areas contain advance information.

Notes:

16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and

output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.

17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state

voltage.

18. At any given voltage and temperature, tEOHZ is le s s th an t EOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed ov er worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

19. This parameter is sampled and not 100% tested.

CY7C1370A

CY7C1372A

PRELIMINARY

S witching Wave fo rms

CEN

CLK

ADDRESS

WE &

Data

In/Out

tCYC

tCH tCL

RA1

tAH

tAS

tWS tWH

tCES tCEH

tCO

= DON’T CARE = UNDEFINED

The combination of WE & BWSx (x = a, b, c, d for CY7C1370V25A & x = a, b for CY7C 1372V25A) define a write cyc le

Out D2

In D5

Out

READ

WRITE

DESELECT

WRITE

READ

SUSPEND

READ

DESELECT

WA2 RA3 RA4 WA5 RA6 RA7

tCLZ tDOH

Out

tCHZ

Device

originally

deselected

Out

tCHZ

tCENS tCENH

tDOH

BWSx

READ/WRITE/DESELECT Sequence

CEN HIGH blocks

Out

all synchronous inputs

tDS tDH

(see Write Cycl e Description table) CE is the combination of CE1, CE2, and CE3. All chip enables need to be active

in order to select the device. A ny chip enable can deselect the devi ce. RAx stands for Read Address X, W Ax

Write Address X, Dx stands for Data-in fo r loc ation X, Qx stands for Data- out for location X. ADV/LD held LOW.

OE held LOW.

CY7C1370A

CY7C1372A

PRELIMINARY

S witching Wave fo rms (continued)

ADV/LD

CLK

ADDRESS

Data

In/Out

tCYC

tCH tCL

tALS tALH

RA1

tAH

tAS

tCES tCEH

tCO

= DO N’T CARE = UNDEFINED

The combination of WE & BWSx(x = a, b c, d) def ine a write cycle (see Write Cycle Description table).

Out

Begin Read

Bur st R ead

tCLZ tDOH

CE is the combination of CE1, C E2, and CE3. All chi p enables need to be active in order to select

the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for

Device

originally

deselected

Write Addr ess X, Dx stands for Data-in for location X, Qx st ands for Data-out for locatio n X. CEN held

WA2

Q1+1

Out Q1+2

Out Q1+3

Out

RA3

tCLZ

tCHZ

D2+1

In D2+2

In D2+3

tCO

Out

tDS

tDH

Bur st R ead

Burst Read

Begin Write

Burst Write

Burst Writ e

Burst Write

Begin Read

Bur st Read

Bur st R ead

Burst Sequences

BWSx

tWS tWH

LOW. During burst writes, byt e writes can be conducted by asserti ng the appropriate BWSx input sig nals.

Burst or der determined by the state of the MODE input. CEN held LOW. OE held LOW.

CY7C1370A

CY7C1372A

PRELIMINARY

Document #: 38-00985-A

S witching Wave fo rms (continued)

Three-State

I/Os

OE Timing

tEOHZ tEOV

tEOLZ

Orde ring Information

Speed

(MHz) Orderi ng Code Package

Name Package Type Operating

Range

167 CY7C1370A-167AC/

CY7C1372A-167AC A101 100 -Lead 14 x 20 x 1.4 mm Thin Quad Flat P ack Commercial

CY7C1370A-167BGC/

CY7C1372A-167BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm )

150 CY7C1370A-150AC/

CY7C1372A-150AC A101 100-Lea d 14 x 20 x 1.4 mm Thin Quad Flat P ack

CY7C1370A-150BGC/

CY7C1372A-150BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm)

133 CY7C1370A-133AC/

CY7C1372A-133AC A101 100-Lea d 14 x 20 x 1.4 mm Thin Quad Flat P ack

CY7C1370A-133BGC/

CY7C1372A-133BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm)

100 CY7C1370A-100AC/

CY7C1372A-100AC A101 100-Lea d 14 x 20 x 1.4 mm Thin Quad Flat P ack

CY7C1370A-100BGC/

CY7C1372A-100BGC BG119 119-Lead FBGA (14 x 22 x 2.4 mm)

Shaded areas contain advance information.

CY7C1370A

CY7C1372A

PRELIMINARY

Package Diagrams

100-Pin Thin Plasti c Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

CY7C1370A

CY7C1372A

PRELIMINARY

of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Revision H is to r y

Package Diagrams (continued)

119-Lead FBGA (14 x 22 x 2.4 mm) BG119

51-85115

Document Title: CY7C1370A/CY7C1372A

Document Number: 38-00985

REV. ECN NO. ISSUE DATE ORIG. OF

CHANGE DESCRIPTION OF CHANGE

** 2991 4/17/00 MPR 1. New Data Sheet

*A 3080 6/13/00 CXV 1. Correct Pin ID, pin #43, B2