THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 LOW-NOISE, HIGH-OUTPUT DRIVE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS Check for Samples: THS3120 THS3121 FEATURES DESCRIPTION * The THS3120 and THS3121 are low-noise, high-voltage, high output current drive, current-feedback amplifiers designed to operate over a wide supply range of 5 V to 15 V for today's high-performance applications. 1 23 * * * * * Low Noise: - 1 pA/Hz Noninverting Current Noise - 10 pA/Hz Inverting Current Noise - 2.5 nV/Hz Voltage Noise High Output Current Drive: 475 mA High Slew Rate: - 1700 V/s (RL = 50 , VO = 8 VPP) Wide Bandwidth: 120 MHz (G = 2, RL = 50 ) Wide Supply Range: 5 V to 15 V Power-Down Feature: (THS3120 Only) The THS3120 offers a power saving mode by providing a power-down pin for reducing the 7-mA quiescent current of the device, when the device is not active. These amplifiers provide well-regulated ac performance characteristics. Most notably, the 0.1-dB flat bandwidth is exceedingly high, reaching beyond 90 MHz. The unity-gain bandwidth of 130 MHz allows for good distortion characteristics at 10 MHz. Coupled with high 1700-V/s slew rate, the THS3120 and THS3121 amplifiers allow for high output voltage swings at high frequencies. APPLICATIONS * * * * Video Distribution Power FET Driver Pin Driver Capacitive Load Driver The THS3120 and THS3121 are offered in an SOIC-8 (D) package and an MSOP-8 (DGN) PowerPADTM package. DIFFERENTIAL GAIN vs NUMBER OF LOADS DIFFERENTIAL PHASE vs NUMBER OF LOADS 0.07 0.05 0.04 Differential Phase - deg 0.06 Differential Gain - % 0.14 Gain = 2, RF = 649 , VS = 15 V, 40 IRE - NTSC and PAL, Worst Case 100 IRE Ramp PAL 0.03 NTSC 0.02 0.01 VIDEO DISTRIBUTION AMPLIFIER APPLICATION Gain = 2, RF = 649 , 0.12 VS = 15 V, 40 IRE - NTSC and PAL, Worst Case 100 IRE Ramp 0.1 0.08 649 649 15 V PAL - + VI NTSC 0.06 75- Transmission Line 75 -15 V 75 0.04 VO(1) n Lines 75 VO(n) 75 0.02 0 0 1 2 3 4 5 6 7 8 0 0 Number of 150 Loads 1 2 3 4 5 6 Number of 150 Loads 7 8 75 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2009, Texas Instruments Incorporated THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TOP VIEW D, DGN TOP VIEW THS3120 REF VINVIN+ VS- 1 8 2 7 3 6 4 5 D, DGN THS3121 NC VINVIN+ VS- PD VS+ VOUT NC NC = No Internal Connection 1 8 2 7 3 6 4 5 NC VS+ VOUT NC NC = No Internal Connection NOTE: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionally, the REF pin functional range is from VS- to (VS+ - 4 V). AVAILABLE OPTIONS (1) PACKAGED DEVICE TA PLASTIC SMALL OUTLINE SOIC (D) 0C to +70C -40C to +85C 0C to +70C -40C to +85C (1) (2) (3) PLASTIC MSOP (DGN) THS3120CD THS3120CDGN THS3120CDR THS3120CDGNR THS3120ID THS3120IDGN THS3120IDR THS3120IDGNR THS3121CD THS3121CDGN THS3121CDR THS3121CDGNR THS3121ID THS3121IDGN THS3121IDR THS3121IDGNR (2) (3) SYMBOL AQA APN AQO APO For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Available in tape and reel. The R suffix standard quantity is 2500 (for example, THS3120CDGNR). The PowerPAD is electrically isolated from all other pins. DISSIPATION RATING TABLE POWER RATING TJ = +125C PACKAGE JC (C/W) JA (C/W) TA = +25C TA = +85C D-8 (1) 38.3 95 1.05 W 421 mW 4.7 58.4 1.71 W 685 W DGN-8 (1) (2) 2 (2) These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the JA is +95C/W with power rating at TA = +25C of 1.05 W. These data were taken using 2 oz. (56,7 grams) trace and copper pad that is soldered directly to a 3 inch x 3 inch (76,2 mm x 76,2 mm) PCB. For further information, see the Application Information section of this data sheet. Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Dual supply 5 15 Single supply 10 30 0 +70 Industrial -40 +85 Operating junction temperature, continuous operating, TJ -40 +125 C Normal storage temperature, TSTG -40 +85 C Supply voltage Commercial Operating free-air temperature, TA V C ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature, unless otherwise noted. PARAMETER UNIT Supply voltage, VS- to VS+ 33 V Input voltage, VI VS Differential input voltage, VID 4 V Output current, IO (2) 550 mA Continuous power dissipation Maximum junction temperature, TJ See Dissipation Ratings Table (3) +150C Maximum junction temperature, continuous operation, long-term reliability, TJ (4) Commercial Operating free-air temperature, TA Industrial Storage temperature, TSTG ESD ratings: (1) (2) (3) (4) +125C 0C to +70C -40C to +85C -65C to +125C HBM 1000 CDM 1500 MM 200 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The THS3120 and THS3121 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about using the PowerPAD thermally-enhanced package. The absolute maximum temperature under any condition is limited by the constraints of the silicon process. The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 3 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS At VS = 15 V, RF = 649 , RL = 50 , and G = 2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS +25C OVER TEMPERATURE +25C 0C to +70C -40C to +85C UNIT MIN/TYP/ MAX MHz TYP V/s TYP AC PERFORMANCE G = 1, RF = 806 , VO = 200 mVPP 130 G = 2, RF = 649 , VO = 200 mVPP 120 G = 5, RF = 499 , VO = 200 mVPP 105 G = 10, RF = 301 , VO = 200 mVPP 66 0.1-dB bandwidth flatness G = 2, RF = 649 , VO = 200 mVPP 90 Large-signal bandwidth G = 5, RF = 499 , VO = 2 VPP Small-signal bandwidth, -3 dB 80 G = 1, VO = 4-V step, RF = 806 1500 G = 2, VO = 8-V step, RF = 649 1700 Slew rate Recommended maximum SR for repetitive signals (1) 900 V/s MAX Rise and fall time G = -5, VO = 10-V step, RF = 499 10 ns TYP Settling time to 0.1% G = -2, VO = 2 VPP step 11 Settling time to 0.01% G = -2, VO = 2 VPP step 52 ns TYP dBc TYP Slew rate (25% to 75% level) Harmonic distortion 2nd harmonic distortion RL = 50 51 RL = 499 53 RL = 50 50 3rd harmonic distortion G = 2, RF = 649 , VO = 2 VPP, f = 10 MHz Input voltage noise f > 20 kHz 2.5 nV/Hz TYP Noninverting input current noise f > 20 kHz 1 pA/Hz TYP Inverting input current noise f > 20 kHz 10 pA/Hz TYP Differential gain Differential phase RL = 499 G = 2, RL = 150 , RF = 649 65 NTSC 0.007% PAL 0.007% NTSC 0.018 PAL 0.022 TYP DC PERFORMANCE Transimpedance Input offset voltage Average offset voltage drift Noninverting input bias current Average bias current drift Inverting input bias current Average bias current drift Input offset current Average offset current drift VO = 3.75 V, Gain = 1 VCM = 0 V VCM = 0 V VCM = 0 V VCM = 0 V 1.9 1.3 1 1 M MIN 3 10 12 13 mV MAX 10 10 V/C TYP 1 4 6 6 A MAX 10 10 nA/C TYP 3 15 20 20 A MAX 10 10 nA/C TYP 4 15 20 20 A MAX 30 30 nA/C TYP V MIN INPUT CHARACTERISTICS Input common-mode voltage range Common-mode rejection ratio VCM = 12.5 V 12.7 12.5 12.2 12.2 70 63 60 60 dB MIN Noninverting input resistance 41 M TYP Noninverting input capacitance 0.4 pF TYP V MIN MIN OUTPUT CHARACTERISTICS RL = 1 k 14 13.5 13 13 RL = 50 13.5 12.5 12 12 Output current (sourcing) RL = 25 475 425 400 400 mA Output current (sinking) RL = 25 490 425 400 400 mA MIN Output impedance f = 1 MHz, closed loop 0.04 TYP Output voltage swing (1) 4 For more information, see the Application Information section of this data sheet. Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) At VS = 15 V, RF = 649 , RL = 50 , and G = 2, unless otherwise noted. TYP OVER TEMPERATURE +25C +25C 0C to +70C -40C to +85C Specified operating voltage 15 16 16 Maximum quiescent current 7 8.5 11 Minimum quiescent current 7 5.5 PARAMETER TEST CONDITIONS UNIT MIN/TYP/ MAX 16 V MAX 11 mA MAX 4 4 mA MIN POWER SUPPLY Power-supply rejection (+PSRR) VS+ = 15.5 V to 14.5 V, VS- = 15 V 75 65 60 60 dB MIN Power-supply rejection (-PSRR) VS+ = 15 V, VS- = -15.5 V to -14.5 V 69 60 55 55 dB MIN POWER-DOWN CHARACTERISTICS (THS3120 Only) REF voltage range VS+ - 4 (2) PD REF + 0.8 Enable Power-down voltage level (2) PD REF + 2 V 300 VPD = 0 V, REF = 0 V, 11 VPD = 3.3 V, REF = 0 V 11 Turn-on time delay 90% of final value 4 Turn-off time delay 10% of final value 6 PD pin bias current Input impedance (2) 3.4 || 1.7 MAX MIN MIN V PD REF +2 Disable Power-down quiescent current V VS- MAX 450 500 500 A MAX A TYP s TYP k || pF TYP For more information, see the Application Information section of this data sheet. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 5 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS At VS = 5 V, RF = 750 , RL = 50 , and G = 2, unless otherwise noted. TYP PARAMETER TEST CONDITIONS +25C OVER TEMPERATURE +25C 0C to +70C -40C to +85C UNIT MIN/TYP/ MAX MHz TYP V/s TYP AC PERFORMANCE G = 1, RF = 909 , VO = 200 mVPP 105 G = 2, RF = 750 , VO = 200 mVPP 100 G = 5, RF = 499 , VO = 200 mVPP 95 G = 10, RF = 301 , VO = 200 mVPP 70 0.1-dB bandwidth flatness G = 2, RF = 750 , VO = 200 mVPP 70 Large-signal bandwidth G = 2, RF = 750 , VO = 2 VPP 85 G = 1, VO = 2-V step, RF = 909 560 G = 2, VO = 2-V step, RF = 750 620 Slew rate Recommended maximum SR for repetitive signals (1) 900 V/s MAX Rise and fall time G = -5, VO = 5-V step, RF = 499 10 ns TYP Settling time to 0.1% G = -2, VO = 2 VPP step 7 Settling time to 0.01% G = -2, VO = 2 VPP step 42 ns TYP dBc TYP Small-signal bandwidth, -3 dB Slew rate (25% to 75% level) Harmonic distortion 2nd harmonic distortion RL = 50 51 RL = 499 53 RL = 50 48 3rd harmonic distortion G = 2, RF = 649 , VO = 2 VPP, f = 10 MHz Input voltage noise f > 20 kHz 2.5 nV/Hz TYP Noninverting input current noise f > 20 kHz 1 pA/Hz TYP Inverting input current noise f > 20 kHz 10 pA/Hz TYP Differential gain Differential phase G = 2, RL = 150 , RF = 806 RL = 499 60 NTSC 0.008% PAL 0.008% NTSC 0.014 PAL 0.018 TYP DC PERFORMANCE Transimpedance Input offset voltage Average offset voltage drift Noninverting input bias current Average bias current drift Inverting input bias current Average bias current drift Input offset current Average offset current drift VO = 1.25 V, gain = 1 VCM = 0 V VCM = 0 V VCM = 0 V VCM = 0 V 1.2 0.9 0.7 0.7 M MIN 6 10 12 13 mV MAX 10 10 V/C TYP 1 4 6 6 A MAX 10 10 nA/C TYP 2 15 20 20 A MAX 10 10 nA/C TYP 2 15 20 20 A MAX 30 30 nA/C TYP V MIN INPUT CHARACTERISTICS Input common-mode voltage range Common-mode rejection ratio VCM = 2.5 V 2.7 2.5 2.3 2.3 66 62 58 58 dB MIN Noninverting input resistance 35 M TYP Noninverting input capacitance 0.5 pF TYP V MIN MIN OUTPUT CHARACTERISTICS RL = 1 k 4 3.8 3.7 3.7 RL = 50 3.9 3.7 3.6 3.6 Output current (sourcing) RL = 10 310 250 200 200 mA Output current (sinking) RL = 10 325 250 200 200 mA MIN Output impedance f = 1 MHz 0.05 TYP Output voltage swing (1) 6 For more information, see the Application Information section of this data sheet. Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 ELECTRICAL CHARACTERISTICS (continued) At VS = 5 V, RF = 750 , RL = 50 , and G = 2, unless otherwise noted. TYP OVER TEMPERATURE +25C +25C 0C to +70C -40C to +85C Specified operating voltage 5 4.5 4.5 4.5 V MIN Maximum quiescent current 6.5 8 10 10 mA MAX PARAMETER TEST CONDITIONS UNIT MIN/TYP/ MAX POWER SUPPLY Minimum quiescent current 6.5 4 3.5 3.5 mA MIN Power-supply rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS- = 5 V 71 62 57 57 dB MIN Power-supply rejection (-PSRR) VS+ = 5 V, VS- = -5.5 V to -4.5 V 66 57 52 52 dB MIN POWER-DOWN CHARACTERISTICS (THS3120 Only) REF voltage range VS+ - 4 (2) PD REF + 0.8 Enable Power-down voltage level (2) PD REF + 2 V 200 VPD = 0 V, REF = 0 V, 11 VPD = 3.3 V, REF = 0 V 11 Turn-on time delay 90% of final value 4 Turn-off time delay 10% of final value 6 PD pin bias current Input impedance (2) 3.4 || 1.7 MAX MIN MIN V PD REF +2 Disable Power-down quiescent current V VS- MAX 450 500 500 A MAX A TYP s TYP k || pF TYP For more information, see the Application Information section of this data sheet. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 7 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS 15-V Graphs FIGURE Noninverting small-signal gain frequency response 1, 2 Inverting small-signal gain frequency response 3 0.1-dB flatness 4 Noninverting large-signal gain frequency response 5 Inverting large-signal gain frequency response 6 Frequency response capacitive load 7 Recommended RISO vs Capacitive load 2nd harmonic distortion vs Frequency 8 9 3rd harmonic distortion vs Frequency 10 Harmonic distortion vs Output voltage swing 11, 12 Slew rate vs Output voltage step 13, 14 Noise vs Frequency 15 Settling time 16, 17 Quiescent current vs Supply voltage 18 Output voltage vs Load resistance 19 Input bias and offset current vs Case temperature 20 Input offset voltage vs Case temperature 21 Transimpedance vs Frequency 22 Rejection ratio vs Frequency 23 Noninverting small-signal transient response 24 Inverting large-signal transient response 25 Overdrive recovery time 26 Differential gain vs Number of loads 27 Differential phase vs Number of loads 28 Closed-loop output impedance vs Frequency 29 Power-down quiescent current vs Supply voltage 30 Turn-on and turn-off time delay 31 5-V Graphs FIGURE Noninverting small-signal gain frequency response 32 Inverting small-signal gain frequency response 33 0.1-dB flatness 34 Slew rate vs Output voltage step 2nd harmonic distortion vs Frequency 3rd harmonic distortion vs Frequency Harmonic distortion vs Output voltage swing 35, 36 37 38 39, 40 Noninverting small-signal transient response 41 Inverting small-signal transient response Input bias and offset current 42 vs Case temperature 43 Overdrive recovery time 44 Settling time Rejection ratio 8 Submit Documentation Feedback 45 vs Frequency 46 Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (15 V) blank NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 RF = 475 RF = 649 7 Noninverting Gain - dB 6 5 RF = 750 4 3 Gain = 2, RL = 50 , VO = 0.2 VPP, VS = 15 V 1 18 16 14 12 G = 5, RF = 499 10 M 100 M G = 2, RF = 649 8 6 4 2 1G 100 k 100 k 1M 10 M 100 M NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 16 G = 5, RF = 499 14 G = -5, RF = 499 14 12 5.9 12 10 8 G = 2, RF = 681 6 4 RL = 50 , VO = 2 VPP, VS = 15 V 2 0 100 k 5.7 1M 10 M 100 M 1M 10 8 G =-1, RF = 681 6 4 2 RL = 50 , VO = 2 VPP, VS = 15 V 0 -2 10 M 100 M -4 1G 1M 10 M f - Frequency - Hz f - Frequency - Hz 100 M Figure 5. Figure 6. FREQUENCY RESPONSE CAPACITIVE LOAD RECOMMENDED RISO vs CAPACITIVE LOAD 2nd HARMONIC DISTORTION vs FREQUENCY 12 R(ISO) = 40.2 CL = 22 pF 10 R(ISO) = 30 CL = 47 pF 8 6 R(ISO) = 20 CL = 100 pF 4 Gain = 5, RL = 50 VS = 15 V 10 M -30 60 Recommended R ISO Resistance - R(ISO) = 49.9 CL = 10 pF 14 Gain = 5, RL = 50 , VS = 15 V 50 40 30 20 10 0 10 100 M 100 CL - Capacitive Load - pF Capacitive Load - Hz Figure 7. 1G f - Frequency - Hz Figure 4. 16 1G f - Frequency - Hz 0.1-dB FLATNESS 6 100 k G = -1, RF = 681 Figure 3. Noninverting Gain - dB Noninverting Gain - dB 1G G = -2, RF = 681 Figure 2. 5.8 Signal Gain - dB 100 M 0 -2 -4 16 6.1 8 6 4 2 Figure 1. Gain = 2, RF = 562 , RL = 50 , VO = 0.2 VPP, VS = 15 V 6.2 -2 10 M G = -5, RF = 499 10 f - Frequency - Hz 6.3 0 1M RL = 50 , VO = 0.2 VPP, VS = 15 V G = -10, RF = 365 18 16 14 12 G = 1, RF = 806 f - Frequency - Hz 2 24 22 20 RL = 50 , VO = 0.2 VPP, VS = 15 V 10 0 -2 -4 0 1M G = 10, RF = 301 Inverting Gain - dB 2 24 22 20 2 nd Harmonic Distortion - dBc Noninverting Gain - dB 8 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE Inverting Gain - dB NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE Figure 8. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 -40 VO = 2 VPP, RL = 50 , VS = 15 V G = 5, RF = 499 -50 G = 2, RF = 649 -60 -70 -80 G = 2, RF = 649 , RL = 499 -90 -100 100 k 1M 10 M 100 M f - Frequency - Hz Figure 9. Submit Documentation Feedback 9 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (15 V) (continued) blank 3rd HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING -75 G = 5, RF = 499 -50 -60 G = 2, RF = 649 -70 -80 G = 2, RF = 649 , RL = 499 -90 HD3, RL = 50 -80 10 M 1M f - Frequency - Hz HD2, RL = 499 -90 -95 100 M 1 2 3 4 5 6 7 8 9 HD2, RL = 50 -50 -60 HD3, RL = 50 -70 HD2, RL = 499 Gain = 2, RF = 649 , f = 8 MHz VS = 15 V -80 HD3, RL = 499 HD3, RL = 499 0 -90 0 10 1 2 3 4 5 6 Figure 10. Figure 11. Figure 12. SLEW RATE vs OUTPUT VOLTAGE STEP SLEW RATE vs OUTPUT VOLTAGE STEP NOISE vs FREQUENCY Rise Fall 1000 800 600 1400 Hz Rise 1200 1000 Fall 800 600 400 400 200 200 0.5 1 1.5 2 2.5 3 3.5 4 0 4.5 5 1 2 Figure 13. SETTLING TIME Rising Edge 1 0.5 VO - Output Voltage - V 0.75 Gain = -2 RL = 50 RF = 499 VS = 15 V 0.25 0 -0.25 -0.5 -0.75 Falling Edge -1 -1.25 0 2 4 6 8 10 t - Time - ns 12 10 Vn 3 4 5 6 7 8 9 10 0.1 14 Figure 16. Submit Documentation Feedback 16 1 Figure 14. Figure 15. SETTLING TIME QUIESCENT CURRENT vs SUPPLY VOLTAGE 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 10 Rising Edge Gain = -2 RL = 50 RF = 499 VS = 15 V Falling Edge 4 6 8 10 12 TA = 25 C 8 7 TA = -40 C 6 5 4 3 2 1 0 2 100 TA = 85 C 9 0 10 f - Frequency - kHz VO - Output Voltage -VPP VO - Output Voltage -VPP 1.25 10 In+ I Q - Quiescent Current - mA 0 9 In- 1 0.01 0 0 I n - Current Noise - pA/ Hz 1200 1600 V n - Voltage Noise - nV/ 1400 Gain = 2 RL = 50 RF = 649 VS = 15 V 1800 SR - Slew Rate - V/ s 1600 8 100 2000 Gain = 1 RL = 50 RF = 806 VS = 15 V 1800 7 VO - Output Voltage Swing - VPP VO - Output Voltage Swing - VPP 2000 VO - Output Voltage - V Gain = 2, RF = 649 , f= 1 MHz VS = 15 V -85 -100 100 k Harmonic Distortion - dBc -40 HD2, RL = 50 Harmonic Distortion - dBc 3rd Harmonic Distortion - dBc VO = 2 VPP, RL = 50 , VS = 15 V -100 SR - Slew Rate - V/ s -40 -70 -30 10 HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING 14 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VS - Supply Voltage - V t - Time - ns Figure 17. Figure 18. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (15 V) (continued) blank INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 6 VS = 15 V 3.5 VOS - Input Offset Voltage - mV IIB- 3 2.5 VS = 15 V TA = -40 to 85C 2 IOS 1.5 1 IIB+ 0.5 10 100 VS = 5 V 3 2 1 TC - Case Temperature - C Figure 19. Figure 20. Figure 21. TRANSIMPEDANCE vs FREQUENCY REJECTION RATIO vs FREQUENCY NONINVERTING SMALL-SIGNAL TRANSIENT RESPONSE 0.3 70 VS = 15 V CMRR 90 0.25 60 Rejection Ratio - dB VS = 15 V 70 VS = 5 V 50 40 30 0.2 VO - Output Voltage - V 80 50 PSRR- 40 30 20 PSRR+ 20 0 0 1M 10 M 100 M 1G 100 k 1M 10 M 100 M f - Frequency - Hz f - Frequency - Hz Figure 22. Figure 23. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Output 0.15 0.1 Input 0.05 0 -0.05 -0.1 -0.15 -0.2 10 10 100 k VS = 15 V 4 TC - Case Temperature - C 100 60 5 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 1000 RL - Load Resistance - Transimpedance Gain - dB ohms INPUT OFFSET VOLTAGE vs CASE TEMPERATURE 4 I IB - Input Bias Current - A I OS - Input Offset Current - A VO - Output Voltage - V OUTPUT VOLTAGE vs LOAD RESISTANCE Gain = 2, RL = 50 , RF = 649 , VS = 15 V -0.25 -0.3 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 t - Time - s Figure 24. Submit Documentation Feedback 11 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (15 V) (continued) blank INVERTING LARGE-SIGNAL TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME 20 Output Output Voltage - V 2 1 0 Input -1 -2 Gain = -5, RL = 50 , RF = 499 , VS = 15 V -3 -4 -5 -6 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1 0 0 0.04 PAL 0.03 -5 -1 -10 -2 -15 -3 0.01 -20 -4 1 0 0 0.11 0.12 0.2 0.4 0.6 0.8 NTSC 0.02 0 t - Time - s 1 2 3 4 5 6 7 Figure 26. Figure 27. DIFFERENTIAL PHASE vs NUMBER OF LOADS CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY POWER-DOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE ZO - Closed-Loop Output Impedance - Gain = 2, RF = 649 , 0.12 VS = 15 V, 40 IRE - NTSC and PAL, Worst Case 100 IRE Ramp 0.1 0.08 PAL NTSC 0.06 0.04 0.02 0 1 2 3 4 5 6 7 400 100 Gain = 2, RF = 649 , VS = 15 V 10 1 0.1 350 300 TA = 85C 250 TA = -40C 200 TA = 25C 150 100 50 0 0.01 8 8 Number of 150 Loads Figure 25. 0.14 Differential Phase - 0.05 Gain = 2, RF = 649 , VS = 15 V, 40 IRE - NTSC and PAL, Worst Case 100 IRE Ramp 0.06 2 5 t - Time - s 0 3 Powerdown Quiescent Current - A VO - Output Voltage - V 10 3 0.07 4 Gain = 2, RF = 648 , VS = 15 V 15 Differential Gain - % 5 VI - Input Voltage - V 6 4 DIFFERENTIAL GAIN vs NUMBER OF LOADS 1M 10 M Number of 150 Loads 100 M 3 1G Figure 28. 5 7 9 11 13 15 VS - Supply Voltage - V f - Frequency - Hz Figure 29. Figure 30. TURN-ON AND TURN-OFF TIME DELAY 1.5 Output Voltage PowerDown Pulse - V VO - Output Voltage Level - V 1 0.5 0 -0.5 Powerdown Pulse 6 5 4 3 Gain = 5, VI = 0.1 Vdc RL = 50 VS = 15 V and 5 V 0 0.1 0.2 0.3 2 1 0 -1 0.4 0.5 0.6 0.7 t - Time - ms Figure 31. 12 Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 TYPICAL CHARACTERISTICS (5 V) blank RL = 50 , VO = 0.2 VPP, VS = 5 V G = 10, RF = 301 22 20 18 16 G = 5, RF = 499 Inverting Gain - dB 14 12 10 G = 2, RF = 750 8 6 4 G = 1, RF = 909 2 0 -2 -4 24 22 20 18 16 10 M 100 M G = -5, RF = 499 10 8 G = -2, RF = 681 6 4 2 G = -1, RF = 750 1M 1G 6 5.9 5.8 100 M 10 M 5.7 1G 1M 10 M 100 M f - Frequency - Hz Figure 32. Figure 33. Figure 34. SLEW RATE vs OUTPUT VOLTAGE STEP SLEW RATE vs OUTPUT VOLTAGE STEP 2nd HARMONIC DISTORTION vs FREQUENCY 700 Gain = 1 RL = 50 RF = 909 VS = 5 V -30 Rise Rise 500 Fall 400 300 200 500 Fall 400 300 200 Gain = 2 RL = 50 RF = 750 VS = 5 V 100 100 0 0 0 1 2 3 4 2nd Harmonic Destortion - dBc 600 SR - Slew Rate - V/ s 600 SR - Slew Rate - V/ s 6.1 f - Frequency - Hz 700 -40 G = -5, RF = 499 -50 -60 G = -2, RF = 649 -70 -80 VO = 2 VPP, RL = 100 , VS = 5 V -90 -100 0 5 1 2 3 4 5 6 7 100 k 1M VO - Output Voltage -VPP VO - Output Voltage -VPP 10 M Figure 36. Figure 37. 3rd HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING HARMONIC DISTORTION vs OUTPUT VOLTAGE SWING -70 VO = 2 VPP, RL = 100 , VS = 5 V -40 HD3, RL = 50 HD3, RL = 50 HD3, RL = 50 Harmonic Distortion - dBc -75 -50 G = -5, RF = 499 -60 -70 -80 G = -2, RF = 649 -80 HD2, RL = 499 -85 HD3, RL = 499 -90 Gain = 2, RF = 649 f= 1 MHz VS = 5 V -95 -90 100 k 1M 10 M 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Output Voltage Swing - VPP f - Frequency - Hz Figure 38. -50 -60 -70 HD2, RL = 499 Gain = 2, RF = 649 f= 8 MHz VS = 5 V -80 -90 0 100 M HD3, RL = 50 HD3, RL = 499 -100 -100 100 M f - Frequency - Hz Figure 35. -30 3rd Harmonic Distortion - dBc Gain = 2, RF = 750 , RL = 50 , VO = 0.2 VPP, VS = 5 V 6.2 14 12 f - Frequency - Hz -40 RL = 50 , VO = 0.2 VPP, VS = 5 V G = -10, RF = 365 0 -2 -4 1M 0.1-dB FLATNESS 6.3 Harmonic Distortion - dBc Noninverting Gain - dB 24 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE Noninverting Gain - dB NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE Figure 39. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VO - Output Voltage Swing - VPP Figure 40. Submit Documentation Feedback 13 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (5 V) (continued) blank INVERTING LARGE-SIGNAL TRANSIENT RESPONSE 0.3 Output 0.15 VO - Output Voltage - V Input 0.1 0.05 0 -0.05 -0.1 Gain = 2 RL = 50 RF = 750 VS = 5 V -0.15 -0.2 -0.25 10 20 30 Output 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 Input Gain = -5, RL = 50 , RF = 499 , VS = 5 V -2.5 -3 -3.5 -0.3 0 VS = 5 V 40 50 60 70 10 20 OVERDRIVE RECOVERY TIME 1 Gain = 2, RF = 750 , VS = 5 V 0.8 1 0.6 0.75 2 0.4 1 0.2 0 0 -1 -0.2 -2 -0.4 -3 -0.6 -4 -0.8 -5 -1 VO - Output Voltage - V VO - Output Voltage - V 30 40 50 60 1 IIB+ 0.75 0.5 IOS -40-30-20-10 0 10 20 30 40 50 60 70 80 90 70 TC - Case Temperature - C Figure 42. Figure 43. SETTLING TIME REJECTION RATIO vs FREQUENCY 70 1.25 VI - Input Voltage - V 5 VS = 5 V 60 Rising Edge 0.5 0.25 Gain = -2 RL = 50 RF = 681 VS = 5 V 0 -0.25 -0.5 50 40 PSRR- 30 CMRR 20 -0.75 0 0.2 0.4 0.6 0.8 1 t - Time - s Falling Edge -1 -1.25 Figure 44. Submit Documentation Feedback PSRR+ 10 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 t - Time - ns 14 IIB- 1.25 t - Time - s Figure 41. 3 1.5 0 0 t - Time - ns 4 1.75 0.25 Rejection Ratio - dB VO - Output Voltage - V 0.2 2 3.5 3 2.5 0.25 I IB - Input Bias Current - A I OS - Input Offset Current - A NONINVERTING SMALL-SIGNAL TRANSIENT RESPONSE INPUT BIAS AND OFFSET CURRENT vs CASE TEMPERATURE 100 k 1M 10 M 100 M f - Frequency - Hz Figure 45. Figure 46. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 APPLICATION INFORMATION MAXIMUM SLEW RATE FOR REPETITIVE SIGNALS The THS3120 and THS3121 are recommended for high slew rate pulsed applications where the internal nodes of the amplifier have time to stabilize between pulses. It is recommended to have at least 20-ns delay between pulses. The THS3120 and THS3121 are not recommended for applications with repetitive signals (sine, square, sawtooth, or other) that exceed 900 V/s. Using the part in these applications results in excessive current draw from the power supply and possible device damage. For applications with high slew rate, repetitive signals, the THS3091 and THS3095 (single), or THS3092 and THS3096 (dual) are recommended. WIDEBAND, NONINVERTING OPERATION The THS3120 and THS3121 are unity-gain stable 130-MHz current-feedback operational amplifiers, designed to operate from a 5-V to 15-V power supply. Figure 47 shows the THS3121 in a noninverting gain of 2-V/V configuration typically used to generate the Typical Characteristics. Most of the curves were characterized using signal sources with 50- source impedance, and with measurement equipment presenting a 50- load impedance. 15 V +VS Current-feedback amplifiers are highly dependent on the feedback resistor RF for maximum performance and stability. Table 1 shows the optimal gain setting resistors RF and RG at different gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for RF. Conversely, increasing RF decreases the bandwidth, but stability is improved. Table 1. Recommended Resistor Values for Optimum Frequency Response THS3120 AND THS3121 RF AND RG VALUES FOR MINIMAL PEAKING WITH RL = 50 GAIN (V/V) SUPPLY VOLTAGE (V) RG () RF () 15 -- 806 5 -- 909 15 649 649 5 750 750 15 124 499 1 2 5 5 124 499 15 33.2 301 5 33.2 301 15 681 681 5 750 750 -2 15 and 5 340 681 -5 15 and 5 100 499 -10 15 and 5 36.5 365 10 -1 + 0.1 F 50 Source + VI 49.9 THS3120 49.9 _ 50 LOAD RF 649 6.8 F 649 RG 0.1 F 6.8 F + -VS -15 V Figure 47. Wideband, Noninverting Gain Configuration Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 15 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com WIDEBAND, INVERTING OPERATION +VS Figure 48 shows the THS3121 in a typical inverting gain configuration where the input and output impedances and signal gain from Figure 47 are retained in an inverting circuit configuration. 50 Source + VI 49.9 RT 15 V +VS 0.1 F THS3120 VI RF 649 6.8 F +VS 2 RF 50 LOAD RG RF 340 RM 59 681 VS 50 Source RG VI 0.1 F 6.8 F 340 RT 59 + -15 V 50 LOAD RG 649 49.9 _ 50 Source _ +VS 2 + + 49.9 THS3120 Figure 48. Wideband, Inverting Gain Configuration _ 49.9 THS3120 + 50 LOAD +VS 2 +VS 2 -VS 681 Figure 49. DC-Coupled, Single-Supply Operation Video Distribution SINGLE-SUPPLY OPERATION The THS3120 and THS3121 have the capability to operate from a single supply voltage ranging from 10 V to 30 V. When operating from a single power supply, biasing the input and output at mid-supply allows for the maximum output voltage swing. The circuits of Figure 49 show inverting and noninverting amplifiers configured for single-supply operation. The wide bandwidth, high slew rate, and high output drive current of the THS3120 and THS3121 matches the demands for video distribution for delivering video signals down multiple cables. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality. 649 649 15 V + VI 75 75- Transmission Line -15 V n Lines 75 VO(1) 75 VO(n) 75 75 Figure 50. Video Distribution Amplifier Application 16 Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 Driving Capacitive Loads Applications such as FET drivers and line drivers can be highly capacitive and cause stability problems for high-speed amplifiers. Figure 51 through Figure 57 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier feedback path. See Figure 51 for recommended resistor values versus capacitive load. Recommended R ISO Resistance - 60 Gain = 5, RL = 50 , VS = 15 V 50 40 30 20 10 0 10 100 CL - Capacitive Load - pF Figure 51. Recommended RISO vs Capacitive Load Placing a small series resistor, RISO, between the amplifier output and the capacitive load, as shown in Figure 52, is an easy way of isolating the load capacitance. Using a ferrite chip in place of RISO, as shown in Figure 53, is another approach of isolating the output of the amplifier. The ferrite impedance characteristic versus frequency is useful to maintain the low frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a ferrite chip with similar impedance to RISO, 20 to 50 , at 100 MHz and low impedance at dc. Figure 54 shows another method used to maintain the low frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series with the negative input is used to stabilize the amplifier and should be equal to the recommended value of RF at unity gain. Replacing RIN with a ferrite chip of similar impedance at about 100 MHz as illustrated in Figure 55 gives similar results with reduced dc offset and low frequency noise. (See the Additional Reference Material section for expanding the usability of current-feedback amplifiers.) RF 499 124 _ 5.11 + RISO -VS VS 27 pF VS 100 LOAD RIN RG 124 1 F 499 49.9 750 VS _ + -VS VS 100 LOAD 5.11 1 F 49.9 Figure 52. Resistor to Isolate Capacitive Load Figure 54. Feedback Technique with Input Resistor for Capacitive Load 499 124 VS _ Ferrite Bead + -VS VS 100 LOAD 1 F 49.9 Figure 53. Ferrite Bead to Isolate Capacitive Load Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 17 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com Figure 57 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier. RF 27 pF 499 FIN RG FB 124 VS VS _ 5.11 + _ + 1 F -VS VS 100 LOAD 5.11 VS -VS 49.9 301 66.5 301 Figure 55. Feedback Technique with Input Ferrite Bead for Capacitive Load VS _ Figure 56 is shown using two amplifiers in parallel to double the output drive current to larger capacitive loads. This technique is used when more output current is needed to charge and discharge the load faster as when driving large FET transistors. 499 124 24.9 5.11 + 499 124 24.9 VS _ -VS -VS Figure 57. PowerFET Drive Circuit The THS3120 features a power-down pin (PD) which lowers the quiescent current from 7 mA down to 300 A, ideal for reducing system power. -VS VS + SAVING POWER WITH POWER-DOWN FUNCTIONALITY AND SETTING THRESHOLD LEVELS WITH THE REFERENCE PIN VS _ 5.11 1 nF 5.11 + -VS Figure 56. Parallel Amplifiers for Higher Output Drive The power-down pin of the amplifier defaults to the REF pin voltage in the absence of an applied voltage, putting the amplifier in the normal on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the positive rail. The threshold voltages for power-on and power-down are relative to the supply rails and are given in the specification tables. Below the Enable Threshold Voltage, the device is on. Above the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs. 18 Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 Figure 58 shows the total system output impedance which includes the amplifier output impedance in parallel with the feedback plus gain resistors, which cumulate to 1298 . Figure 47 shows this circuit configuration for reference. Powerdown Output Impedance - 1400 Gain = 2 RF = 649 VS = 15 V and 5 V 1200 1000 800 600 400 200 0 100 k 1M 10 M 100 M 1G f - Frequency - Hz Figure 58. Power-down Output Impedance vs Frequency POWER-DOWN REFERENCE PIN OPERATION In addition to the power-down pin, the THS3120 features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. In most split-supply applications, the reference pin is connected to ground. In either case, the user needs to be aware of voltage-level thresholds that apply to the power-down pin. Table 2 shows examples and illustrate the relationship between the reference voltage and the power-down thresholds. In the table, the threshold levels are derived by the following equations: PD REF + 0.8 V for enable PD REF + 2 V for disable where the usable range at the REF pin is VS- VREF (VS+ - 4 V). The recommended mode of operation is to tie the REF pin to midrail, thus settings the enable/disable threshold to V(midrail) + 0.8 V and V(midrail) = 2 V respectively. Table 2. Power-Down Threshold Voltage Levels As with most current-feedback amplifiers, the internal architecture places some limitations on the system when in power-down mode. Most notably is the fact that the amplifier actually turns ON if there is a 0.7 V or greater difference between the two input nodes (V+ and V-) of the amplifier. If this difference exceeds 0.7 V, the output of the amplifier creates an output voltage equal to approximately [(V+) - (V-) - 0.7 V] x Gain. Also, if a voltage is applied to the output while in power-down mode, the V- node voltage is equal to VO(applied) x RG/(RF + RG). For low gain configurations and a large applied voltage at the output, the amplifier may actually turn ON due to the aforementioned behavior. The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions. SUPPLY VOLTAGE (V) REFERENCE PIN VOLTAGE (V) ENABLE LEVEL (V) DISABLE LEVEL (V) 15, 5 0 0.8 2 15 2 2.8 4 15 -2 -1.2 0 5 1 1.8 3 5 -1 -0.2 1 30 15 15.8 17 10 5 5.8 7 Note that if the REF pin is left unterminated, it floats to the positive rail and falls outside of the recommended operating range given above (VS- VREF VS+ - 4 V). As a result, it no longer serves as a reliable reference for the PD pin, and the enable/disable thresholds given above no longer apply. If the PD pin is also left unterminated, it floats to the positive rail and the device is disabled. If balanced, split supplies are used (VS) and the REF and PD pins are grounded, the device is enabled. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 19 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE Achieving optimum performance with high frequency amplifiers, like the THS3120 and THS3121, requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: * Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. * Minimize the distance [< 0.25 inch, (6,4 mm)] from the power-supply pins to high frequency 0.1-F and 100-pF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (6.8 F or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. * Careful selection and placement of external components preserve the high-frequency performance of the THS3120 and THS3121. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep the leads and printed circuit board (PCB) trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 2.0 k, this parasitic capacitance can add a pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. 20 Submit Documentation Feedback * * Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces [0.05 inch (1,3 mm) to 0.1 inch (2,54 mm)] should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (less than 4 pF) may not need an RS because the THS3120 and THS3121 are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS3120/THS3121 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. Socketing a high-speed part like the THS3120 and THS3121 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS3120/THS3121 parts directly onto the board. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 PowerPAD DESIGN CONSIDERATIONS The THS3120 and THS3121 are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted (see Figure 59a and Figure 59b). This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package (see Figure 59c). Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that devices such as the THS312x have no electrical connection between the PowerPAD and the die. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 59. Views of Thermally-Enhanced Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. PowerPAD LAYOUT CONSIDERATIONS 1. PCB with a top side etch pattern as shown in Figure 60. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 0.01 inch (0,254 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 0.205 (5,21) 0.060 (1,52) 0.017 (0,432) 0.013 (0,33) 0.075 (1,91) 0.094 (2,39) 0.030 (0,76) 0.025 (0,64) 0.010 (0,254) vias 0.035 (0,89) 0.040 (1,01) Dimensions are in inches (millimeters). Figure 60. DGN PowerPAD PCB Etch and Via Pattern 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS3120/THS3121 IC. These additional vias may be larger than the 0.01-inch (0,254 mm) diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any potential voltage such as VS-, is acceptable as there is no electrical connection to the silicon. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS3120/THS3121 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 21 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com POWER DISSIPATION AND THERMAL CONSIDERATIONS The THS3120 and THS3121 incorporate automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately +160C. When the junction temperature reduces to approximately +140C, the amplifier turns on again. But, for maximum performance and reliability, the designer must take care to ensure that the design does not exceed a junction temperature of +125C. Between +125C and +150C, damage does not occur, but the performance of the amplifier begins to degrade and long term reliability suffers. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. T * TA P Dmax + max q JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (C). 4.0 PD - Maximum Power Dissipation - W 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. TJ = +125C 3.5 3.0 qJA = 58.4C/W 2.5 2.0 qJA = 95C/W 1.5 1.0 0.5 qJA = 158C/W 0 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C Results are with no air flow and PCB size = 3 inches x 3 inches (76,2 mm x 76,2 mm); JA = 58.4C/W for MSOP-8 with PowerPAD (DGN); JA = 95C/W for SOIC-8 High-K test PCB (D); JA = 158C/W for MSOP-8 with PowerPAD without solder. Figure 61. Maximum Power Distribution vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. DESIGN TOOLS TA is the ambient temperature (C). Evaluation Fixtures, Spice Models, and Application Support JA = JC + CA JC is the thermal coeffiecient from the silicon junctions to the case (C/W). CA is the thermal coeffiecient from the case to ambient air (C/W). (1) For systems where heat dissipation is more critical, the THS3120 and THS3121 are offered in an MSOP-8 with PowerPAD package offering even better thermal performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note (literature number SLMA002). also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance. 22 Submit Documentation Feedback Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has been developed for the THS3120 and THS3121 operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device. The evaluation board can be ordered through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS3121 is available through the Texas Instruments web site (www.ti.com). The product information center (PIC) is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in the small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. J2 GND TP2 J1 VS+ J7 VSFB2 FB1 VS+ + C3 C5 C4 C2 C1 VS- C6 + PD J7 R5 Z1 R6 0W R4 TP1 VS+ R3 J5 VIN- R8B 7 8 2 _ R1 R8A 6 3 + 1 4 R7A R7B Z2 THS3120DGN EVM 6445588 J6 VOUT VSJ4 VIN+ R2 Figure 63. THS3120 EVM Board Layout (Top Layer) REF J8 NOTE: The Edge number for the THS3121 is 6445589. 1 Figure 62. THS3120 EVM Circuit Configuration Figure 64. THS3120 EVM Board Layout (Bottom Layer) Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 23 THS3120 THS3121 SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009........................................................................................................................................ www.ti.com Table 3. Bill of Materials THS3120DGN and THS3121DGN EVM DESCRIPTION SMD SIZE REFERENCE DESIGNATOR PCB QUANTITY MANUFACTURER'S PART NUMBER (1) 1 Bead, ferrite, 3 A, 80 1206 FB1, FB2 2 (Steward) HI1206N800R-00 2 Cap. 6.8 F, tantalum, 35 V, 10% D C1, C2 2 (AVX) TAJD685K035R 3 Open 0805 R5, Z1 2 4 Cap. 0.1 F, ceramic, X7R, 50 V 0805 C3, C4 2 5 Cap. 100 pF, ceramic, NPO, 100 V 0805 C5, C6 2 (AVX) 08051A101JAT2A 6 Resistor, 0 , 1/8 W, 1% 0805 R6 (2) 1 (Phycomp) 9C08052A0R00JLHFT 7 Resistor, 124 , 1/8 W, 1% 0805 R3 1 (Phycomp) 9C08052A1240FKHFT 8 Resistor, 499 , 1/8 W, 1% 0806 R4 1 (Phycomp) 9C08052A4990FKHFT 9 Open 1206 R7A, Z2 2 10 Resistor, 49.9 , 1/4 W, 1% 1206 R2, R8A 2 (Phycomp) 9C12063A49R9FKRFT 11 Resistor, 0 , 1/4 W, 1% 1206 R1 1 (Phycomp) 9C12063A53R6FKRFT 12 Open 2512 R7B, R8B 2 13 Header, 0.1 inch (2,54 mm) CTRS, 0.025 inch (0,635 mm) sq pins 3 pos. JP1 (2) 1 (Sullins) PZC36SAAN ITEM (1) (2) (AVX) 08055C104KAT2A 14 Shunts JP1 (2) 1 (Sullins) SSC02SYAN 15 Jack, banana receptance, 0.25 inch (6,35 mm) dia. hole J1, J2, J3 3 (SPC) 813 16 Test point, red J7 (2), J8 (2), TP1 3 (Keystone) 5000 17 Test point, black TP2 1 (Keystone) 5001 18 Connector, SMA PCB jack J4, J5, J6 3 (Amphenol) 901-144-8RFX 19 Standoff, 4-40 hex, 0.625 inch (15,88 mm) length 4 (Keystone) 1808 20 Screw, Phillips, 4-40, 0.250 inch (6,35 mm) 4 SHR-0440-016-SN U1 (2) 21 IC, THS3120 1 (TI) THS3120DGN 22 Board, printed-circuit (THS3120) (2) 1 (TI) EDGE # 6445588 23 IC, THS3121 U1 1 (TI) THS3121DGN 24 Board, printed-circuit (THS3121) 1 (TI) EDGE # 6445589 The manufacturer's part numbers were used for test purposes only. Applies to the THS3120DGN EVM only. ADDITIONAL REFERENCE MATERIAL * * * * * * * 24 PowerPAD Made Easy, application brief (SLMA004) PowerPAD Thermally-Enhanced Package, technical brief (SLMA002) Voltage Feedback versus Current-Feedback Amplifiers, (SLVA051) Current Feedback Analysis and Compensation (SLOA021) Current Feedback Amplifiers: Review, Stability, and Application (SBOA081) Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013) Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications Journal www.ti.com/sc/analogapps). Submit Documentation Feedback Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 THS3120 THS3121 www.ti.com........................................................................................................................................ SLOS420E - SEPTEMBER 2003 - REVISED OCTOBER 2009 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (January 2009) to Revision E ............................................................................................... Page * Changed Power-Down Characteristics, Power-down quiescent current test conditions of 15 V Electrical Characteristics ...................................................................................................................................................................... 5 * Changed Power-Down Characteristics, PD pin bias current parameter of 15 V Electrical Characteristics ....................... 5 * Changed Power-Down Characteristics, Power-down quiescent current test conditions of 5 V Electrical Characteristics ...................................................................................................................................................................... 7 * Changed Power-Down Characteristics, PD pin bias current parameter of 5 V Electrical Characteristics ......................... 7 * Updated format of Application Information section ............................................................................................................. 15 * Added caption title to Figure 52 .......................................................................................................................................... 17 * Added caption title to Figure 53 .......................................................................................................................................... 17 * Added caption title to Figure 54 .......................................................................................................................................... 17 * Added caption title to Figure 55 .......................................................................................................................................... 18 * Added caption title to Figure 56 .......................................................................................................................................... 18 * Changed first sentence of second paragraph of the Saving Power with Power-Down Functionality section .................... 18 * Changed last sentence of Power-Down Reference Pin Operation section ........................................................................ 19 Changes from Revision C (February 2007) to Revision D ............................................................................................. Page * Changed input offset voltage values ..................................................................................................................................... 4 * Changed input common-mode voltage range values ........................................................................................................... 4 * Changed power-supply rejection ratio values ....................................................................................................................... 5 * Changed input offset voltage values ..................................................................................................................................... 6 * Changed input common-mode voltage range values ........................................................................................................... 6 * Changed power-supply rejection ratio values ....................................................................................................................... 7 Copyright (c) 2003-2009, Texas Instruments Incorporated Product Folder Link(s): THS3120 THS3121 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) THS3120CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA THS3120CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA THS3120CDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA THS3120ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3120I THS3120IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APN THS3121CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3121C THS3121ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3121I THS3121IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APO THS3121IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APO (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Aug-2018 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS3120CDGNR Package Package Pins Type Drawing MSOPPower PAD DGN 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS3120CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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