0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Gain − %
PAL
NTSC
Gain = 2,
RF = 649 Ω,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
+
−
75 Ω75 Ω
75 Ω
75 Ω
75 Ω
n Lines
VO(1)
VO(n)
75-Ω Transmission Line
VI
649 Ω649 Ω
−15 V
15 V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase − deg
PAL
NTSC
Gain = 2,
RF = 649 Ω,
VS = ±15 V,
40 IRE − NTSC and PAL,
Worst Case ±100 IRE Ramp
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
VIDEO DISTRIBUTION AMPLIFIER APPLICATION
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
LOW-NOISE, HIGH-OUTPUT DRIVE, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
Check for Samples: THS3120 THS3121
1FEATURES DESCRIPTION
23• Low Noise: The THS3120 and THS3121 are low-noise,
high-voltage, high output current drive,
– 1 pA/√Hz Noninverting Current Noise current-feedback amplifiers designed to operate over
– 10 pA/√Hz Inverting Current Noise a wide supply range of ±5 V to ±15 V for today's
– 2.5 nV/√Hz Voltage Noise high-performance applications.
• High Output Current Drive: 475 mA The THS3120 offers a power saving mode by
• High Slew Rate: providing a power-down pin for reducing the 7-mA
quiescent current of the device, when the device is
– 1700 V/μs (RL= 50 Ω, VO=8VPP)not active.
• Wide Bandwidth: 120 MHz (G = 2, RL= 50 Ω)These amplifiers provide well-regulated ac
• Wide Supply Range: ±5 V to ±15 V performance characteristics. Most notably, the 0.1-dB
• Power-Down Feature: (THS3120 Only) flat bandwidth is exceedingly high, reaching beyond
90 MHz. The unity-gain bandwidth of 130 MHz allows
APPLICATIONS for good distortion characteristics at 10 MHz. Coupled
• Video Distribution with high 1700-V/μs slew rate, the THS3120 and
THS3121 amplifiers allow for high output voltage
• Power FET Driver swings at high frequencies.
• Pin Driver
• Capacitive Load Driver The THS3120 and THS3121 are offered in an
SOIC-8 (D) package and an MSOP-8 (DGN)
PowerPAD™ package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
4
8
7
6
5
NC
VIN-
VIN+
VS-
NC
VS+
VOUT
NC
D,DGNTOP VIEWD,DGNTOP VIEW
NC =NoInternalConnection
1
2
3
4
8
7
6
5
REF
VIN-
VIN+
VS-
PD
VS+
VOUT
NC
NC=NoInternalConnection
THS3120 THS3121
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
NOTE: The device with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionally, the
REF pin functional range is from VS– to (VS+ – 4 V).
AVAILABLE OPTIONS(1)
PACKAGED DEVICE
TAPLASTIC SMALL OUTLINE SOIC (D) PLASTIC MSOP (DGN) (2) (3) SYMBOL
THS3120CD THS3120CDGN
0°C to +70°C AQA
THS3120CDR THS3120CDGNR
THS3120ID THS3120IDGN
–40°C to +85°C APN
THS3120IDR THS3120IDGNR
THS3121CD THS3121CDGN
0°C to +70°C AQO
THS3121CDR THS3121CDGNR
THS3121ID THS3121IDGN
–40°C to +85°C APO
THS3121IDR THS3121IDGNR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Available in tape and reel. The R suffix standard quantity is 2500 (for example, THS3120CDGNR).
(3) The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE POWER RATING
TJ= +125°C
PACKAGE θJC (°C/W) θJA (°C/W) TA= +25°C TA= +85°C
D-8(1) 38.3 95 1.05 W 421 mW
DGN-8(2) 4.7 58.4 1.71 W 685 W
(1) These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θJA is +95°C/W with
power rating at TA= +25°C of 1.05 W.
(2) These data were taken using 2 oz. (56,7 grams) trace and copper pad that is soldered directly to a 3 inch x 3 inch (76,2 mm x 76,2 mm)
PCB. For further information, see the Application Information section of this data sheet.
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........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
RECOMMENDED OPERATING CONDITIONS
PARAMETER MIN NOM MAX UNIT
Dual supply ±5 ±15
Supply voltage V
Single supply 10 30
Commercial 0 +70
Operating free-air temperature, TA°C
Industrial –40 +85
Operating junction temperature, continuous operating, TJ–40 +125 °C
Normal storage temperature, TSTG –40 +85 °C
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature, unless otherwise noted.
PARAMETER UNIT
Supply voltage, VS– to VS+ 33 V
Input voltage, VI±VS
Differential input voltage, VID ±4 V
Output current, IO(2) 550 mA
Continuous power dissipation See Dissipation Ratings Table
Maximum junction temperature, TJ(3) +150°C
Maximum junction temperature, continuous operation, long-term reliability, TJ(4) +125°C
Commercial 0°C to +70°C
Operating free-air temperature, TAIndustrial –40°C to +85°C
Storage temperature, TSTG –65°C to +125°C
HBM 1000
ESD ratings: CDM 1500
MM 200
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3120 and THS3121 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI Technical Brief SLMA002 for more information about using the PowerPAD
thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
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SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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ELECTRICAL CHARACTERISTICS
At VS= ±15 V, RF= 649 Ω, RL= 50 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE
0°C to –40°C to MIN/TYP/
PARAMETER TEST CONDITIONS +25°C +25°C +70°C +85°C UNIT MAX
AC PERFORMANCE
G = 1, RF= 806 Ω, VO= 200 mVPP 130
G = 2, RF= 649 Ω, VO= 200 mVPP 120
Small-signal bandwidth, –3 dB G = 5, RF= 499 Ω, VO= 200 mVPP 105 MHz TYP
G = 10, RF= 301 Ω, VO= 200 mVPP 66
0.1-dB bandwidth flatness G = 2, RF= 649 Ω, VO= 200 mVPP 90
Large-signal bandwidth G = 5, RF= 499 Ω, VO= 2 VPP 80
G = 1, VO= 4-V step, RF= 806 Ω1500
Slew rate (25% to 75% level) V/µs TYP
G = 2, VO= 8-V step, RF= 649 Ω1700
Recommended maximum SR for
Slew rate 900 V/µs MAX
repetitive signals(1)
Rise and fall time G = –5, VO= 10-V step, RF= 499 Ω10 ns TYP
Settling time to 0.1% G = –2, VO= 2 VPP step 11 ns TYP
Settling time to 0.01% G = –2, VO= 2 VPP step 52
Harmonic distortion
RL= 50 Ω51
2nd harmonic distortion G = 2, RL= 499 Ω53
RF= 649 Ω,dBc TYP
VO= 2 VPP,RL= 50 Ω50
f = 10 MHz
3rd harmonic distortion RL= 499 Ω65
Input voltage noise f > 20 kHz 2.5 nV/√Hz TYP
Noninverting input current noise f > 20 kHz 1 pA/√Hz TYP
Inverting input current noise f > 20 kHz 10 pA/√Hz TYP
NTSC 0.007%
Differential gain G = 2, PAL 0.007%
RL= 150 Ω, TYP
NTSC 0.018°
RF= 649 Ω
Differential phase PAL 0.022°
DC PERFORMANCE
Transimpedance VO= ±3.75 V, Gain = 1 1.9 1.3 1 1 MΩMIN
Input offset voltage 3 10 12 13 mV MAX
VCM = 0 V
Average offset voltage drift ±10 ±10 μV/°C TYP
Noninverting input bias current 1 4 6 6 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Inverting input bias current 3 15 20 20 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Input offset current 4 15 20 20 μA MAX
VCM = 0 V
Average offset current drift ±30 ±30 nA/°C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ±12.7 ±12.5 ±12.2 ±12.2 V MIN
Common-mode rejection ratio VCM = ±12.5 V 70 63 60 60 dB MIN
Noninverting input resistance 41 MΩTYP
Noninverting input capacitance 0.4 pF TYP
OUTPUT CHARACTERISTICS
RL= 1 kΩ±14 ±13.5 ±13 ±13
Output voltage swing V MIN
RL= 50 Ω±13.5 ±12.5 ±12 ±12
Output current (sourcing) RL= 25 Ω475 425 400 400 mA MIN
Output current (sinking) RL= 25 Ω490 425 400 400 mA MIN
Output impedance f = 1 MHz, closed loop 0.04 ΩTYP
(1) For more information, see the Application Information section of this data sheet.
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........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
At VS= ±15 V, RF= 649 Ω, RL= 50 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE
0°C to –40°C to MIN/TYP/
PARAMETER TEST CONDITIONS +25°C +25°C +70°C +85°C UNIT MAX
POWER SUPPLY
Specified operating voltage ±15 ±16 ±16 ±16 V MAX
Maximum quiescent current 7 8.5 11 11 mA MAX
Minimum quiescent current 7 5.5 4 4 mA MIN
Power-supply rejection (+PSRR) VS+ = 15.5 V to 14.5 V, VS– = 15 V 75 65 60 60 dB MIN
Power-supply rejection (–PSRR) VS+ = 15 V, VS– = –15.5 V to –14.5 V 69 60 55 55 dB MIN
POWER-DOWN CHARACTERISTICS (THS3120 Only)
VS+ – 4 MAX
REF voltage range (2) V
VS– MIN
PD ≤REF
Enable MIN
+ 0.8
Power-down voltage level(2) V
PD ≥REF
Disable MAX
+ 2
Power-down quiescent current PD ≥REF + 2 V 300 450 500 500 μA MAX
VPD = 0 V, REF = 0 V, 11
PD pin bias current μA TYP
VPD = 3.3 V, REF = 0 V 11
Turn-on time delay 90% of final value 4 μs TYP
Turn-off time delay 10% of final value 6
Input impedance 3.4 || 1.7 kΩ|| pF TYP
(2) For more information, see the Application Information section of this data sheet.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
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SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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ELECTRICAL CHARACTERISTICS
At VS= ±5 V, RF= 750 Ω, RL= 50 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE
0°C to –40°C to MIN/TYP/
PARAMETER TEST CONDITIONS +25°C +25°C +70°C +85°C UNIT MAX
AC PERFORMANCE
G = 1, RF= 909 Ω, VO= 200 mVPP 105
G = 2, RF= 750 Ω, VO= 200 mVPP 100
Small-signal bandwidth, –3 dB G = 5, RF= 499 Ω, VO= 200 mVPP 95 MHz TYP
G = 10, RF= 301 Ω, VO= 200 mVPP 70
0.1-dB bandwidth flatness G = 2, RF= 750 Ω, VO= 200 mVPP 70
Large-signal bandwidth G = 2, RF= 750 Ω, VO= 2 VPP 85
G = 1, VO= 2-V step, RF= 909 Ω560
Slew rate (25% to 75% level) V/μs TYP
G = 2, VO= 2-V step, RF= 750 Ω620
Recommended maximum SR for
Slew rate 900 V/μs MAX
repetitive signals(1)
Rise and fall time G = –5, VO= 5-V step, RF= 499 Ω10 ns TYP
Settling time to 0.1% G = –2, VO= 2 VPP step 7 ns TYP
Settling time to 0.01% G = –2, VO= 2 VPP step 42
Harmonic distortion
RL= 50 Ω51
2nd harmonic distortion G = 2, RL= 499 Ω53
RF= 649 Ω,dBc TYP
VO= 2 VPP,RL= 50 Ω48
f = 10 MHz
3rd harmonic distortion RL= 499 Ω60
Input voltage noise f > 20 kHz 2.5 nV/√Hz TYP
Noninverting input current noise f > 20 kHz 1 pA/√Hz TYP
Inverting input current noise f > 20 kHz 10 pA/√Hz TYP
NTSC 0.008%
Differential gain G = 2, PAL 0.008%
RL= 150 Ω, TYP
NTSC 0.014°
RF= 806 Ω
Differential phase PAL 0.018°
DC PERFORMANCE
Transimpedance VO= ±1.25 V, gain = 1 1.2 0.9 0.7 0.7 MΩMIN
Input offset voltage 6 10 12 13 mV MAX
VCM = 0 V
Average offset voltage drift ±10 ±10 µV/°C TYP
Noninverting input bias current 1 4 6 6 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Inverting input bias current 2 15 20 20 μA MAX
VCM = 0 V
Average bias current drift ±10 ±10 nA/°C TYP
Input offset current 2 15 20 20 μA MAX
VCM = 0 V
Average offset current drift ±30 ±30 nA/°C TYP
INPUT CHARACTERISTICS
Input common-mode voltage range ±2.7 ±2.5 ±2.3 ±2.3 V MIN
Common-mode rejection ratio VCM = ±2.5 V 66 62 58 58 dB MIN
Noninverting input resistance 35 MΩTYP
Noninverting input capacitance 0.5 pF TYP
OUTPUT CHARACTERISTICS
RL= 1 kΩ±4 ±3.8 ±3.7 ±3.7
Output voltage swing V MIN
RL= 50 Ω±3.9 ±3.7 ±3.6 ±3.6
Output current (sourcing) RL= 10 Ω310 250 200 200 mA MIN
Output current (sinking) RL= 10 Ω325 250 200 200 mA MIN
Output impedance f = 1 MHz 0.05 ΩTYP
(1) For more information, see the Application Information section of this data sheet.
6Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
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........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS (continued)
At VS= ±5 V, RF= 750 Ω, RL= 50 Ω, and G = 2, unless otherwise noted.
TYP OVER TEMPERATURE
0°C to –40°C to MIN/TYP/
PARAMETER TEST CONDITIONS +25°C +25°C +70°C +85°C UNIT MAX
POWER SUPPLY
Specified operating voltage ±5 ±4.5 ±4.5 ±4.5 V MIN
Maximum quiescent current 6.5 8 10 10 mA MAX
Minimum quiescent current 6.5 4 3.5 3.5 mA MIN
VS+ = 5.5 V to 4.5 V,
Power-supply rejection (+PSRR) 71 62 57 57 dB MIN
VS– = 5 V
VS+ = 5 V,
Power-supply rejection (–PSRR) 66 57 52 52 dB MIN
VS- = –5.5 V to –4.5 V
POWER-DOWN CHARACTERISTICS (THS3120 Only)
VS+ – 4 MAX
REF voltage range (2) V
VS– MIN
PD ≤REF
Enable MIN
+ 0.8
Power-down voltage level(2) V
PD ≥REF
Disable MAX
+ 2
Power-down quiescent current PD ≥REF + 2 V 200 450 500 500 µA MAX
VPD = 0 V, REF = 0 V, 11
PD pin bias current μA TYP
VPD = 3.3 V, REF = 0 V 11
Turn-on time delay 90% of final value 4 μs TYP
Turn-off time delay 10% of final value 6
Input impedance 3.4 || 1.7 kΩ|| pF TYP
(2) For more information, see the Application Information section of this data sheet.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
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SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
±15-V Graphs FIGURE
Noninverting small-signal gain frequency response 1, 2
Inverting small-signal gain frequency response 3
0.1-dB flatness 4
Noninverting large-signal gain frequency response 5
Inverting large-signal gain frequency response 6
Frequency response capacitive load 7
Recommended RISO vs Capacitive load 8
2nd harmonic distortion vs Frequency 9
3rd harmonic distortion vs Frequency 10
Harmonic distortion vs Output voltage swing 11, 12
Slew rate vs Output voltage step 13, 14
Noise vs Frequency 15
Settling time 16, 17
Quiescent current vs Supply voltage 18
Output voltage vs Load resistance 19
Input bias and offset current vs Case temperature 20
Input offset voltage vs Case temperature 21
Transimpedance vs Frequency 22
Rejection ratio vs Frequency 23
Noninverting small-signal transient response 24
Inverting large-signal transient response 25
Overdrive recovery time 26
Differential gain vs Number of loads 27
Differential phase vs Number of loads 28
Closed-loop output impedance vs Frequency 29
Power-down quiescent current vs Supply voltage 30
Turn-on and turn-off time delay 31
±5-V Graphs FIGURE
Noninverting small-signal gain frequency response 32
Inverting small-signal gain frequency response 33
0.1-dB flatness 34
Slew rate vs Output voltage step 35, 36
2nd harmonic distortion vs Frequency 37
3rd harmonic distortion vs Frequency 38
Harmonic distortion vs Output voltage swing 39, 40
Noninverting small-signal transient response 41
Inverting small-signal transient response 42
Input bias and offset current vs Case temperature 43
Overdrive recovery time 44
Settling time 45
Rejection ratio vs Frequency 46
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0
1
2
3
4
5
6
7
8
9
1 M 10 M 100 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
RF = 475 Ω
RF = 649 Ω
RF = 750 Ω
Gain = 2,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
−4
−2
0
2
4
6
8
10
12
14
16
18
20
22
24
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
G = 1, RF = 806 Ω
G = 10, RF = 301 Ω
G = 5, RF = 499 Ω
G = 2, RF = 649 Ω
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -1, RF = 681 Ω
G = -10, RF = 365 Ω
G = -5, RF = 499 Ω
G = -2, RF = 681 Ω
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
0
2
4
6
8
10
12
14
16
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
G = 5, RF = 499 Ω
G = 2, RF = 681 Ω
RL = 50 Ω,
VO = 2 VPP,
VS = ±15 V
5.7
5.8
5.9
6
6.1
6.2
6.3
100 k 1 M 10 M 100 M
Gain = 2,
RF = 562 Ω ,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±15 V
f - Frequency - Hz
Noninverting Gain - dB
-4
-2
0
2
4
6
8
10
12
14
16
1 M 10 M 100 M 1 G
f - Frequency - Hz
G = -5, RF = 499 Ω
G =-1, RF = 681 Ω
RL = 50 Ω,
VO = 2 VPP,
VS = ±15 V
Inverting Gain - dB
-2
0
2
4
6
8
10
12
14
16
10 M 100 M
Capacitive Load - Hz
Signal Gain - dB
Gain = 5,
RL = 50 Ω
VS = ±15 V
R(ISO) = 49.9 Ω CL = 10 pF
R(ISO) = 40.2 Ω
CL = 22 pF
R(ISO) = 30 Ω
CL = 47 pF
R(ISO) = 20 Ω
CL = 100 pF
0
10
20
30
40
50
60
10 100
CL − Capacitive Load − pF
Recommended R Ω
Gain = 5,
RL = 50 Ω,
VS = ±15 V
ISOResistance −
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
2 nd Harmonic Distortion - dBc
G = 2,
RF = 649 Ω
G = 2, RF = 649 Ω,
RL = 499 Ω
VO = 2 VPP,
RL = 50 Ω,
VS = ±15 V
G = 5,
RF = 499 Ω
-100100 k
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THS3121
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........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±15 V)
blank
NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 1. Figure 2. Figure 3.
NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL
0.1-dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 4. Figure 5. Figure 6.
RECOMMENDED RISO 2nd HARMONIC DISTORTION
FREQUENCY RESPONSE vs vs
CAPACITIVE LOAD CAPACITIVE LOAD FREQUENCY
Figure 7. Figure 8. Figure 9.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): THS3120 THS3121
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
3rd Harmonic Distortion - dBc
G = 2,
RF = 649 Ω,
RL = 499 Ω
VO = 2 VPP,
RL = 50 Ω,
VS = ±15 V
100 k
-100
G = 2,
RF = 649 Ω
G = 5,
RF = 499 Ω
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0 1 2 3 4 5 6 7 8 9 10
SR − Slew Rate − V/
VO − Output Voltage −VPP
sµ
Fall
Rise
Gain = 2
RL = 50 Ω
RF = 649 Ω
VS = ±15 V
1
10
100
0.01 0.1 1 10 100
f - Frequency - kHz
- Current Noise -
Vn
In
- Voltage Noise -
pA/ Hz
nV/ Hz
In-
In+
Vn
−1.25
−1
−0.75
−0.5
−0.25
0
0.25
0.5
0.75
1
1.25
0 2 4 6 8 10 12 14 16
t − Time − ns
− Output Voltage − VVO
Gain = −2
RL = 50 Ω
RF = 499 Ω
VS = ±15 V
Rising Edge
Falling Edge
−4.5
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 2 4 6 8 10 12 14 16
t − Time − ns
− Output Voltage − VVO
Gain = −2
RL = 50 Ω
RF = 499 Ω
VS = ±15 V
Rising Edge
Falling Edge
0
1
2
3
4
5
6
7
8
9
10
2 3 4 5 6 7 8 9 10 11 12 13 14 15
- Quiescent Current - mAIQ
VS - Supply Voltage - ±V
TA = 25 °C
TA = -40 °C
TA = 85 °C
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
blank
3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 10. Figure 11. Figure 12.
SLEW RATE SLEW RATE NOISE
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP FREQUENCY
Figure 13. Figure 14. Figure 15.
QUIESCENT CURRENT
vs
SETTLING TIME SETTLING TIME SUPPLY VOLTAGE
Figure 16. Figure 17. Figure 18.
10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
−16
−14
−12
−10
−8
−6
−4
−2
0
2
4
6
8
10
12
14
16
10 100 1000
RL − Load Resistance − Ω
− Output Voltage − VVO
VS = ±15 V
TA = −40 to 85°C
0
0.5
1
1.5
2
2.5
3
3.5
4
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
− Input Bias Current −
TC − Case Temperature − °C
VS = ±15 V
− Input Offset Current −
IIB−
IIB Aµ
IOS Aµ
IIB+
IOS
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
t - Time - µs
- Output Voltage - VVO
Output
Input
Gain = 2,
RL = 50 Ω,
RF = 649 Ω,
VS = ±15 V
0
10
20
30
40
50
60
70
80
90
100
100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Transimpedance Gain - dB ohms
VS = ±15 V
VS = ±5 V
0
10
20
30
40
50
60
70
100 k 1 M 10 M 100 M
CMRR VS = ±15 V
Rejection Ratio − dB
f − Frequency − Hz
PSRR−
PSRR+
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±15 V) (continued)
blank
INPUT BIAS AND
OUTPUT VOLTAGE OFFSET CURRENT INPUT OFFSET VOLTAGE
vs vs vs
LOAD RESISTANCE CASE TEMPERATURE CASE TEMPERATURE
Figure 19. Figure 20. Figure 21.
TRANSIMPEDANCE REJECTION RATIO
vs vs NONINVERTING SMALL-SIGNAL
FREQUENCY FREQUENCY TRANSIENT RESPONSE
Figure 22. Figure 23. Figure 24.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): THS3120 THS3121
-20
-15
-10
-5
0
5
10
15
20
0 0.2 0.4 0.6 0.8 1-4
-3
-2
-1
0
1
2
3
4
t - Time - µs
Output Voltage - V
- Input Voltage - VVI
Gain = 2,
RF = 648 Ω,
VS = ±15 V
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12
t - Time - µs
- Output Voltage - VVO
Output
Input
Gain = -5,
RL = 50 Ω,
RF = 499 Ω,
VS = ±15 V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 1 2 3 4 5 6 7 8
Number of 150 Ω Loads
Differential Phase -
PAL
NTSC
Gain = 2,
RF = 649 Ω,
VS = ±15 V,
40 IRE - NTSC and PAL,
Worst Case ±100 IRE Ramp
°
0.01
0.1
1
10
100
1 M 10 M 100 M 1 G
f − Frequency − Hz
Gain = 2,
RF = 649 Ω,
VS = ±15 V
ZO− Closed-Loop Output Impedance − Ω
0
50
100
150
200
250
300
350
400
3 5 7 9 11 13 15
TA = −40°C
VS − Supply Voltage − ±V
Powerdown Quiescent Current −
TA = 85°C
Aµ
TA = 25°C
−0.5
0
0.5
1
1.5
0 0.1 0.2 0.3 0.4 0.5 −1
0
1
2
3
4
5
6
t − Time − ms
− Output Voltage Level − VVO
Powerdown Pulse
PowerDown Pulse − V
Output Voltage
0.6 0.7
Gain = 5,
VI = 0.1 Vdc
RL = 50 Ω
VS = ±15 V and ±5 V
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±15 V) (continued)
blank
DIFFERENTIAL GAIN
INVERTING LARGE-SIGNAL vs
TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME NUMBER OF LOADS
Figure 25. Figure 26. Figure 27.
CLOSED-LOOP OUTPUT POWER-DOWN QUIESCENT
DIFFERENTIAL PHASE IMPEDANCE CURRENT
vs vs vs
NUMBER OF LOADS FREQUENCY SUPPLY VOLTAGE
Figure 28. Figure 29. Figure 30.
TURN-ON AND TURN-OFF
TIME DELAY
Figure 31.
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−4
−2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 100 M 1 G
f − Frequency − Hz
Noninverting Gain − dB
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
G = 10, RF = 301 Ω
G = 5, RF = 499 Ω
G = 2, RF = 750 Ω
G = 1, RF = 909 Ω
100 M
-4
-2
0
2
4
6
8
10
12
14
16
18
20
22
24
1 M 10 M 1 G
f - Frequency - Hz
Inverting Gain - dB
G = -1, RF = 750 Ω
G = -10, RF = 365 Ω
G = -5, RF = 499 Ω
G = -2, RF = 681 Ω
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
5.7
5.8
5.9
6
6.1
6.2
6.3
1 M 10 M 100 M
Gain = 2,
RF = 750 Ω ,
RL = 50 Ω,
VO = 0.2 VPP,
VS = ±5 V
f - Frequency - Hz
Noninverting Gain - dB
0
100
200
300
400
500
600
700
0 1 2 3 4 5 6 7
SR − Slew Rate − V/
VO − Output Voltage −VPP
sµ
Gain = 2
RL = 50 Ω
RF = 750 Ω
VS = ±5 V
Fall
Rise
0
100
200
300
400
500
600
700
0 1 2 3 4 5
SR − Slew Rate − V/
VO − Output Voltage −VPP
sµ
Gain = 1
RL = 50 Ω
RF = 909 Ω
VS = ±5 V Fall
Rise
-90
-80
-70
-60
-50
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
HD3, RL = 50Ω
HD3, RL = 50Ω
Gain = 2,
RF = 649 Ω
f= 8 MHz
VS = ±5 V
HD3, RL = 499Ω
HD2, RL = 499Ω
-100
-95
-90
-85
-80
-75
-70
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Harmonic Distortion - dBc
VO - Output Voltage Swing - VPP
HD3, RL = 50Ω
HD3, RL = 50Ω
HD2, RL = 499Ω
HD3, RL = 499Ω
Gain = 2,
RF = 649 Ω
f= 1 MHz
VS = ±5 V
-90
-80
-70
-60
-50
-40
-30
1 M 10 M 100 M
f - Frequency - Hz
3rd Harmonic Distortion - dBc
VO = 2 VPP,
RL = 100 Ω,
VS = ±5 V
G = -5, RF = 499 Ω
G = -2, RF = 649 Ω
100 k
-100
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
TYPICAL CHARACTERISTICS (±5 V)
blank
NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE FREQUENCY RESPONSE 0.1-dB FLATNESS
Figure 32. Figure 33. Figure 34.
SLEW RATE SLEW RATE 2nd HARMONIC DISTORTION
vs vs vs
OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP FREQUENCY
Figure 35. Figure 36. Figure 37.
3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION
vs vs vs
FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING
Figure 38. Figure 39. Figure 40.
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-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0 10 20 30 40 50 60 70
t - Time - ns
- Output Voltage - VVO
Gain = 2
RL = 50 Ω
RF = 750 Ω
VS = ±5 V
Input
Output
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
−40−30−20−100 10 20 30 40 50 60 70 80 90
− Input Bias Current −
TC − Case Temperature − °C
VS = ±5 V
− Input Offset Current −
IIB−
IIB Aµ
IOS Aµ
IIB+
IOS
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 10 20 30 40 50 60 70
t - Time - µs
- Output Voltage - VVO
Output
Input
Gain = -5,
RL = 50 Ω,
RF = 499 Ω,
VS = ±5 V
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 0.2 0.4 0.6 0.8 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t - Time - µs
- Input Voltage - VVI
Gain = 2,
RF = 750 Ω,
VS = ±5 V
- Output Voltage - VVO
−1.25
−1
−0.75
−0.5
−0.25
0
0.25
0.5
0.75
1
1.25
0 2 4 6 8 10 12 14 16 18 20 22 24 26
t − Time − ns
− Output Voltage − VVO
Gain = −2
RL = 50 Ω
RF = 681 Ω
VS = ±5 V
Rising Edge
Falling Edge
0
10
20
30
40
50
60
70
100 k 1 M 10 M 100 M
VS = ±5 V
Rejection Ratio − dB
f − Frequency − Hz
PSRR−
PSRR+
CMRR
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (±5 V) (continued)
blank
INPUT BIAS AND
OFFSET CURRENT
NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL vs
TRANSIENT RESPONSE TRANSIENT RESPONSE CASE TEMPERATURE
Figure 41. Figure 42. Figure 43.
REJECTION RATIO
vs
OVERDRIVE RECOVERY TIME SETTLING TIME FREQUENCY
Figure 44. Figure 45. Figure 46.
14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
_
+
THS3120
RF
649 Ω
49.9 Ω
0.1 µF 6.8 µF
-VS
-15 V
RG
50 Ω Source
+
VI
0.1 µF 6.8 µF
+
+VS
15 V
649 Ω
49.9 Ω
50 Ω LOAD
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
APPLICATION INFORMATION
MAXIMUM SLEW RATE FOR REPETITIVE Current-feedback amplifiers are highly dependent on
SIGNALS the feedback resistor RFfor maximum performance
and stability. Table 1 shows the optimal gain setting
The THS3120 and THS3121 are recommended for resistors RFand RGat different gains to give
high slew rate pulsed applications where the internal maximum bandwidth with minimal peaking in the
nodes of the amplifier have time to stabilize between frequency response. Higher bandwidths can be
pulses. It is recommended to have at least 20-ns achieved, at the expense of added peaking in the
delay between pulses. frequency response, by using even lower values for
The THS3120 and THS3121 are not recommended RF. Conversely, increasing RFdecreases the
for applications with repetitive signals (sine, square, bandwidth, but stability is improved.
sawtooth, or other) that exceed 900 V/μs. Using the
part in these applications results in excessive current Table 1. Recommended Resistor Values for
draw from the power supply and possible device Optimum Frequency Response
damage. THS3120 AND THS3121 RFAND RGVALUES FOR MINIMAL
PEAKING WITH RL= 50 Ω
For applications with high slew rate, repetitive signals, SUPPLY VOLTAGE
the THS3091 and THS3095 (single), or THS3092 and GAIN (V/V) (V) RG(Ω) RF(Ω)
THS3096 (dual) are recommended. ±15 — 806
1
WIDEBAND, NONINVERTING OPERATION ±5 — 909
±15 649 649
The THS3120 and THS3121 are unity-gain stable 2±5 750 750
130-MHz current-feedback operational amplifiers,
designed to operate from a ±5-V to ±15-V power ±15 124 499
5
supply. ±5 124 499
±15 33.2 301
Figure 47 shows the THS3121 in a noninverting gain 10
of 2-V/V configuration typically used to generate the ±5 33.2 301
Typical Characteristics. Most of the curves were ±15 681 681
–1
characterized using signal sources with 50-Ωsource ±5 750 750
impedance, and with measurement equipment –2 ±15 and ±5 340 681
presenting a 50-Ωload impedance. –5 ±15 and ±5 100 499
–10 ±15 and ±5 36.5 365
Figure 47. Wideband, Noninverting Gain
Configuration
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): THS3120 THS3121
_
+
THS3120
49.9 Ω
50 Ω Source
VI
+VS
RF
649 Ω
RG
649 Ω
+VS
2
+VS
2
_
+
THS3120
340 Ω
50 Ω Source
VI
VS
RF
681 Ω
+VS
2+VS
2
59 Ω
RG
RT
RT
49.9 Ω
49.9 Ω
50 Ω LOAD
50 Ω LOAD
_
+
THS3120
RG
340 Ω
0.1 µF 6.8 µF
-VS
-15 V
50 Ω Source
+
VI
0.1 µF 6.8 µF
+
+VS
15 V
RF
681 Ω
RM
59 Ω
49.9 Ω
50 Ω LOAD
+
-
75 Ω75 Ω
75 Ω
75 Ω
75 Ω
n Lines
VO(1)
VO(n)
75-Ω Transmission Line
VI
649 Ω649 Ω
-15 V
15 V
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
WIDEBAND, INVERTING OPERATION
Figure 48 shows the THS3121 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 47 are
retained in an inverting circuit configuration.
Figure 49. DC-Coupled, Single-Supply Operation
Figure 48. Wideband, Inverting Gain
Configuration Video Distribution
The wide bandwidth, high slew rate, and high output
SINGLE-SUPPLY OPERATION drive current of the THS3120 and THS3121 matches
The THS3120 and THS3121 have the capability to the demands for video distribution for delivering video
operate from a single supply voltage ranging from signals down multiple cables. To ensure high signal
10 V to 30 V. When operating from a single power quality with minimal degradation of performance, a
supply, biasing the input and output at mid-supply 0.1-dB gain flatness should be at least 7x the
allows for the maximum output voltage swing. The passband frequency to minimize group delay
circuits of Figure 49 show inverting and noninverting variations from the amplifier. A high slew rate
amplifiers configured for single-supply operation. minimizes distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality.
Figure 50. Video Distribution Amplifier
Application
16 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
0
10
20
30
40
50
60
10 100
CL − Capacitive Load − pF
Recommended R Ω
Gain = 5,
RL = 50 Ω,
VS = ±15 V
ISOResistance −
_
+
VS
-VS
49.9 Ω
499 Ω
5.11 Ω
1 µF
124 Ω
VS
100 Ω LOAD
RISO
_
+
VS
-VS
49.9 Ω
5.11 Ω
1 µF
124 Ω
VS
27 pF 499 Ω
RF
RG750 Ω100 Ω LOAD
RIN
_
+
VS
-VS
49.9 Ω
499 Ω
Ferrite Bead
1 µF
124 Ω
VS
100 Ω LOAD
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
Driving Capacitive Loads Placing a small series resistor, RISO, between the
amplifier output and the capacitive load, as shown in
Applications such as FET drivers and line drivers can Figure 52, is an easy way of isolating the load
be highly capacitive and cause stability problems for capacitance.
high-speed amplifiers. Using a ferrite chip in place of RISO, as shown in
Figure 51 through Figure 57 show recommended Figure 53, is another approach of isolating the output
methods for driving capacitive loads. The basic idea of the amplifier. The ferrite impedance characteristic
is to use a resistor or ferrite chip to isolate the phase versus frequency is useful to maintain the low
shift at high frequency caused by the capacitive load frequency load independence of the amplifier while
from the amplifier feedback path. See Figure 51 for isolating the phase shift caused by the capacitance at
recommended resistor values versus capacitive load. high frequency. Use a ferrite chip with similar
impedance to RISO, 20 Ωto 50 Ω, at 100 MHz and
low impedance at dc.
Figure 54 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RFat unity gain.
Replacing RIN with a ferrite chip of similar impedance
at about 100 MHz as illustrated in Figure 55 gives
similar results with reduced dc offset and low
frequency noise. (See the Additional Reference
Figure 51. Recommended RISO vs Capacitive Material section for expanding the usability of
Load current-feedback amplifiers.)
Figure 52. Resistor to Isolate Capacitive Load Figure 54. Feedback Technique with Input
Resistor for Capacitive Load
Figure 53. Ferrite Bead to Isolate Capacitive Load
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS3120 THS3121
_
+
VS
-VS
49.9 Ω
5.11 Ω
1 µF
124 Ω
VS
27 pF 499 Ω
RF
RGFB 100 Ω LOAD
FIN
_
+
VS
-VS
_
+
VS
-VS-VS
VS
301 Ω
301 Ω
66.5 Ω
5.11 Ω
5.11 Ω
_
+
VS
-VS
499 Ω
5.11 Ω
124 Ω
VS
_
+
VS
-VS
499 Ω
5.11 Ω
124 Ω
24.9 Ω
24.9 Ω
1 nF
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
Figure 57 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
Figure 55. Feedback Technique with Input Ferrite
Bead for Capacitive Load
Figure 56 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load Figure 57. PowerFET Drive Circuit
faster as when driving large FET transistors.
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3120 features a power-down pin (PD) which
lowers the quiescent current from 7 mA down to
300 μA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
REF pin voltage in the absence of an applied voltage,
putting the amplifier in the normal on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
Figure 56. Parallel Amplifiers for Higher Output rails and are given in the specification tables. Below
Drive the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
18 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
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........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
Figure 58 shows the total system output impedance POWER-DOWN REFERENCE PIN
which includes the amplifier output impedance in OPERATION
parallel with the feedback plus gain resistors, which In addition to the power-down pin, the THS3120
cumulate to 1298 Ω.Figure 47 shows this circuit features a reference pin (REF) which allows the user
configuration for reference. to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. Table 2 shows examples and illustrate the
relationship between the reference voltage and the
power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤REF + 0.8 V for enable
PD ≥REF + 2 V for disable
where the usable range at the REF pin is
VS– ≤VREF ≤(VS+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus settings the enable/disable
threshold to V(midrail) + 0.8 V and V(midrail) =2V
Figure 58. Power-down Output Impedance vs respectively.
Frequency Table 2. Power-Down Threshold Voltage Levels
As with most current-feedback amplifiers, the internal REFERENCE
architecture places some limitations on the system SUPPLY PIN ENABLE DISABLE
when in power-down mode. Most notably is the fact VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
that the amplifier actually turns ON if there is a ±0.7 V ±15, ±5 0 0.8 2
or greater difference between the two input nodes ±15 2 2.8 4
(V+ and V–) of the amplifier. If this difference ±15 –2 –1.2 0
exceeds ±0.7 V, the output of the amplifier creates an ±5 1 1.8 3
output voltage equal to approximately [(V+) – (V–) –
0.7 V] × Gain. Also, if a voltage is applied to the ±5 –1 –0.2 1
output while in power-down mode, the V– node 30 15 15.8 17
voltage is equal to VO(applied) × RG/(RF+ RG). For low 10 5 5.8 7
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the Note that if the REF pin is left unterminated, it floats
aforementioned behavior. to the positive rail and falls outside of the
recommended operating range given above (VS– ≤
The time delays associated with turning the device on VREF ≤VS+ – 4 V). As a result, it no longer serves as
and off are specified as the time it takes for the a reliable reference for the PD pin, and the
amplifier to reach either 10% or 90% of the final enable/disable thresholds given above no longer
output voltage. The time delays are in the order of apply. If the PD pin is also left unterminated, it floats
microseconds because the amplifier moves in and out to the positive rail and the device is disabled. If
of the linear mode of operation in these transitions. balanced, split supplies are used (±VS) and the REF
and PD pins are grounded, the device is enabled.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
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THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
PRINTED-CIRCUIT BOARD LAYOUT • Connections to other wideband devices on the
TECHNIQUES FOR OPTIMAL board may be made with short direct traces or
PERFORMANCE through onboard transmission lines. For short
connections, consider the trace and the input to
Achieving optimum performance with high frequency the next device as a lumped capacitive load.
amplifiers, like the THS3120 and THS3121, requires Relatively wide traces [0.05 inch (1,3 mm) to
careful attention to board layout parasitic and external 0.1 inch (2,54 mm)] should be used, preferably
component types. Recommendations that optimize with ground and power planes opened up around
performance include: them. Estimate the total capacitive load and
• Minimize parasitic capacitance to any ac ground determine if isolation resistors on the outputs are
for all of the signal I/O pins. Parasitic capacitance necessary. Low parasitic capacitive loads (less
on the output and input pins can cause instability. than 4 pF) may not need an RSbecause the
To reduce unwanted capacitance, a window THS3120 and THS3121 are nominally
around the signal I/O pins should be opened in all compensated to operate with a 2-pF parasitic
of the ground and power planes around those load. Higher parasitic capacitive loads without an
pins. Otherwise, ground and power planes should RSare allowed as the signal gain increases
be unbroken elsewhere on the board. (increasing the unloaded phase margin). If a long
• Minimize the distance [< 0.25 inch, (6,4 mm)] from trace is required, and the 6-dB signal loss intrinsic
the power-supply pins to high frequency 0.1-μFto a doubly-terminated transmission line is
and 100-pF decoupling capacitors. At the device acceptable, implement a matched impedance
pins, the ground and power-plane layout should transmission line using microstrip or stripline
not be in close proximity to the signal I/O pins. techniques (consult an ECL design handbook for
Avoid narrow power and ground traces to microstrip and stripline layout techniques). A 50-Ω
minimize inductance between the pins and the environment is not necessary onboard, and in
decoupling capacitors. The power-supply fact, a higher impedance environment improves
connections should always be decoupled with distortion as shown in the distortion versus load
these capacitors. Larger (6.8 μF or more) plots. With a characteristic board trace impedance
tantalum decoupling capacitors, effective at lower based on board material and trace dimensions, a
frequency, should also be used on the main matching series resistor into the trace from the
supply pins. These may be placed somewhat output of the THS3120/THS3121 is used as well
farther from the device and may be shared among as a terminating shunt resistor at the input of the
several devices in the same area of the PC board. destination device. Remember also that the
terminating impedance is the parallel combination
• Careful selection and placement of external of the shunt resistor and the input impedance of
components preserve the high-frequency the destination device: this total effective
performance of the THS3120 and THS3121. impedance should be set to match the trace
Resistors should be a very low reactance type. impedance. If the 6-dB attenuation of a
Surface-mount resistors work best and allow a doubly-terminated transmission line is
tighter overall layout. Again, keep the leads and unacceptable, a long trace can be
printed circuit board (PCB) trace length as short series-terminated at the source end only. Treat
as possible. Never use wirewound type resistors the trace as a capacitive load in this case. This
in a high-frequency application. Because the does not preserve signal integrity as well as a
output pin and inverting input pins are the most doubly-terminated line. If the input impedance of
sensitive to parasitic capacitance, always position the destination device is low, there is some signal
the feedback and series output resistors, if any, as attenuation due to the voltage divider formed by
close as possible to the inverting input pins and the series output into the terminating impedance.
output pins. Other network components, such as
input termination resistors, should be placed close • Socketing a high-speed part like the THS3120 and
to the gain-setting resistors. Even with a low THS3121 is not recommended. The additional
parasitic capacitance shunting the external lead length and pin-to-pin capacitance introduced
resistors, excessively high resistor values can by the socket can create an extremely
create significant time constants that can degrade troublesome parasitic network which can make it
performance. Good axial metal-film or almost impossible to achieve a smooth, stable
surface-mount resistors have approximately frequency response. Best results are obtained by
0.2 pF in shunt with the resistor. For resistor soldering the THS3120/THS3121 parts directly
values greater than 2.0 kΩ, this parasitic onto the board.
capacitance can add a pole and/or a zero that can
effect circuit operation. Keep resistor values as
low as possible, consistent with load driving
considerations.
20 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
0.205
(5,21)
0.060
(1,52)
0.013
(0,33)
0.017
(0,432)
0.025
(0,64)
0.094
(2,39)
0.040
(1,01)
0.035
(0,89)
0.075
(1,91)
0.010
vias
(0,254)
0.030
(0,76)
DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
PowerPAD DESIGN CONSIDERATIONS
The THS3120 and THS3121 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted (see
Figure 59a and Figure 59b). This arrangement results
in the lead frame being exposed as a thermal pad on
the underside of the package (see Figure 59c).
Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be
achieved by providing a good thermal path away from
the thermal pad. Note that devices such as the
THS312x have no electrical connection between the
PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing Dimensions are in inches (millimeters).
operation. During the surface-mount solder operation Figure 60. DGN PowerPAD PCB Etch and Via
(when the leads are being soldered), the thermal pad Pattern
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this 3. Additional vias may be placed anywhere along
copper area, heat can be conducted away from the the thermal plane outside of the thermal pad
package into either a ground plane or other heat area. This helps dissipate the heat generated by
dissipating device. the THS3120/THS3121 IC. These additional vias
may be larger than the 0.01-inch (0,254 mm)
The PowerPAD package represents a breakthrough diameter vias directly under the thermal pad.
in combining the small area and ease of assembly of They can be larger because they are not in the
surface mount with the, heretofore, awkward thermal pad area to be soldered so that wicking
mechanical methods of heatsinking. is not a problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS–,
is acceptable as there is no electrical connection
to the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
Figure 59. Views of Thermally-Enhanced Package connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
Although there are many ways to properly heatsink soldering operations. This makes the soldering of
the PowerPAD package, the following steps illustrate vias that have plane connections easier. In this
the recommended approach. application, however, low thermal resistance is
desired for the most efficient heat transfer.
PowerPAD LAYOUT CONSIDERATIONS Therefore, the holes under the
1. PCB with a top side etch pattern as shown in THS3120/THS3121 PowerPAD package should
Figure 60. There should be etch for the leads as make their connection to the internal ground
well as etch for the thermal pad. plane with a complete connection around the
2. Place five holes in the area of the thermal pad. entire circumference of the plated-through hole.
These holes should be 0.01 inch (0,254 mm) in 6. The top-side solder mask should leave the
diameter. Keep them small so that solder wicking terminals of the package and the thermal pad
through the holes is not a problem during reflow. area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): THS3120 THS3121
4.0
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
P MaximumPowerDissipation W-
D-
T =+125 C°
J
q=58.4
JA °C/W
q=95
JA °C/W
q=158
JA °C/W
-40 100-20 0 20 40 60 80
T Free-AirTemperature
A- - °C
PDmax +Tmax *TA
qJA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coeffiecient from the silicon junctions to
the case (°C/W).
θCA is the thermal coeffiecient from the case to ambient
air (°C/W).
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3120 and THS3121 incorporate automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately +160°C. When the junction
temperature reduces to approximately +140°C, the
amplifier turns on again. But, for maximum Results are with no air flow and PCB size = 3 inches × 3 inches
performance and reliability, the designer must take (76,2 mm × 76,2 mm); θJA = 58.4°C/W for MSOP-8 with
PowerPAD (DGN); θJA = 95°C/W for SOIC-8 High-K test PCB (D);
care to ensure that the design does not exceed a θJA = 158°C/W for MSOP-8 with PowerPAD without solder.
junction temperature of +125°C. Between +125°C
and +150°C, damage does not occur, but the Figure 61. Maximum Power Distribution vs
performance of the amplifier begins to degrade and Ambient Temperature
long term reliability suffers. The thermal
characteristics of the device are dictated by the When determining whether or not the device satisfies
package and the PC board. Maximum power the maximum power dissipation requirement, it is
dissipation for a given package can be calculated important to not only consider quiescent power
using the following formula. dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
DESIGN TOOLS
Evaluation Fixtures, Spice Models, and
Application Support
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal an evaluation board has
(1) been developed for the THS3120 and THS3121
operational amplifier. The board is easy to use,
For systems where heat dissipation is more critical, allowing for straightforward evaluation of the device.
the THS3120 and THS3121 are offered in an The evaluation board can be ordered through the
MSOP-8 with PowerPAD package offering even Texas Instruments web site, www.ti.com, or through
better thermal performance. The thermal coefficient your local Texas Instruments sales representative.
for the PowerPAD packages are substantially
improved over the traditional SOIC. Maximum power Computer simulation of circuit performance using
dissipation levels are depicted in the graph for the SPICE is often useful when analyzing the
available packages. The data for the PowerPAD performance of analog circuits and systems. This is
packages assume a board layout that follows the particularly true for video and RF-amplifier circuits
PowerPAD layout guidelines referenced above and where parasitic capacitance and inductance can have
detailed in the PowerPAD application note (literature a major effect on circuit performance. A SPICE model
number SLMA002). also illustrates the effect of not for the THS3121 is available through the Texas
soldering the PowerPAD to a PCB. The thermal Instruments web site (www.ti.com). The product
impedance increases substantially which may cause information center (PIC) is also available for design
serious heat and performance issues. Be sure to assistance and detailed product information. These
always solder the PowerPAD to the PCB for optimum models do a good job of predicting small-signal ac
performance. and transient performance under a wide variety of
operating conditions. They are not intended to model
22 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
THS3120DGN EVM
6445588
TP2GND
J2
+
C2 C4 C6
C1
+
FB1
C5 C3
FB2
VS+
VOUT
J5
VIN-
J4
VIN+
VS+
VS-
VS-
J7
VS-
R4
R8A
2
3
6
7
41
J8
R2
Z2
J7
R1
J6
R3 _
+
PD
8
R8B
R5 Z1
TP1
R6
0W
R7BR7A
REF
1
J1
VS+
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in the small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
Figure 63. THS3120 EVM Board Layout
(Top Layer)
NOTE: The Edge number for the THS3121 is
6445589.
Figure 62. THS3120 EVM Circuit Configuration
Figure 64. THS3120 EVM Board Layout
(Bottom Layer)
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): THS3120 THS3121
THS3120
THS3121
SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................
www.ti.com
Table 3. Bill of Materials
THS3120DGN and THS3121DGN EVM
REFERENCE PCB MANUFACTURER'S
ITEM DESCRIPTION SMD SIZE DESIGNATOR QUANTITY PART NUMBER (1)
1 Bead, ferrite, 3 A, 80 Ω1206 FB1, FB2 2 (Steward) HI1206N800R-00
2 Cap. 6.8 μF, tantalum, 35 V, 10% D C1, C2 2 (AVX) TAJD685K035R
3 Open 0805 R5, Z1 2
4 Cap. 0.1 μF, ceramic, X7R, 50 V 0805 C3, C4 2 (AVX) 08055C104KAT2A
5 Cap. 100 pF, ceramic, NPO, 100 V 0805 C5, C6 2 (AVX) 08051A101JAT2A
6 Resistor, 0 Ω, 1/8 W, 1% 0805 R6(2) 1 (Phycomp) 9C08052A0R00JLHFT
7 Resistor, 124 Ω, 1/8 W, 1% 0805 R3 1 (Phycomp) 9C08052A1240FKHFT
8 Resistor, 499 Ω, 1/8 W, 1% 0806 R4 1 (Phycomp) 9C08052A4990FKHFT
9 Open 1206 R7A, Z2 2
10 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R2, R8A 2 (Phycomp) 9C12063A49R9FKRFT
11 Resistor, 0 Ω, 1/4 W, 1% 1206 R1 1 (Phycomp) 9C12063A53R6FKRFT
12 Open 2512 R7B, R8B 2
Header, 0.1 inch (2,54 mm) CTRS,
13 3 pos. JP1(2) 1 (Sullins) PZC36SAAN
0.025 inch (0,635 mm) sq pins
14 Shunts JP1(2) 1 (Sullins) SSC02SYAN
Jack, banana receptance,
15 J1, J2, J3 3 (SPC) 813
0.25 inch (6,35 mm) dia. hole
16 Test point, red J7(2), J8(2), TP1 3 (Keystone) 5000
17 Test point, black TP2 1 (Keystone) 5001
18 Connector, SMA PCB jack J4, J5, J6 3 (Amphenol) 901-144-8RFX
Standoff, 4-40 hex, 0.625 inch
19 4 (Keystone) 1808
(15,88 mm) length
Screw, Phillips, 4-40,
20 4 SHR-0440-016-SN
0.250 inch (6,35 mm)
21 IC, THS3120 U1(2) 1 (TI) THS3120DGN
22 Board, printed-circuit (THS3120) (2) 1 (TI) EDGE # 6445588
23 IC, THS3121 U1 1 (TI) THS3121DGN
24 Board, printed-circuit (THS3121) 1 (TI) EDGE # 6445589
(1) The manufacturer's part numbers were used for test purposes only.
(2) Applies to the THS3120DGN EVM only.
ADDITIONAL REFERENCE MATERIAL
• PowerPAD Made Easy, application brief (SLMA004)
• PowerPAD Thermally-Enhanced Package, technical brief (SLMA002)
• Voltage Feedback versus Current-Feedback Amplifiers, (SLVA051)
• Current Feedback Analysis and Compensation (SLOA021)
• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
• Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
24 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated
Product Folder Link(s): THS3120 THS3121
THS3120
THS3121
www.ti.com
........................................................................................................................................ SLOS420E –SEPTEMBER 2003–REVISED OCTOBER 2009
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (January 2009) to Revision E ............................................................................................... Page
• Changed Power-Down Characteristics, Power-down quiescent current test conditions of ±15 V Electrical
Characteristics ...................................................................................................................................................................... 5
• Changed Power-Down Characteristics, PD pin bias current parameter of ±15 V Electrical Characteristics ....................... 5
• Changed Power-Down Characteristics, Power-down quiescent current test conditions of ±5 V Electrical
Characteristics ...................................................................................................................................................................... 7
• Changed Power-Down Characteristics, PD pin bias current parameter of ±5 V Electrical Characteristics ......................... 7
• Updated format of Application Information section ............................................................................................................. 15
• Added caption title to Figure 52 .......................................................................................................................................... 17
• Added caption title to Figure 53 .......................................................................................................................................... 17
• Added caption title to Figure 54 .......................................................................................................................................... 17
• Added caption title to Figure 55 .......................................................................................................................................... 18
• Added caption title to Figure 56 .......................................................................................................................................... 18
• Changed first sentence of second paragraph of the Saving Power with Power-Down Functionality section .................... 18
• Changed last sentence of Power-Down Reference Pin Operation section ........................................................................ 19
Changes from Revision C (February 2007) to Revision D ............................................................................................. Page
• Changed input offset voltage values ..................................................................................................................................... 4
• Changed input common-mode voltage range values ........................................................................................................... 4
• Changed power-supply rejection ratio values ....................................................................................................................... 5
• Changed input offset voltage values ..................................................................................................................................... 6
• Changed input common-mode voltage range values ........................................................................................................... 6
• Changed power-supply rejection ratio values ....................................................................................................................... 7
Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): THS3120 THS3121
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS3120CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA
THS3120CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA
THS3120CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AQA
THS3120ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3120I
THS3120IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APN
THS3121CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3121C
THS3121ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 3121I
THS3121IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU |
CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APO
THS3121IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 APO
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS3120CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS3120CDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
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