MOTOROLA CMOS LOGIC DATA 393
MC14516B
The MC14516B synchronous up/down binary counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure.
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the
reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Internally Synchronous for High Speed
•Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock
•Single Pin Reset
•Asynchronous Preset Enable Operation
•Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
TRUTH TABLE
Carry In Up/Down Preset
Enable Reset Clock Action
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low . When counting down,
Carry Out is low only when Q0 through Q3 and Carry In are low.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
v
(Vin or Vout)
v
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD = PIN 16
VSS = PIN 8
6
11
14
2
7
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
RESET
UP/DOWN
CLOCK
P0
P1
P2
P3
1
5
9
10
15
4
12
13
3
MOTOROLA CMOS LOGIC DATAMC14516B
394
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.58 µA/kHz) f + IDD
IT = (1.20 µA/kHz) f + IDD
IT = (1.70 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**
ā
The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
P1
P2
Q2
C
VDD
R
U/D
Q1
P0
P3
Q3
PE
VSS
CARRY OUT
Q0
CARRY IN
MOTOROLA CMOS LOGIC DATA 395
MC14516B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic
Symbol
VDD
All Types
Unit
Characteristic
Symbol
VDD
Min Typ # Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
315
130
100
630
260
200
ns
Clock to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
315
130
100
630
260
200
ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
180
80
60
360
160
120
ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
315
130
100
630
360
200
ns
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
550
225
150
1100
450
300
ns
Reset Pulse Width tw5.0
10
15
380
200
160
190
100
80
—
—
—
ns
Clock Pulse Width tWH 5.0
10
15
350
170
140
200
100
75
—
—
—
ns
Clock Pulse Frequency fcl 5.0
10
15
—
—
—
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time
The Preset or Reset signal must be low prior to a
positive–going transition of the clock.
trem 5.0
10
15
650
230
180
325
115
90
—
—
ns
Clock Rise and Fall Time tTLH,
tTHL 5.0
10
15
—
—
—
—
—
—
15
5
4
µs
Setup Time
Carry In to Clock tsu 5.0
10
15
260
120
100
130
60
50
—
—
—
ns
Hold Time
Clock to Carry In th5.0
10
15
0
20
20
– 60
– 20
0
—
—
—
ns
Setup Time
Up/Down to Clock tsu 5.0
10
15
500
200
150
250
100
75
—
—
—
ns
Hold Time
Clock to Up/Down th5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
—
—
—
ns
Setup Time
Pn to PE tsu 5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
—
—
—
ns
Hold Time
PE to Pn th5.0
10
15
480
420
420
240
210
210
—
—
—
ns
Preset Enable Pulse Width tWH 5.0
10
15
200
100
80
100
50
40
—
—
—
ns
*The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATAMC14516B
396
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR CL
CL
CL
CL
VDD
VARIABLE
WIDTH
VDD
VSS
CLOCK
ID0.01
µ
F
CERAMIC
20 ns
20 ns
10%
50% 90%
500 pF
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
R
UP/DOWN
CLOCK
P0
P1
P2
P3
CL
LOGIC DIAGRAM
PE
C
T
Q
Q
PPE
C
T
Q
Q
PPE
C
T
Q
Q
PPE
C
T
Q
Q
P
Q2
14
P2
13
Q1
11 P3
3Q3
2
P0
4Q0
6P1
12
CARRY OUT
CLOCK
PRESET
ENABLE
RESET
CARRY IN
UP/DOWN
9
1
15
7
5
10
TOGGLE FLIP–FLOP
PE
C
T
Q
Q
P
PARALLEL IN
FLIP–FLOP FUNCTIONAL TRUTH TABLE
Preset
Enable Clock T Qn+1
1 X X Parallel In
0 0 Qn
0 1 Qn
0 X Qn
X = Don’t Care
MOTOROLA CMOS LOGIC DATA 397
MC14516B
Figure 2. Switching Time Waveforms
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VOL
VOH
RESET
PRESET ENABLE
CARRY IN OR
UP/DOWN
CLOCK
Q0 OR CARRY OUT
trem
tsu trem
th
tTLH
tPLH
tPHL
tPLH
tTHL
50%
50%
90%
10%
50%
90%
10%
CARRY OUT ONLY
tw(H) tw(H)
tw
1
fcl
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active–low input is used when
Cascading stages. Carry In is usually connected to Carry
Out of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or decrem-
ented, depending on the direction of count, on the positive
transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0 correspond-
ing to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out–
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count, high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0 volts
to 18.0 volts.
MOTOROLA CMOS LOGIC DATAMC14516B
398
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
L.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin M.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
TERMINAL COUNT
INDICATOR
P0 P1 P2 P3 P4 P5 P6 P7
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
+VDD
+VDD
+VDD OPEN = COUNT
CLOCK
RESET
RESISTORS = 10 k
W
0 = COUNT
1 = PRESET
1 = UP
0 = DOWN
PRESET
ENABLE
MOTOROLA CMOS LOGIC DATA 399
MC14516B
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTER
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P7
P6
P5
P4
P3
P2
P1
P0
CARRY OUT
(MSD)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CARRY OUT
(LSD)
RESET
COUNT
PRESET ENABLE
UP COUNT DOWN COUNT UP COUNT DOWN
COUNT
PRESET
ENABLE RESET
13 14 15 16 17 18 18 17 16 15 14 13
19 251 252 253 254 255 0 1 2 2 13 0 1 2
UP COUNT
MOTOROLA CMOS LOGIC DATAMC14516B
400
Figure 4. Programmable Cascaded Frequency Divider
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary , to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1 111 1 111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
BUFFER
fout
M.S.D.
MC14516B
L.S.D.
MC14516B
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
+VDD
+VDD
Cout
+VDD OPEN = COUNT
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3
P0 P1 P2 P3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
P4 P5 P6 P7
CLOCK (fin)
RESET
RESISTORS = 10 k
W
fout = fin
n
MOTOROLA CMOS LOGIC DATA 401
MC14516B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
FE
G
NK
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.750 0.785 19.05 19.93
B0.240 0.295 6.10 7.49
C––– 0.200 ––– 5.08
D0.015 0.020 0.39 0.50
E0.050 BSC 1.27 BSC
F0.055 0.065 1.40 1.65
G0.100 BSC 2.54 BSC
H0.008 0.015 0.21 0.38
K0.125 0.170 3.18 4.31
L0.300 BSC 7.62 BSC
M0 15 0 15
N0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
MOTOROLA CMOS LOGIC DATAMC14516B
402
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided
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MC14516B/D
*MC14516B/D*
◊
