ANALOG Fast, Complete 12-Bit A/D Converter DEVICES with Microprocessor Interface ADS74A REV. C 1.1 Scope. This specification covers the detail requirements for a 12-bit resolution A/D converter with complete microprocessor interface and a high performance buried Zener reference. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -1 AD574AS(X)/883B -2 ADS74AT(XV833B -3 AD574AU(X)/883B NOTE 'See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description D D-28 28-Pin DIP E E-28A 28-Pin LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vcc to Digital Common... 2 1. ee es +16.5V Ver to Digital Common... 1... ee ee -16.5V Viocic to Digital Common .. 2... 1 1 es +7V Analog Common to Digital Common .. 1... 2... 2 ee ee es +1V Control Inputs (CE, CS, Ag, 12/8, R/C) to Digital Common ......... ~0.5V to Viogic +0.5V Analog Inputs (REF IN, BIP OFF, 10V;,) to Analog Common ............000- +16.5V 20Vin to Analog Common... . 1. ee es +24V REF OUT .. 12... ee ee ee ee Indefinite Short to Common Momentary Short to Vcc Power Dissipation ... ee ee ee 1000mW Storage Temperature Range... 2... ee ee ee 65C to + 150C Lead Temperature (Soldering 10sec) . 2... ee ee + 300C 1.5 Thermal Characteristics. Thermal Resistance 8j = 25C/W for D-28 or E-28A 83, = 60C/AW for D-28 or E-28A ANALOG-TO-DIGITAL CONVERTERS 6-19 ANALOG-TO-DIGITAL CONVERTERS ADS74ASPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device @+25C | 1 2,3 4 Test Condition Units Power Dissipation Pp 1,2,3 | 725 725 Tristated Outputs mW max Input Resistance Rm ~1,2,3 | 3 3 10V Span kN min 7 kf max 6 20V Span kN min 14 14 kN max Internal 10V Reference VREF -1,2 +20 +20 Bipolar mV Output Voltage Error 3 +10 +20 +10 1.5mA External Load Logic Input High? Vin -1,2,3 | 2.0 2.0 +Vmin CE, CS, RIC, Ao 5.5 + Vmax Logic Input Low Vit -1,2,3 | 0.5 Vmin CE, CS, R/C, Ag 0.8 0.8 + Vmax Logic Input Current Tun 1,2,3 20 20 20 Vin=5.0V + pA max CE,CS, RIC, Ao Vu. =0.0V Logic Output High DB11-DB0 Vou |-1,2,3 | 2.4 2.4 2.4 Isource = 500nA +Vmin Logic Output Low DB11-DB0, STS Voi ~1,2,3 0.4 0.4 0.4 Ising = 1.6mA + V max Three-State Output Leakage Outputs Tristated DB11-DBO lor |-1,2,3 | 20 20 20 Vi =5.0V + pA max Power Supply Current IL 1,2,3 | 40 40 Outputs Tristated mA max lec 1,2,3 | 5 5 Tee -1,2,3 30 30 Full-Scale Calibration Drift TCAg |-1 20 + LSB max -2 10 -3 5 Linearity LE -1 1 1 1 10V Unipolar, 20V Bipolar | + LSB max -2,3 1/2 1 I 1/2 Major Transitions Differential Nonlinearity? DNL |-1 11 11 1] All Codes Tested Bits min -2,3 12 1] 12 12 Power Supply Rejection Ratio*} PSRR | -1 2 2 See Note 5 + LSB max -2,3 I 2 1 PSRR |-1,2,3 | 1/2 v2 See Note 6 PSRR |{-1 2 2 See Note? 2,3 1 2 1 Unipolar Offset Error VosE ~1 2 2 4 + LSB max ~2,3 1 2 2 1 Unipolar Offset Drift TCyos | -1 2 + LSB max -2,3 1 Bipolar Offset Error Bpog -1 4 4 8 Bipolar + LSB max -2 4 4 6 20V Span -3 2 4 3 2 . Bipolar Offset Drift TCBpog] 1 4 Bipolar + LSB max 2 2 20V Span -3 1 Full-Scale Error Ag -1,2 0.25 0.25 Bipolar + %/FSR max =3 0.125 0.25 0.125 | 20V Span Av -1,2 0.25 Unipolar + %/FSR max -3 0.125 10V Span 6-20 ANALOG-TO-DIGITAL CONVERTERS REV. CADS74A Design Sub Sub Sub Limit Group | Group | Group Test Symbol | Device @+25C | 1 2,3 9 Test Condition! Units Full-Control Mode! STS Delay from CE tpsc -1,2,3 400 350 Timing Per Figure 1 ns max CE Pulse Width tHec -1,2,3 300 300 Timing Per Figure 1 ns min Access Timing (from CE) | tpp -1,2,3 | 200 200 Timing Per Figure 2 ns max Output Float Delay tur -1,2,3 100 100 Timing Per Figure 2 ns max Data Valid After CE Low lup -1,2,3 25 25 Timing Per Figure 2 ns min Stand-Alone Mode! ; Low R/C Pulse Width ture -1,2,3 250 250 Timing Per Figure 3 ns min STS Delay from R/C tps -1,2,3 | 600 600 Timing Per Figure 3 ns max Data Access Time tppr -1,2,3 250 250 Timing Per Figure 3 ns max Data Valid After R/CLow THDR -1,2,3 25 25 Timing Per Figure 3 ns min Conversion Time te -1,2,3 35 35 To 12 Bits pes max 24 24 To8 Bit NOTES Veg = +15V, Vez = 1SV3 Viggic = +5V; 12/8 connected to Viocic: Ao and CS at logic 0, CE at logic 1. 10V unipolar configuration unless otherwise noted. 10V Unipolar: 500 resistor Pin 8 to Pin 10, $02 resistor Pin 12 to ground, analog input to Pin 13. 20V Bipolar: 500 resistor Pin 8 to Pin 12, 502 resistor Pin 8 to Pin 10, analog input to Pin 14. See Figures 1, 2, and 3 for timing information. Vin = 2.0V min and Vy, =0.8V max, guaranteed design limits 55C to + 125C. 3Minimum resolution for which no missing codes are guaranteed. Change in unipolar 10V span with full-scale (Code 4095) transition voltage. >Test Conditions for PSRR: 13.5V = Voc = 16.5V; Viocic = 5V; Vez = 15V 11.4V < Voc 12.6V, Viocic = 5V; Vez = 12V 4.5V = Viocic = 5-5V> Voc = 15V, Vez = ~15V 7_16.5< Veg = -13.5V, Viocic = $V, Voc = ISV ~12.6V = Veg = 11.4V, Viogic = 5V3 Vcc = 12V 8See Figure 4. 3.2.1 Functional Block Diagram and Terminal Assignments. D Package (DIP) +5V SUPPLY. Voge DATA MODE SELECT STATUS STs ORT MSE. cHIP Sevect CONTROL DB10 BYTE ADDRESS SHORT CYCLE ope Ao READ/CONVERT ae CHIP ENABLE +12/416V SUPPLY pee DIGITAL Vee DATA +10V REFERENCE REF OUT obs OUTPUTS ANALOG commen Dea ANALOG COMMON AC 9 REFERENCE INPUT REF IN oe -12/-15 SUPPLY Vee GIPOLAR OFFSET 1 OFF Det 10V SPAN INPUT 10w 20V SPAN INPUT 20Vie OBO LSB DIGITAL COMMON oc REV. C READICONVERT RE 5 CHIP ENABLE CE 6 HIZVI+IBY Veo 7 +10 REFERENCE REF OUT & REFERENCE INPUT AEF IN:10 ~12W/-18V Vee 31 E Package (LCC) ANALOG-TO-DIGITAL CONVERTERS 6-21 = BYTE ADDRESS/SHORT CYCLE Ao w CHP SELECT TS DATA MODE SELECT 12/8 @ STATUS STS [R= +5V SUPPLY Vicce & oer 26 ofS 24 085 23 087 ADS74A 22 pes TOP VIEW (Not to Scale) 21 Des 20 ope 19 oBa 1213-14-16 96:17: BIPOLAR OFFSET BP OFF 10V SPAN INPUT 10Vm, ANALOG-TO-DIGITAL CONVERTERS aAD574A 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (57). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). +15V REF our Ac REF yy 15V Vee BIP OFF 10Vw 20Viy %~v S0Hz = 10V PEAK ALL RESISTORS 3k0), 1/4 WATT. ce Symbol! | Parameter Min Typ Max! Units tosc STS Delay from CE 400 | ns cS tyec CE Pulse Width 300 ns tssc CS toCE Setup 50 ns Re thse CS Low During CEHigh | 200 ns tsrc R/C toCE Setup 50 ns tec R/C Low During CE High | 200 ns Ao tsac AotoCE Setup 0 ns tHac Ao Valid During CE High | 300 ns sts te Conversion Time 8-Bir Cycle 10 24 ws 12-Bit Cycle 15 35 ps 0811-DBO HIGH IMPEDANCE Figure 1. Convert Start Timing 6-22 ANALOG-TO-DIGITAL CONVERTERS REV. ADS74A ce Symbol | Parameter Min Typ Max | Units top! Access Time (fromCE) 200 | ns cs tip Data Valid after CE Low 25 ns tun Output Float Delay 100 | ns _ tssR CS toCE Setup 150 as Ric tsrr R/C toCE Setup 0 ns Tsar AotoCE Setup 150 ns Ao usr CS Valid After CE Low 50 ns UHRR R/CHigh After CE Low 0 ns sts tHAR Ao Valid After CE Low 50 ns top is measured with the load circuit of Figure 4 and defined as the time required pe11-D80 HIGH foranoutput tocross 0.4V to 2.4V. IMPEDANCE . tut is defined as the time required for the data lines tochange 0.5V when loaded with the circuit of Figure 5. Figure 2. Read Timing tos eo Symbol | Parameter Min Typ Max | Units tur. | Low R/C Pulse Width 250 as bitoa * | | tos STS Delay from R/C 600 | ns RIE sts VP =| DATA HIGH-Z tupr Data Valid After R/C Low 25 ns cevom thg |}? fovravatin tus STS Delay After Data Valid | 300 1000 | os | CHR High R/C Pulse Width 300 ns tppr Data Access Time 250 | ns toon tc _w-] PENRO wicHz 7 DATA wigHz VALID Figure 3. Stand-Alone Mode Timing +5V 3k DBy DEN 3k Fo T 100pF a. High-Z to Logic 1 b. High-Z to Logic 0 Figure 4. Load Circuit for Access Timing Test +5V OBn DBn 3k Tt 10pF a. Logic 1 to High-Z b. Logie 0 to High-Z KS Figure 5. Load Circuit for Output Float Delay Test REV. C ANALOG-TO-DIGITAL CONVERTERS 6-23 ANALOG-TO-DIGITAL CONVERTERS a