K6T4008C1B-GB70 - Samsung Electronics

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

Document Title

512Kx8 bit Low Power CMOS Static RAM

Revision History

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.0

0.1

1.0

2.0

3.0

Remark

Advance

Preliminary

Final

History

Initial Draft

Revise

- Changed Operating current by reticle revision

ICC at write : 35mA → 45mA

ICC1 at read/write : 15/35mA → 10/45mA

Finalize

- Changed Operating current

ICC1 at write : 45mA → 40mA

ICC2; 90mA → 80mA

- Change test load at 55ns : 100pF → 50pF

Revise

- Change datasheet format

Revise

- Industrial product speed bin change:70/100ns → 55/70ns

Draft Date

December 7, 1996

March 6, 1997

October 9, 1997

February 17, 1998

September 8, 1998

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

512Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6T4008C1B families are fabricated by SAMSUNG′s

advanced CMOS process technology. The families support

various operating temperature ranges and various package

types for user flexibility of system design. The family also

support low data retention voltage for battery back-up oper-

ation with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 512Kx8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-DIP-600, 32-SOP-525

32-TSOP2-400F/R

PIN DESCRIPTION

Pin Name Function

WE Write Enable Input

CS Chip Select Input

OE Output Enable Input

A0~A18 Address Inputs

I/O1~I/O8Data Inputs/Outputs

Vcc Power

Vss Ground

PRODUCT FAMILY

1. The parameter is measured with 50pF test load.

Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

K6T4008C1B-L Commercial (0~70°C)

4.5~5.5V 551)/70ns

100µA

20µA80mA

32-DIP-600, 32-SOP-525

32-TSOP2-400F/R

K6T4008C1B-B

K6T4008C1B-P Inderstrial (-40~85°C)100µA

50µA32-SOP-525

32-TSOP2-400F/R

K6T4008C1B-F

FUNCTIONAL BLOCK DIAGRAM

32-DIP

32-SOP

(Forward)

32-TSOP2

A16

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A15

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

32-TSOP2

A16

A14

A12

I/O1

I/O2

I/O3

VSS

VCC

A15

A13

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

(Reverse)

A18

A17 A17

A18

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

1024 rows

512×8 columns

I/O Circuit

Column select

Clk gen.

Row

select

A9 A8 A13A17A15 A11A10

A18

A16

A14

A12

I/O1Data

cont

Data

cont

I/O8

Control

logic

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

K6T4008C1B-DL55

K6T4008C1B-DB55

K6T4008C1B-DL70

K6T4008C1B-DB70

K6T4008C1B-GL55

K6T4008C1B-GB55

K6T4008C1B-GL70

K6T4008C1B-GB70

K6T4008C1B-VB55

K6T4008C1B-VB70

K6T4008C1B-MB55

K6T4008C1B-MB70

32-DIP, 55ns, L-pwr

32-DIP, 55ns, LL-pwr

32-DIP, 70ns, L-pwr

32-DIP, 70ns, LL-pwr

32-SOP, 55ns, L-pwr

32-SOP, 55ns, LL-pwr

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

32-TSOP2-F, 55ns, LL-pwr

32-TSOP2-F, 70ns, LL-pwr

32-TSOP2-R, 55ns, LL-pwr

32-TSOP2-R, 70ns, LL-pwr

K6T4008C1B-GP55

K6T4008C1B-GF55

K6T4008C1B-GP70

K6T4008C1B-GF70

K6T4008C1B-VF55

K6T4008C1B-VF70

K6T4008C1B-MF55

K6T4008C1B-MF70

32-SOP, 55ns, L-pwr

32-SOP, 55ns, LL-pwr

32-SOP, 70ns, L-pwr

32-SOP, 70ns, LL-pwr

32-TSOP2-F, 55ns, LL-pwr

32-TSOP2-F, 70ns, LL-pwr

32-TSOP2-R, 55ns, LL-pwr

32-TSOP2-R, 70ns, LL-pwr

FUNCTIONAL DESCRIPTION

1. X means don′t care.( Must be in low or high state.)

CS OE WE I/O Pin Mode Power

HX1) X1) High-Z Deselected Standby

LH H High-Z Output disbaled Active

L L HDout Read Active

LX1) LDin Write Active

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V-

Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -65 to 150 °C-

Operating Temperature TA0 to 70 °CK6T4008C1B-L/-B

-40 to 85 °CK6T4008C1B-P/-F

Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. Commercial Product: TA=0 to 70°C, otherwise specified

Industrial Product: TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns

3. Undershoot: -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V

Ground Vss 0 0 0 V

Input high voltage VIH 2.2 -Vcc+0.52) V

Input low voltage VIL -0.53) -0.8 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA

Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read -7.5 15 mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA

CS≤0.2V, VIN≥0.2V or VIN ≥ Vcc-0.2V Read -410 mA

Write -27 40

ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL -65 80 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.4 - - V

Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 3mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc

K6T4008C1B-L -2100 µA

K6T4008C1B-B -120 µA

K6T4008C1B-P -2100 µA

K6T4008C1B-F -150 µA

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)

Parameter List Symbol

Speed Bins

Units

55*ns 70ns

Min Max Min Max

Read

Read cycle time tRC 55 -70 -ns

Address access time tAA -55 -70 ns

Chip select to output tCO -55 -70 ns

Output enable to valid output tOE -25 -35 ns

Chip select to low-Z output tLZ 10 -10 -ns

Output enable to low-Z output tOLZ 5-5-ns

Chip disable to high-Z output tHZ 020 025 ns

Output disable to high-Z output tOHZ 020 025 ns

Output hold from address change tOH 10 -10 -ns

Write

Write cycle time tWC 55 -70 -ns

Chip select to end of write tCW 45 -60 -ns

Address set-up time tAS 0-0-ns

Address valid to end of write tAW 45 -60 -ns

Write pulse width tWP 40 -50 -ns

Write recovery time tWR 0-0-ns

Write to output high-Z tWHZ 020 025 ns

Data to write time overlap tDW 25 -30 -ns

Data hold from write time tDH 0-0-ns

End write to output low-Z tOW 5-5-ns

CL1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See right): CL=100pF+1TTL

CL=50pF+1TTL

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -5.5 V

Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V

K6T4008C1B-L - - 50

µA

K6T4008C1B-B - - 15

K6T4008C1B-P - - 50

K6T4008C1B-F - - 20

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

Address

Data Out Previous Data Valid Data Valid

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

Address

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

tOH

tAA

tOLZ

tLZ tOHZ

tHZ

tRC

tOE

tCO1

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

tWC

tWR(4)

tAS(3)

tDW tDH

Data Valid

Data in

Data out High-Z High-Z

tCW(2)

tWP(1)

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR tRDR

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

tCW(2) tWR(4)

tWP(1)

tDW tDH

tOW

tWHZ

Data Undefined

Data Valid

Data in

Data out

tWC

tAW

tAS(3)

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

PACKAGE DIMENSIONS Units: millimeter(Inch)

0~15°

1.91

32 PIN DUAL INLINE PACKAGE (600mil)

#32

13.60±0.20

0.535±0.008

41.91±0.20

1.650±0.008

( )

0.075

15.24

0.600

+0.10

MAX

42.31

1.666

0.25 -0.05

+0.004

0.010

-0.002

2.54

0.100

MAX

3.81±0.20

0.150±0.008

5.08

0.200

MIN

0.015

0.38 0.130±0.012

3.30±0.30

#16

#17

1.52±0.10

0.060±0.004

0.46±0.10

0.018±0.004

32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8°

#32

20.47±0.20

0.806±0.008

MAX

20.87

0.822 MAX

2.74±0.20

0.108±0.008

3.00

0.118

MIN

0.002

0.05

0.004 MAX

0.10 MAX

0.71

( )

0.028

13.34

0.525

11.43±0.20

0.450±0.008

0.80±0.20

0.031±0.008

+0.10

0.20 -0.05

+0.004

0.008

-0.002

14.12±0.30

0.556±0.012

#17

#16

1.27

0.050

+0.100

0.41 -0.050

+0.004

0.016 -0.002

K6T4008C1B Family CMOS SRAM

Revision 3.0

September 1998

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0~8°

#32

20.95±0.10

0.825±0.004

MAX

21.35

0.841

MAX

1.00±0.10

0.039±0.004

1.20

0.047

MIN

0.002

0.05

0.004 MAX

0.10 MAX

0.95

( )

0.037

10.16

0.400

+0.10

0.15 -0.05

+0.004

0.006 -0.002

11.76±0.20

0.463±0.008

#17

#16 0.50

( )

0.020

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

1.27

0.050

0.40±0.10

0.016±0.004

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8°

#32

10.16

0.400

+0.10

0.15 -0.05

+0.004

0.006 -0.002

11.76±0.20

0.463±0.008

#17

#16

0.50

( )

0.020

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

20.95±0.10

0.825±0.004

MAX

21.35

0.841

MAX

1.00 ±0.10

0.039±0.004

1.20

0.047

MIN

0.002

0.05

0.004 MAX

0.10 MAX

0.95

( )

0.037 1.27

0.050

0.40±0.10

0.016±0.004

Units: millimeter(Inch)