CD40192BCN - Fairchild - Datasheet.Live

October 1987

Revised March 2002

CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary

Counter

CD40192BC • CD40193BC

Synchronous 4-Bit Up/Down Decade Counter •

Synchronous 4-Bit Up/Down Binary Counter

General Description

The CD40192BC and CD40193BC up/down counters are

monolithic complementary MOS (CMOS) integrated cir-

cuits. The CD40192BC is a BCD counter, while the

CD40193 BC is a bina ry coun ter.

Counting up and co unting do wn is pe rform ed by two count

inputs, one being held HIGH while the other is clocked. The

outputs change on the positive-going transition of this

clock.

These counters feature preset inputs that are enabled

when load is a logical “0” and a clea r which forces all ou t-

puts to “0” wh en it i s at log ical “ 1”. Th e coun ters also ha ve

carry and borrow outputs so that they can be cascaded

using no external circuitry.

All inputs are protected against damage due to static dis-

charge by clamps to VDD and VSS.

Features

■Wide supply voltage range: 3V to 15V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility: Fan out of 2 driving 74L

or 1 driving 74LS

■Carry and borrow ou tpu ts for easy expansi o n to N- bit b y

cascading

■Asynchronous clear

■Equivalent to: MM74C192 and MM74C193

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the order ing code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Cascading Packages

Order Number Package Number Package Description

CD40192BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD40193BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD40193BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD40192BC • CD40193BC

Block Diagrams

CD40192BC Synchronous 4-Bit Up/Down Decade Counter

CD40193BC Synchronous 4-Bit Up/Down Binary Counter

3 www.fairchildsemi.com

CD40192BC • CD40193BC

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions (Note 2)

Note 1: “Absolute Maximum Ratings” are those va lues beyond which the

safety of the device cannot be guaranteed. They are not meant to imply

that the devices should be operated at these limits. The “Recommended

Operating Conditions” and Electrical Characteristics tables provide condi-

tio ns f or actu al device operation.

Note 2: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 3)

Note 3: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Note 4: IOH and IOL are test ed one output at a ti m e.

DC Supply Vo ltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5toV

DD +0.5 VDC

Storage Temperature Range (TS) −65°C to +150°C

Power Di ssipa ti on (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (T L)

(Soldering, 10 seconds) 260 °C

DC Supply Voltage (V DD) 3 to 15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)

CD401 92B C, C D40 193BC −55°C to +125°C

Symbol Parameter Conditions −55°C +25°C+125°CUnits

MinMax MinTypMaxMinMax

IDD Quiescent Device VDD = 5V, VIN = VDDor VSS 55150

µACurrent VDD = 10V, VIN = VDD or VSS 10 10 300

VDD = 15V, VIN = VDD or V SS 20 20 600

VOL LOW Level VDD = 5V 0.05 0.05 0.05 VOutput Voltage VDD = 10V 0.05 0.05 0.05

VDD = 15V 0.05 0.05 0.05

VOH HIGH Level VDD = 5V 4.95 4.95 4.95 VOutput Voltage VDD = 10V 9.95 9.95 9.95

VDD = 15V 14.95 14.95 14.95

VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 VInput Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0

VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VInput Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0

VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0

IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9

VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4

IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 µA

VDD = 15V, V IN = 15V 0.1 10−5 0.1 1.0

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CD40192BC • CD40193BC

AC Electrical Characteristics (Note 3)

TA = 25°C, CL = 50 pF, RL = 200 kΩ, input tr = tf = 20 ns, unless otherwise specified.

Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note,

AN-90.

Symbol Parameter Conditions Min Typ Max Units

tPHL or tPLH Propagation Delay Time VDD = 5V 250 400 nsfrom Count Up or VDD = 10V 100 160

Count Down to Q VDD = 15V 80 130

tPHL or tPLH Propagation Delay Time VDD = 5V 120 200 nsfrom Count Up to Carry VDD = 10V 50 80

VDD = 15V 40 65

tPHL or tPLH Propagation Delay Time VDD = 5V 120 200 nsfrom Count Down VDD = 10V 50 80

to Borrow VDD = 15V 40 65

tSU Time Prior to Load VDD = 5V 100 160 nsThat Data Must VDD = 10V 30 50

Be Present VDD = 15V 25 40

tPHL Propagation Delay Time VDD = 5V 130 220 nsfrom Clear to Q VDD = 10V 60 100

VDD = 15V 50 80

tPLH or tPHL Propagation Delay Time VDD = 5V 300 480 nsfrom Load to Q VDD = 10V 120 190

VDD = 15V 95 150

tTLH or tTHL Output Transition Time VDD = 5V 100 200 ns VDD = 10V 50 100

VDD = 15V 40 80

fCL Maximum Count Frequency VDD = 5V 2.5 4 MHzVDD = 10V 6 10

VDD = 15V 7.5 12.5

trCL or t fCL Maximum Count Rise VDD = 5V 15 µsor Fall Time VDD = 10V 5

VDD = 15V 1

tWH, tWL Minimum Count Pulse VDD = 5V 120 200 nsWidth VDD = 10V 35 80

VDD = 15V 28 65

tWH Minimum Clear VDD = 5V 300 480 nsPulse Width VDD = 10V 120 190

VDD = 15V 95 150

tWL Minimum Load VDD = 5V 100 160 nsPulse Width VDD = 10V 40 65

VDD = 15V 32 55

CIN Average Input Capacitance Load and Data 5 7.5

Inputs (A,B,C,D)

Count Up, Count 10 15

Down and Clear

CPD Power Dissipation Capacity (Note 5) 100 pF

5 www.fairchildsemi.com

CD40192BC • CD40193BC

Timing Diagrams

CD40192BC

Sequence:

1. Clear out puts to ze ro.

2. Load (p res et) to BC D s ev en.

3. Count up t o eight, nine, carry, zero, one an d t w o.

4. Count down to one, zero, borrow, nine, eight and seven.

CD40193BC

Sequence:

1. Clear out puts to ze ro.

2. Load (p res et) to binary thirteen.

3. Count up to fourteen, fifteen, carry, zero, one and two.

4. Count down to one, zero, borrow, fifteen, fourteen and thirteen.

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CD40192BC • CD40193BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

7 www.fairchildsemi.com

CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary

Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.