1.6 V, Micropower 12-, 10-, and 8-Bit ADCs in 6-Lead SOT-23 AD7466/AD7467/AD7468 FUNCTIONAL BLOCK DIAGRAM FEATURES Specified for VDD of 1.6 V to 3.6 V Low power: 0.62 mW typ at 100 kSPS with 3 V supplies 0.48 mW typ at 50 kSPS with 3.6 V supplies 0.12 mW typ at 100 kSPS with 1.6 V supplies Fast throughput rate: 200 kSPS Wide input bandwidth: 71 dB SNR at 30 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI(R)-/QSPITM-/MICROWIRETM-/DSP-compatible Automatic power-down Power-down mode: 8 nA typ 6-lead SOT-23 package 8-lead MSOP package VDD VIN 12-/10-/8-BIT SUCCESSIVE APPROXIMATION ADC T/H SCLK CONTROL LOGIC SDATA AD7466/AD7467/AD7468 GND 02643-001 CS Figure 1. APPLICATIONS Battery-powered systems Medical instruments Remote data acquisition Isolated data acquisition GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1 The AD7466/AD7467/AD7468 are 12-, 10-, and 8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 1.6 V to 3.6 V power supply and feature throughput rates up to 200 kSPS with low power dissipation. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz. 1. Specified for supply voltages of 1.6 V to 3.6 V. 2. 12-, 10-, and 8-bit ADCs in SOT-23 packages. 3. High throughput rate with low power consumption. Power consumption in normal mode of operation at 100 kSPS and 3 V is 0.9 mW maximum. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through increases in the serial clock speed. Automatic power-down after conversion allows the average power consumption to be reduced when in power-down. Current consumption is 0.1 A maximum and 8 nA, typically when in power-down. 5. Reference derived from the power supply. 6. No pipeline delay. 7. The part features a standard successive approximation ADC with accurate control of conversions via a CS input. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK. 1 Protected by U.S. Patent No. 6,681,332. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD7466/AD7467/AD7468 TABLE OF CONTENTS AD7466 Specifications..................................................................... 3 Converter Operation.................................................................. 17 AD7467 Specifications..................................................................... 5 ADC Transfer Function............................................................. 17 AD7468 Specifications..................................................................... 7 Typical Connection Diagram ................................................... 18 Timing Specifications....................................................................... 9 Analog Input ............................................................................... 18 Timing Examples........................................................................ 10 Digital Inputs .............................................................................. 19 Absolute Maximum Ratings.......................................................... 11 Normal Mode.............................................................................. 19 ESD Caution................................................................................ 11 Power Consumption .................................................................. 20 Pin Configurations and Function Descriptions ......................... 12 Serial Interface ................................................................................ 22 Typical Performance Characteristics ........................................... 13 Microprocessor Interfacing....................................................... 23 Dynamic Performance Curves ................................................. 13 Application Hints ........................................................................... 25 DC Accuracy Curves.................................................................. 13 Grounding and Layout .............................................................. 25 Power Requirement Curves ...................................................... 13 Evaluating the Performance of the AD7466 and AD7467.... 25 Terminology .................................................................................... 16 Outline Dimensions ....................................................................... 26 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 27 Circuit Information.................................................................... 17 REVISION HISTORY 4/05--Rev. A to Rev. B Moved Terminology Section......................................................... 16 Changes to Ordering Guide .......................................................... 27 11/04--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to General Description .................................................... 1 Added Patent Number ..................................................................... 1 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 5/03--Revision 0: Initial Version Rev. B | Page 2 of 28 AD7466/AD7467/AD7468 AD7466 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the B version is -40C to +85C. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full-Power Bandwidth B Version Unit 69 70 70 70 71 71 70.5 -83 -85 dB min dB min dB typ dB min dB typ dB min dB typ dB typ dB typ -84 -86 10 40 3.2 1.9 750 450 dB typ dB typ ns typ ps typ MHz typ MHz typ kHz typ kHz typ 12 1.5 -0.9/+1.5 Bits LSB max LSB max 1 1 2 LSB max LSB max LSB max 0 to VDD 1 20 V A max pF typ 0.7 x VDD 2 0.2 x VDD 0.3 x VDD 0.8 1 1 10 V min V min V max V max V max A max A typ pF max DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error (TUE) ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding VDD - 0.2 V min 0.2 V max 1 A max 10 pF max Straight (natural) binary Test Conditions/Comments fIN = 30 kHz sine wave. 1.8 V VDD 2 V; see the Terminology section. 2.5 V VDD 3.6 V. VDD = 1.6 V. 1.8 V VDD 2 V; see the Terminology section. 1.8 V VDD 2 V. 2.5 V VDD 3.6 V. VDD = 1.6 V. See the Terminology section. See the Terminology section. fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section. @ 3 dB, 2.5 V VDD 3.6 V. @ 3 dB, 1.6 V VDD 2.2 V. @ 0.1 dB, 2.5 V VDD 3.6 V. @ 0.1 dB, 1.6 V VDD 2.2 V. Maximum specifications apply as typical figures when VDD = 1.6 V. See the Terminology section. Guaranteed no missed codes to 12 bits; see the Terminology section. See the Terminology section. See the Terminology section. See the Terminology section. 1.6 V VDD < 2.7 V. 2.7 V VDD 3.6 V. 1.6 V VDD < 1.8 V. 1.8 V VDD < 2.7 V. 2.7 V VDD 3.6 V. Typically 20 nA, VIN = 0 V or VDD. Sample tested at 25C to ensure compliance. ISOURCE = 200 A, VDD = 1.6 V to 3.6 V. ISINK = 200 A. Rev. B | Page 3 of 28 AD7466/AD7467/AD7468 Parameter CONVERSION RATE Conversion Time Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 4.70 200 s max kSPS max 16 SCLK cycles with SCLK at 3.4 MHz. See the Serial Interface section. 1.6/3.6 V min/max 300 110 20 240 80 16 165 50 10 0.1 A max A typ A typ A max A typ A typ A max A typ A typ A max 0.9 0.6 0.3 0.3 mW max mW max mW max W max Digital inputs = 0 V or VDD. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 3 V, fSAMPLE = 50 kSPS. VDD = 3 V, fSAMPLE = 10 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 50 kSPS. VDD = 2.5 V, fSAMPLE = 10 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 50 kSPS. VDD = 1.8 V, fSAMPLE = 10 kSPS. SCLK on or off, typically 8 nA. See the Power Consumption section. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. VDD = 3 V. Rev. B | Page 4 of 28 AD7466/AD7467/AD7468 AD7467 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the B version is -40C to +85C. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full-Power Bandwidth B Version Unit 61 -72 -74 dB min dB max dB max -83 -83 10 40 3.2 1.9 750 450 dB typ dB typ ns typ ps typ MHz typ MHz typ kHz typ kHz typ 10 0.5 0.5 Bits LSB max LSB max 0.2 0.2 1 LSB max LSB max LSB max 0 to VDD 1 20 V A max pF typ 0.7 x VDD 2 0.2 x VDD 0.3 x VDD 0.8 1 1 10 V min V min V max V max V max A max A typ pF max DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error (TUE) ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate Test Conditions/Comments Maximum/minimum specifications apply as typical figures when VDD = 1.6 V, fIN = 30 kHz sine wave. See the Terminology section. See the Terminology section. See the Terminology section. fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section. @ 3 dB, 2.5 V VDD 3.6 V. @ 3 dB, 1.6 V VDD 2.2 V. @ 0.1 dB, 2.5 V VDD 3.6 V. @ 0.1 dB, 1.6 V VDD 2.2 V. Maximum specifications apply as typical figures when VDD = 1.6 V. See the Terminology section. Guaranteed no missed codes to 10 bits; see the Terminology section. See the Terminology section. See the Terminology section. See the Terminology section. 1.6 V VDD < 2.7 V. 2.7 V VDD 3.6 V. 1.6 V VDD < 1.8 V. 1.8 V V DD < 2.7 V. 2.7 V VDD 3.6 V. Typically 20 nA, VIN = 0 V or VDD. Sample tested at 25C to ensure compliance. VDD - 0.2 V min 0.2 V max 1 A max 10 pF max Straight (natural) binary ISOURCE = 200 A, VDD = 1.6 V to 3.6 V. ISINK = 200 A. 3.52 275 12 SCLK cycles with SCLK at 3.4 MHz. See the Serial Interface section. s max kSPS max Sample tested at 25C to ensure compliance. Rev. B | Page 5 of 28 AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit Test Conditions/Comments 1.6/3.6 V min/max 210 170 140 0.1 A max A max A max A max 0.63 0.42 0.25 mW max mW max mW max Digital inputs = 0 V or VDD. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. SCLK on or off, typically 8 nA. See the Power Consumption section. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. 0.3 W max VDD = 3 V. Rev. B | Page 6 of 28 AD7466/AD7467/AD7468 AD7468 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the B version is -40C to +85C. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full-Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Total Unadjusted Error (TUE) ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate B Version Unit 49 -66 -66 dB min dB max dB max -77 -77 10 40 3.2 1.9 750 450 dB typ dB typ ns typ ps typ MHz typ MHz typ kHz typ kHz typ 8 0.2 0.2 Bits LSB max LSB max 0.1 0.1 0.3 LSB max LSB max LSB max 0 to VDD 1 20 V A max pF typ 0.7 x VDD 2 0.2 x VDD 0.3 x VDD 0.8 1 1 10 V min V min V max V max V max A max A typ pF max VDD - 0.2 V min 0.2 V max 1 A max 10 pF max Straight (natural) binary 2.94 320 s max kSPS max Test Conditions/Comments Maximum/minimum specifications apply as typical figures when VDD = 1.6 V, fIN = 30 kHz sine wave. See the Terminology section. See the Terminology section. See the Terminology section. fa = 29.1 kHz, fb = 29.9 kHz; see theTerminology section. @ 3 dB, 2.5 V VDD 3.6 V. @ 3 dB, 1.6 V VDD 2.2 V. @ 0.1 dB, 2.5 V VDD 3.6 V. @ 0.1 dB, 1.6 V VDD 2.2 V. Maximum specifications apply as typical figures when VDD = 1.6 V. See the Terminology section. Guaranteed no missed codes to 8 bits; see the Terminology section. See the Terminology section. See the Terminology section. See the Terminology section. 1.6 V VDD < 2.7 V. 2.7 V VDD 3.6 V. 1.6 V VDD < 1.8 V. 1.8 V VDD < 2.7 V. 2.7 V VDD 3.6 V. Typically 20 nA, VIN = 0 V or VDD. Sample tested at 25C to ensure compliance. ISOURCE = 200 A; VDD = 1.6 V to 3.6 V. ISINK = 200 A. Sample tested at 25C to ensure compliance. 10 SCLK cycles with SCLK at 3.4 MHz. See the Serial Interface section. Rev. B | Page 7 of 28 AD7466/AD7467/AD7468 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Operational) Power-Down Mode Power Dissipation Normal Mode (Operational) Power-Down Mode B Version Unit 1.6/3.6 V min/max 190 155 120 0.1 A max A max A max A max 0.57 0.4 0.2 0.3 mW max mW max mW max W max Test Conditions/Comments Digital inputs = 0 V or VDD. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. SCLK on or off, typically 8 nA. See the Power Consumption section. VDD = 3 V, fSAMPLE = 100 kSPS. VDD = 2.5 V, fSAMPLE = 100 kSPS. VDD = 1.8 V, fSAMPLE = 100 kSPS. VDD = 3 V. Rev. B | Page 8 of 28 AD7466/AD7467/AD7468 TIMING SPECIFICATIONS For all devices, VDD = 1.6 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V. Table 4. Limit at TMIN, TMAX 3.4 10 20 150 16 x tSCLK 12 x tSCLK 10 x tSCLK Unit MHz max kHz min kHz min kHz min tQUIET 780 640 10 ns max ns max ns min t1 t2 10 55 ns min ns min t3 55 ns max t4 140 ns max t5 t6 t7 0.4 tSCLK 0.4 tSCLK 10 ns min ns min ns min t8 60 ns max 7 ns min tCONVERT Acquisition Time Description Mark/space ratio for the SCLK input is 40/60 to 60/40. 1.6 V VDD 3 V; minimum fSCLK at which specifications are guaranteed. VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed. VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed. AD7466. AD7467. AD7468. Acquisition time/power-up time from power-down. See the Terminology section. The acquisition time is the time required for the part to acquire a fullscale step input value within 1 LSB or a 30 kHz ac input value within 0.5 LSB. VDD = 1.6 V. 1.8 V VDD 3.6 V. Minimum quiet time required between bus relinquish and the start of the next conversion. Minimum CS pulse width. CS to SCLK setup time. If VDD = 1.6 V and fSCLK = 3.4 MHz, t2 has to be 192 ns minimum in order to meet the maximum figure for the acquisition time. Delay from CS until SDATA is three-state disabled. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. Data access time after SCLK falling edge. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. SCLK low pulse width. SCLK high pulse width. SCLK to data valid hold time. Measured with the load circuit in Figure 2 and defined as the time required for the output to cross the VIH or VIL voltage. SCLK falling edge to SDATA three-state. t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part, and is independent of the bus loading. SCLK falling edge to SDATA three-state. 200A TO OUTPUT PIN IOL 1.4V CL 50pF 200A IOH 02643-002 Parameter fSCLK Figure 2. Load Circuit for Digital Output Timing Specifications Rev. B | Page 9 of 28 AD7466/AD7467/AD7468 TIMING EXAMPLES Timing Example 2 Figure 3 and Figure 4 show some of the timing parameters from the Timing Specifications section (Table 4). The AD7466 can also operate with slower clock frequencies. As shown in Figure 4, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a throughput of 50 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 20 s. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 s = 7.55 s, and t8 = 60 ns max, this leaves tQUIET to be 12.39 s, which satisfies the requirement of 10 ns for tQUIET. The part is fully powered up and the signal is fully acquired at Point A, which means the acquisition/power-up time is t2 + 2(1/fSCLK) = 55 ns + 1 s = 1.05 s, satisfying the maximum requirement of 640 ns for the power-up time. In this example and with other slower clock values, the part is fully powered up and the signal already acquired before the third SCLK falling edge; however, the track-and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 4. Timing Example 1 As shown in Figure 4, fSCLK = 3.4 MHz and a throughput of 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 s. Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 4.41 s = 4.46 s, and t8 = 60 ns max, then tQUIET = 5.48 s, which satisfies the requirement of 10 ns for tQUIET. The part is fully powered up and the signal is fully acquired at Point A. This means that the acquisition/power-up time is t2 + 2(1/fSCLK) = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement of 640 ns for the power-up time. t1 CS tCONVERT 1 SCLK t6 A 2 3 4 13 5 14 15 16 t5 t3 SDATA 0 t4 0 THREE-STATE t7 DB11 0 0 t8 tQUIET DB10 DB2 DB1 DB0 THREE-STATE 4 LEADING ZEROS 02643-003 t2 Figure 3. AD7466 Serial Interface Timing Diagram Example CS tCONVERT t2 1 2 A 3 4 5 13 14 16 15 t8 tQUIET ACQUISITION TIME TRACK-AND-HOLD IN TRACK AUTOMATIC POWER-DOWN TRACK-AND-HOLD IN HOLD 1/THROUGHPUT POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED. Figure 4. AD7466 Serial Interface Timing Diagram Example Rev. B | Page 10 of 28 02643-004 SCLK B AD7466/AD7467/AD7468 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to any Pin Except Supplies Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature SOT-23 Package JA Thermal Impedance JC Thermal Impedance MSOP Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infared (15 sec) ESD Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V 10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -40C to +85C -65C to +150C 150C 229.6C/W 91.99C/W 205.9C/W 43.74C/W 215C 220C 3.5 kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 11 of 28 AD7466/AD7467/AD7468 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) CS 1 6 CS 5 SDATA 4 SCLK SDATA 2 SCLK 3 NC 4 AD7466/ AD7467/ AD7468 TOP VIEW (Not to Scale) 8 VDD 7 GND 6 VIN 5 NC NC = NO CONNECT Figure 5. SOT-23 Pin Configuration 02643-006 VIN 3 AD7466/ AD7467/ AD7468 02643-005 VDD 1 GND 2 Figure 6. MSOP Pin Configuration Table 6. Pin Function Descriptions Mnemonic Description CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the devices and frames the serial data transfer. Power Supply Input. The VDD range for the devices is from 1.6 V to 3.6 V. Analog Ground. Ground reference point for all circuitry on the devices. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Data Out. Logic output. The conversion result from the AD7466/AD7467/AD7468 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7466 consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. The data stream from the AD7467 consists of four leading zeros followed by the 10 bits of conversion data, provided MSB first. The data stream from the AD7468 consists of four leading zeros followed by the 8 bits of conversion data, provided MSB first. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the parts. This clock input is also used as the clock source for the conversion process of the parts. No Connect. VDD GND VIN SDATA SCLK NC Rev. B | Page 12 of 28 AD7466/AD7467/AD7468 TYPICAL PERFORMANCE CHARACTERISTICS DYNAMIC PERFORMANCE CURVES DC ACCURACY CURVES Figure 7, Figure 8, and Figure 9 show typical FFT plots for the AD7466, AD7467, and AD7468, respectively, at a 100 kSPS sample rate and a 30 kHz input tone. Figure 14 and Figure 15 show typical INL and DNL performance for the AD7466. Figure 10 shows the signal-to-noise and distortion ratio performance vs. input frequency for various supply voltages while sampling at 100 kSPS with an SCLK frequency of 3.4 MHz for the AD7466. Figure 16 shows the supply current vs. supply voltage for the AD7466 at -40C, +25C, and +85C, with SCLK frequency of 3.4 MHz and a sampling rate of 100 kSPS. Figure 11 shows the signal-to-noise ratio (SNR) performance vs. input frequency for various supply voltages while sampling at 100 kSPS with an SCLK frequency of 3.4 MHz for the AD7466. Figure 12 shows the total harmonic distortion (THD) vs. analog input signal frequency for various supply voltages while sampling at 100 kSPS with an SCLK frequency of 3.4 MHz for the AD7466. POWER REQUIREMENT CURVES Figure 17 shows the maximum current vs. supply voltage for the AD7466 with different SCLK frequencies. Figure 18 shows the shutdown current vs. supply voltage. Figure 19 shows the power consumption vs. throughput rate for the AD7466 with an SCLK of 3.4 MHz and different supply voltages. See the Power Consumption section for more details. Figure 13 shows the THD vs. analog input frequency for different source impedances with a supply voltage of 2.7 V, an SCLK frequency of 3.4 MHz, and sampling at a rate of 100 kSPS for the AD7466 (see the Analog Input section). 25 5 8192 POINT FFT VDD = 1.8V fSAMPLE = 100kSPS fIN = 30kHz SINAD = 61.51dB THD = -80.61dB SFDR = -82.10dB -5 -25 SNR (dB) -15 -35 -55 -45 -65 -75 -115 0 5 10 15 20 25 30 35 FREQUENCY (kHz) 40 45 02643-008 -85 -95 02643-007 SNR (dB) 15 8192 POINT FFT VDD = 1.8V fSAMPLE = 100kSPS fIN = 30kHz SINAD = 70.82dB THD = -84.18dB SFDR = -85.48dB -105 0 50 5 10 15 20 25 30 35 FREQUENCY (kHz) 40 45 Figure 8. AD7467 Dynamic Performance at 100 kSPS Figure 7. AD7466 Dynamic Performance at 100 kSPS Rev. B | Page 13 of 28 50 AD7466/AD7467/AD7468 -5 -15 -25 TEMP = 25C -67 -69 -71 -73 THD (dB) -35 -45 VDD = 1.8V -75 VDD = 2.2V -55 -77 -65 -79 -75 -81 02643-009 -85 -95 0 5 10 15 20 25 30 35 FREQUENCY (kHz) 40 45 VDD = 1.6V VDD = 3V -83 VDD = 3.6V VDD = 2.7V -85 50 10 100 INPUT FREQUENCY (kHz) Figure 12. AD7466 THD vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages Figure 9. AD7468 Dynamic Performance at 100 kSPS -76 -65 TEMP = 25C VDD = 2.7V -66 -77 -67 -78 -68 -79 RIN = 1k THD (dB) -69 VDD = 1.8V VDD = 1.6V VDD = 2.2V -80 RIN = 10 -70 -81 -71 -82 -72 -83 VDD = 3.6V VDD = 3V VDD = 2.7V -73 10 02643-010 SINAD (dB) TEMP = 25C RIN = 510 RIN = 0 -84 10 100 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) Figure 10. AD7466 SINAD vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages Figure 13. AD7466 THD vs. Analog Input Frequency for Various Source Impedances 1.0 TEMP = 25C 0.8 -69.0 0.6 -69.5 0.4 VDD = 1.8V VDD = 1.6V -70.5 VDD = 2.2V -71.0 0.2 0 -0.2 -71.5 -0.4 -72.0 -0.6 -72.5 VDD = 3.6V -73.0 VDD = 3V VDD = 2.7V 10 VDD = 1.8V TEMP = 25C fIN = 50Hz fSAMPLE = 100kSPS 02643-014 -70.0 INL ERROR (LSB) -68.5 02643-011 SNR (dB) -68.0 RIN = 100 02643-013 SNR (dB) -65 8192 POINT FFT VDD = 1.8V fSAMPLE = 100kSPS fIN = 30kHz SINAD = 49.83dB THD = -79.37dB SFDR = -70.46dB 02643-012 5 -0.8 -1.0 0 100 INPUT FREQUENCY (kHz) 512 1024 1536 2048 2560 CODE 3072 Figure 14. AD7466 INL Performance Figure 11. AD7466 SNR vs. Analog Input Frequency at 100 kSPS for Various Supply Voltages Rev. B | Page 14 of 28 3584 4096 AD7466/AD7467/AD7468 1.0 2.5 VDD = 1.8V TEMP = 25C fIN = 50Hz fSAMPLE = 100kSPS 0.8 2.0 SHUTDOWN CURRENT (nA) 0.4 0.2 0 -0.2 -0.4 TEMP = +85C 1.5 1.0 TEMP = +25C TEMP = -40C 02643-015 0.5 -0.6 -0.8 0 512 1024 1536 2048 2560 CODE 3072 3584 0 1.5 4096 2.0 2.5 3.0 SUPPLY VOLTAGE (V) 4.0 1.4 fSAMPLE = 100kSPS TEMP = 25C TEMP = -40C 265 1.2 VDD = 3.0V 240 TEMP = +25C 1.0 215 POWER (mW) SUPPLY CURRENT (A) 3.5 Figure 18. Shutdown Current vs. Supply Voltage Figure 15. AD7466 DNL Performance 290 02643-018 DNL ERROR (LSB) 0.6 190 165 VDD = 2.7V 0.8 0.6 140 VDD = 2.2V 0.4 TEMP = +85C 115 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 3.4 3.6 560 0 440 fSCLK = 3.4MHz, fSAMPLE = 200kSPS fSCLK = 2.4MHz, fSAMPLE = 140kSPS 380 320 260 200 fSCLK = 1.2MHz, fSAMPLE = 50kSPS 80 1.4 02643-017 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) 3.2 3.4 3.6 50 100 150 THROUGHPUT (kSPS) 200 250 Figure 19. Power Consumption vs. Throughput Rate, SCLK 3.4 MHz TEMP = 25C 500 MAXIMUM CURRENT (A) 0 3.8 Figure 16. Supply Current vs. Supply Voltage, SCLK 3.4 MHz 02643-019 65 1.4 VDD = 1.8V 0.2 02643-016 90 3.8 Figure 17. Maximum Current vs. Supply Voltage for Different SCLK Frequencies Rev. B | Page 15 of 28 AD7466/AD7467/AD7468 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7466/ AD7467/AD7468, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Unadjusted Error (TUE) A comprehensive specification that includes gain error, linearity error, and offset error. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (that is, AGND + 1 LSB). Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7466/AD7467/AD7468, it is defined as Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, VREF - 1 LSB) after the offset error has been adjusted out. Track-and-Hold Acquisition Time The time required for the part to acquire a full-scale step input value within 1 LSB, or a 30 kHz ac input value within 0.5 LSB. The AD7466/AD7467/AD7468 enter track mode on the CS falling edge, and return to hold mode on the third SCLK falling edge. The parts remain in hold mode until the following CS falling edge. See Figure 4 and the Serial Interface section for more details. Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output of the ADC. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwidth (fS/2). The rms value of the sine wave is half of its peak-to-peak value divided by 2, and the rms value for the quantization noise is q/12. The ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as SNR = 6.02 N + 1.76 db Thus, for a 12-bit converter, it is 74 dB; for a 10-bit converter, it is 62 dB; and for an 8-bit converter, it is 50 dB. However, in practice, various error sources in the ADCs cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on. THD (dB ) = 20 log V22 + V32 + V42 + V52 + V62 V1 where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) The ratio of the rms value of the next-largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7466/AD7467/AD7468 are tested using the CCIF standard where two input frequencies are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dBs. Rev. B | Page 16 of 28 AD7466/AD7467/AD7468 THEORY OF OPERATION The AD7466/AD7467/AD7468 are fast, micropower, 12-bit, 10-bit, and 8-bit ADCs, respectively. The parts can be operated from a 1.6 V to 3.6 V supply. When operated from any supply voltage within this range, the AD7466/AD7467/AD7468 are capable of throughput rates of 200 kSPS when provided with a 3.4 MHz clock. The AD7466/AD7467/AD7468 provide the user with an onchip track-and-hold, an ADC, and a serial interface housed in a tiny 6-lead SOT-23 or an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part, but also provides the clock source for the successive approximation ADC. The analog input range is 0 V to VDD. An external reference is not required for the ADC, and there is no on-chip reference. The reference for the AD7466/AD7467/AD7468 is derived from the power supply, thus giving the widest possible dynamic input range. When the ADC starts a conversion, as shown in Figure 21, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 22 shows the ADC transfer function. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR A SW1 B CONVERSION PHASE AGND CONTROL LOGIC SW2 02643-021 CIRCUIT INFORMATION COMPARATOR VDD/2 Figure 21. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7466/AD7467/AD7468 is straight binary. The designed code transitions occur at successive integer LSB values; that is, 1 LSB, 2 LSB, and so on. The LSB size for the devices is as follows: CONVERTER OPERATION The AD7466/AD7467/AD7468 are successive approximation analog-to-digital converters based around a charge redistribution DAC. Figure 20 and Figure 21 show simplified schematics of the ADC. Figure 20 shows the ADCs during the acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. VDD/4096 for the AD7466 VDD/1024 for the AD7467 VDD/256 for the AD7468 The ideal transfer characteristics for the devices are shown in Figure 22. SAMPLING CAPACITOR A SW1 B AGND ACQUISITION PHASE CONTROL LOGIC SW2 COMPARATOR VDD/2 02643-020 VIN ADC CODE CHARGE REDISTRIBUTION DAC 111...111 111...110 111...000 011...111 1LSB = VDD/4096 (AD7466) 1LSB = VDD/1024 (AD7467) 1LSB = VDD/256 (AD7468) 000...010 000...001 000...000 0V 1LSB +VDD - 1LSB ANALOG INPUT Figure 20. ADC Acquisition Phase 02643-022 The AD7466/AD7467/AD7468 also feature an automatic power-down mode to allow power savings between conversions. The power-down feature is implemented across the standard serial interface, as described in the Normal Mode section. Figure 22. AD7466/AD7467/AD7468 Transfer Characteristics Rev. B | Page 17 of 28 AD7466/AD7467/AD7468 TYPICAL CONNECTION DIAGRAM Table 7. AD7466 Performance for Voltage Reference IC Figure 23 shows a typical connection diagram for the devices. VREF is taken internally from VDD and, therefore, VDD should be well decoupled. This provides an analog input range of 0 V to VDD. 2.5V 0.1F 240A 5V SUPPLY REF192 1F TANT Reference Tied to VDD ADR318 @ 1.8 V ADR370 @ 2.048 V ADR421 @ 2.5 V ADR423 @ 3 V 10F 0.1F ANALOG INPUT 680nF VDD SCLK VIN AD7466 GND C/P SDATA CS SERIAL INTERFACE 02643-023 0V TO VDD INPUT AD7466 SNR Performance (dB) 70.73 70.72 71.13 71.44 Figure 23. REF192 as Power Supply to AD7466 The conversion result consists of four leading zeros followed by the MSB of the 12-bit, 10-bit, or 8-bit result from the AD7466, AD7467, or AD7468, respectively. See the Serial Interface section. Alternatively, because the supply current required by the AD7466/AD7467/AD7468 is so low, a precision reference can be used as the supply source to the devices. An equivalent circuit of the AD7466/AD7467/AD7468 analog input structure is shown in Figure 24. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes these diodes to become forward-biased and to start conducting current into the substrate. Capacitor C1 in Figure 24 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 200 . Capacitor C2 is the ADC sampling capacitor with a typical capacitance of 20 pF. VDD D1 VIN Table 7 provides some typical performance data with various references used as a VDD source under the same setup conditions. The ADR318, for instance, is a 1.8 V band gap voltage reference. Its tiny footprint, low power consumption, and additional shutdown capability make the ADR318 ideal for battery-powered applications. C1 4pF D2 CONVERSION PHASE--SWITCH OPEN TRACK PHASE--SWITCH CLOSED 02643-024 The REF19x series devices are precision micropower, low dropout voltage references. For the AD7466/AD7467/AD7468 voltage range operation, the REF193, REF192, and REF191 can be used to supply the required voltage to the ADC, delivering 3 V, 2.5 V, and 2.048 V, respectively (see Figure 23). This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at a value other than 3 V or 2.5 V (for example, 5 V). The REF19x outputs a steady voltage to the AD7466/AD7467/AD7468. If the low dropout REF192 is used when the AD7466 is converting at a rate of 100 kSPS, the REF192 needs to supply a maximum of 240 A to the AD7466. The load regulation of the REF192 is typically 10 ppm/mA (REF192, VS = 5 V), which results in an error of 2.4 ppm (6 V) for the 240 A drawn from it. This corresponds to a 0.0098 LSB error for the AD7466 with VDD = 2.5 V from the REF192. For applications where power consumption is important, the automatic power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See the Normal Mode section. C2 R1 20pF Figure 24. Equivalent Analog Input Circuit For ac applications, removing high frequency components from the analog input signal by using a band-pass filter on the relevant analog input pin is recommended. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This might necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Table 8 provides typical performance data for various op amps used as the input buffer under constant setup conditions. Table 8. AD7466 Performance for Input Buffers Op Amp in the Input Buffer AD8510 AD8610 AD797 Rev. B | Page 18 of 28 AD7466 SNR Performance (dB) 30 kHz Input, VDD = 1.8 V 70.75 71.45 71.42 AD7466/AD7467/AD7468 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 13 shows a graph of THD vs. analog input signal frequency for different source impedances when using a supply voltage of 2.7 V and sampling at a rate of 100 kSPS. For the AD7466, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7466 automatically enters power-down mode on the 16th SCLK falling edge. For the AD7467, 14 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7467 automatically enters power-down mode on the 14th SCLK falling edge. DIGITAL INPUTS For the AD7468, 12 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7468 automatically enters power-down mode on the 12th SCLK falling edge. The digital inputs applied to the AD7466/AD7467/AD7468 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7466/AD7467/AD7468 are operated with a VDD of 3 V, 5 V logic levels could be used on the digital inputs. However, the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS or SCLK is applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V is applied prior to VDD. The AD7466 also enters power-down mode if CS is brought high any time before the 16th SCLK falling edge. The conversion that was initiated by the CS falling edge terminates and SDATA goes back into three-state. This also applies for the AD7467 and AD7468; if CS is brought high before the conversion is complete (the 14th SCLK falling edge for the AD7467, and the 12th SCLK falling edge for the AD7468), the part enters power-down, the conversion terminates, and SDATA goes back into three-state. NORMAL MODE The AD7466/AD7467/AD7468 automatically enter powerdown at the end of each conversion. This mode of operation is designed to provide flexible power management options and to optimize the power dissipation/throughput rate ratio for low power application requirements. Figure 25 shows the general operation of the AD7466/AD7467/AD7468. On the CS falling edge, the part begins to power up and the track-and-hold, which was in hold while the part was in power-down, goes into track mode. The conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the track-and-hold returns to hold mode. Although CS can idle high or low between conversions, bringing CS high once the conversion is complete is recommended to save power. When supplies are first applied to the devices, a dummy conversion should be performed to ensure that the parts are in powerdown mode, the track-and-hold is in hold mode, and SDATA is in three-state. Once a data transfer is complete (SDATA has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed, by bringing CS low again. AD7468 ENTERS POWER-DOWN THE PART BEGINS TO POWER UP AD7467 ENTERS POWER-DOWN THE PART IS POWERED UP AND VIN FULLY ACQUIRED AD7466 ENTERS POWER-DOWN CS SDATA 1 2 3 12 14 VALID DATA Figure 25. Normal Mode Operation Rev. B | Page 19 of 28 16 02643-025 SCLK AD7466/AD7467/AD7468 POWER CONSUMPTION The AD7466/AD7467/AD7468 automatically enter powerdown mode at the end of each conversion or if CS is brought high before the conversion is finished. When the AD7466/AD7467/AD7468 are in power-down mode, all the analog circuitry is powered down and the current consumption is typically 8 nA. This reduced power consumption can be seen in Figure 26, which shows the supply current vs. SCLK frequency for various supply voltages at a throughput rate of 100 kSPS. For a fixed throughput rate, the supply current (average current) drops as the SCLK frequency increases because the part is in powerdown mode most of the time. It can also be seen that, for a lower supply voltage, the supply current drops accordingly. To achieve the lowest power dissipation, there are some considerations the user should keep in mind. 390 fSAMPLE = 100kSPS TEMP = 25C 360 Figure 27 shows two AD7466s running with two different SCLK frequencies, SCLK A and SCLK B, with SCLK A having the higher SCLK frequency. For the same throughput rate, the AD7466 using SCLK A has a shorter conversion time than the AD7466 using SCLK B, and it remains in power-down mode longer. The current consumption in power-down mode is very low; thus, the average power consumption is greatly reduced. 330 VDD = 3.6V SUPPLY CURRENT (A) The conversion time is determined by the serial clock frequency; the faster the SCLK frequency, the shorter the conversion time. This implies that as the frequency increases, the part dissipates power for a shorter period of time when the conversion is taking place, and it remains in power-down mode for a longer percentage of the cycle time or throughput rate. 300 270 VDD = 3.0V 240 210 VDD = 2.7V 180 VDD = 2.2V 150 VDD = 1.8V 02643-026 120 90 60 2.2 VDD = 1.6V 2.4 2.6 2.8 3.0 3.2 SCLK FREQUENCY (MHz) 3.4 3.6 Figure 26. Supply Current vs. SCLK Frequency for a Fixed Throughput Rate and Different Supply Voltages 1/THROUGHPUT CONVERSION TIME B CONVERSION TIME A CS 1 16 1 16 SCLK B 02643-027 SCLK A Figure 27. Conversion Time Comparison for Different SCLK Frequencies and a Fixed Throughput Rate 1/THROUGHPUT B 1/THROUGHPUT A POWER DOWN TIME A CONVERSION TIME A CS A POWER DOWN TIME B CONVERSION TIME B CS B 16 02643-028 1 SCLK Figure 28. Conversion Time vs. Power-Down Time for a Fixed SCLK Frequency and Different Throughput Rates Rev. B | Page 20 of 28 AD7466/AD7467/AD7468 Figure 19 shows power consumption vs. throughput rate for a 3.4 MHz SCLK frequency. In this case, the conversion time is the same for all cases because the SCLK frequency is a fixed parameter. Low throughput rates lead to lower current consumptions, with a higher percentage of the time in power-down mode. Figure 28 shows two AD7466s running with the same SCLK frequency, but at different throughput rates. The A throughput rate is higher than the B throughput rate. The slower the throughput rate, the longer the period of time the part is in power-down mode, and the average power consumption drops accordingly. Figure 29 shows the power vs. throughput rate for different supply voltages and SCLK frequencies. For this plot, all the elements regarding power consumption that were explained previously (the influence of the SCLK frequency, the influence of the throughput rate, and the influence of the supply voltage) are taken into consideration. The average power consumption includes the power dissipated when the part is converting and the power dissipated when the part is in power-down mode. The average power dissipated during conversion is calculated as the percentage of the cycle time spent when converting, multiplied by the maximum current during conversion. The average power dissipated in power-down mode is calculated as the percentage of cycle time spent in power-down mode, multiplied by the current figure for power-down mode. In order to obtain the value for the average power, these terms must be multiplied by the voltage. Considering the maximum current for each SCLK frequency for VDD = 1.8 V Power Consumption A = ((4.7/20) x 186 A + (15.3/20) x 100 nA) x 1.8 V = (43.71 + 0.076) A x 1.8 V = 78.8 W = 0.07 mW Power Consumption B = ((13/20) x 108 A + (7/20) x 100 nA) x 1.8 V = (70.2 + 0.035) A x 1.8 V = 126.42 W = 0.126 mW 1.4 TEMP = 25C 1.2 It can be concluded that for a fixed throughput rate, the average power consumption drops as the SCLK frequency increases. VDD = 3.0V, SCLK = 2.4MHz POWER (mW) 1.0 Power Consumption Example 2 0.8 This example shows that, for a fixed SCLK frequency, as the throughput rate decreases, the average power consumption drops. From Figure 28, for SCLK = 3.4 MHz, Throughput A = 100 kSPS (which gives a cycle time of 10 s), and Throughput B = 50 kSPS (which gives a cycle time of 20 s), the following values can be obtained: VDD = 3.0V, SCLK = 3.4MHz 0.6 VDD = 1.8V, SCLK = 2.4MHz 0.4 02643-029 0.2 VDD = 1.8V, SCLK = 3.4MHz 0 0 50 100 150 THROUGHPUT (kSPS) 200 Conversion Time A = 16 x (1/SCLK) = 4.7 s (47% of the cycle time for a throughput of 100 kSPS) 250 Figure 29. Power vs. Throughput Rate for Different SCLK and Supply Voltages Power-Down Time A = (1/Throughput A) - Conversion Time A = 10 s - 4.7 s = 5.3 s (53% of the cycle time) The following examples show calculations for the information in this section. Conversion Time B = 16 x (1/SCLK) = 4.7 s (23.5% of the cycle time for a throughput of 50 kSPS) Power Consumption Example 1 This example shows that, for a fixed throughput rate, as the SCLK frequency increases, the average power consumption drops. From Figure 27, for SCLK A = 3.4 MHz, SCLK B = 1.2 MHz, and a throughput rate of 50 kSPS, which gives a cycle time of 20 s, the following values can be obtained: Power-Down Time B = (1/Throughput B) - Conversion Time B = 20 s - 4.7 s = 15.3 s (76.5% of the cycle time) The average power consumption is calculated as explained in Power Consumption Example 1, considering the maximum current for a 3.4 MHz SCLK frequency for VDD = 1.8 V. Power Consumption A = ((4.7/10) x 186 A + (5.3/10) x 100 nA) x 1.8 V= (87.42 + 0.053) A x 1.8 V = 157.4 W = 0.157 mW Conversion Time A = 16 x (1/SCLK A) = 4.7 s (23.5% of the cycle time) Power-Down Time A = (1/Throughput) - Conversion Time A = 20 s - 4.7 s = 15.3 s (76.5% of the cycle time) Power Consumption B = ((4.7/20) x 186 A + (15.3/20) x 100 nA) x 1.8 V = (43.7 + 0.076) A x 1.8 V = 78.79 W = 0.078 mW Conversion Time B = 16 x (1/SCLK B) = 13 s (65% of the cycle time) Power-Down Time B = (1/Throughput) - Conversion Time B = 20 s - 13 s = 7 s (35% of the cycle time) It can be concluded that for a fixed SCLK frequency, the average power consumption drops as the throughput rate decreases. Rev. B | Page 21 of 28 AD7466/AD7467/AD7468 SERIAL INTERFACE Figure 30, Figure 31, and Figure 32 show the timing diagrams for serial interfacing to the AD7466/AD7467/AD7468. The serial clock provides the conversion clock and controls the transfer of information from the ADC during a conversion. For the AD7468, the 12th SCLK falling edge causes the SDATA line to go back into three-state, and the part enters power-down. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion terminates, the SDATA line goes back into three-state, and the AD7468 enters power down; otherwise SDATA returns to three-state on the 12th SCLK falling edge, as shown in Figure 32. Twelve serial clock cycles are required to perform the conversion process and to access data from the AD7468. The part begins to power up on the CS falling edge. The falling edge of CS puts the track-and-hold into track mode and takes the bus out of three-state. The conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the part should be powered-up fully at Point B, as shown in Figure 30, and the track-and-hold returns to hold. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero; thus, the first clock falling edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. For the AD7466, the final bit in the data transfer is valid on the 16th SCLK falling edge, having been clocked out on the previous (15th) SCLK falling edge. For the AD7466, the SDATA line goes back into three-state and the part enters power-down on the 16th SCLK falling edge. If the rising edge of CS occurs before 16 SCLKs elapse, the conversion terminates, the SDATA line goes back into threestate, and the part enters power-down; otherwise SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 30. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7466. In applications with a slow SCLK, it is possible to read in data on each SCLK rising edge. In such a case, the first falling edge of SCLK after the CS falling edge clocks out the second leading zero and can be read in the following rising edge. If the first SCLK edge after the CS falling edge is a falling edge, the first leading zero that was clocked out when CS went low is missed, unless it is not read on the first SCLK falling edge. The 15th falling edge of SCLK clocks out the last bit, and it can be read in the following rising SCLK edge. For the AD7467, the 14th SCLK falling edge causes the SDATA line to go back into three-state, and the part enters power-down. If the rising edge of CS occurs before 14 SCLKs elapse, the conversion terminates, the SDATA line goes back into three-state, and the AD7467 enters power-down; otherwise SDATA returns to three-state on the 14th SCLK falling edge, as shown in Figure 31. Fourteen serial clock cycles are required to perform the conversion process and to access data from the AD7467. If the first SCLK edge after the CS falling edge is a rising edge, CS clocks out the first leading zero, and it can be read on the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero, and it can be read on the following rising edge. t1 CS tCONVERT SCLK t6 B 1 2 3 4 13 5 14 15 16 t5 t3 SDATA 0 t4 0 THREE-STATE t7 0 0 t8 DB11 tQUIET DB10 4 LEADING ZEROS DB2 DB1 DB0 THREE-STATE 12 BITS OF DATA 02643-030 t2 Figure 30. AD7466 Serial Interface Timing Diagram t1 CS SCLK tCONVERT t6 B 1 2 3 4 t3 0 SDATA THREE-STATE 5 t4 0 0 0 4 LEADING ZEROS 13 t7 DB9 DB8 14 t5 t8 DB0 10 BITS OF DATA Figure 31. AD7467 Serial Interface Timing Diagram Rev. B | Page 22 of 28 tQUIET THREE-STATE 02643-031 t2 AD7466/AD7467/AD7468 t1 CS tCONVERT B 1 SCLK 2 t6 3 4 t3 0 SDATA THREE-STATE 11 t5 t4 0 0 0 12 t8 t7 DB7 DB0 8 BITS OF DATA 4 LEADING ZEROS tQUIET THREE-STATE 02643-032 t2 Figure 32. AD7468 Serial Interface Timing Diagram MICROPROCESSOR INTERFACING AD7466/AD7467/AD7468 to ADSP-218x Interface The serial interface on the AD7466/AD7467/AD7468 allows the parts to be connected directly to many different microprocessors. This section explains how to interface the AD7466/ AD7467/AD7468 with some of the more common microcontroller and DSP serial interface protocols. The ADSP-218x family of DSPs is interfaced directly to the AD7466/AD7467/AD7468 without any glue logic. The SPORT control register must be set up as described in Table 9. Table 9. SPORT Control Register Setup AD7466/AD7467/AD7468 to TMS320C541 Interface The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7466/AD7467/AD7468. The CS input allows easy interfacing between the TMS320C541 and the AD74xx devices, without requiring any glue logic. The serial port of the TMS320C541 is set up to operate in burst mode (FSM = 1 in the serial port control register, SPC) with internal CLKX (MCM = 1 in the SPC register) and internal frame signal (TXM = 1 in the SPC register), so both pins are configured as outputs. For the AD7466, the word length should be set to 16 bits (FO = 0 in the SPC register). The standard synchronous serial port interface in this DSP allows only frames with a word length of 16 bits or 8 bits. Therefore, for the AD7467 and AD7468 where 14 and 12 bits are required, the FO bit also would be set up to 16 bits. In these cases, the user should keep in mind that the last 2 bits and 4 bits for the AD7467 and AD7468, respectively, are invalid data as the SDATA line goes back into three-state on the 14th and 12th SCLK falling edge. To summarize, the values in the SPC register are FO = 0, FSM = 1, MCM = 1, and TXM = 1. Figure 33 shows the connection diagram. For signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provide equidistant sampling. AD7466/ AD7467/ AD74681 TMS320C5411 SCLK CLKX CLKR SDATA CS DR FSX Setting TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 ISCLK = 1 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 SLEN = 1111 SLEN = 1101 SLEN = 1011 The connection diagram in Figure 34 shows how the ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling might not be achieved. The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, therefore, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK goes high, low, and high again before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data can be transmitted, or it can wait until the next clock edge. PINS OMITTED FOR CLARITY. 02643-033 FSR 1ADDITIONAL Description Alternate framing Active low frame signal Right-justify data Internal serial clock Frame every word Sets up RFS as an input Sets up TFS as an output 16 bits for the AD7466 14 bits for the AD7467 12 bits for the AD7468 Figure 33. Interfacing to the TMS320C541 Rev. B | Page 23 of 28 AD7466/AD7467/AD7468 For example, the ADSP-2181 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods elapse for every SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP. AD7466/AD7467/AD7468 to DSP563xx Interface The connection diagram in Figure 35 shows how the AD7466/ AD7467/AD7468 can be connected to the synchronous serial interface (SSI) of the DSP563xx family of DSPs from Motorola. The SSI is operated in synchronous mode and normal mode (SYN = 1 and MOD = 0 in Control Register B, CRB) with an internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in the CRB register). Set the word length in Control Register A (CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not offer the option for a 14-bit AD7466/ AD7467/ AD74681 word length, so the AD7467 word length is set up to 16 bits like the AD7466 word length. In this case, the user should keep in mind that the last two bits are invalid data because the SDATA goes back into three-state on the 14th SCLK falling edge. The frame sync polarity bit (FSP) in the CRB register can be set to 1, which means the frame goes low and a conversion starts. Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB register, it is established that Pins SC2 (the frame sync signal) and SCK in the serial port are configured as outputs, and the most significant bit (MSB) is shifted first. To summarize MOD = 0 SYN = 1 WL2, WL1, WL0 depend on the word length FSL1 = 0, FSL0 = 0 FSP = 1, negative frame sync SCD2 = 1 SCKD = 1 SHFD = 0 For signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidistant sampling. AD7466/ AD7467/ AD74681 ADSP-218x1 SDATA CS SCLK DR SCLK SCK SDATA SRD CS SC2 RFS 1ADDITIONAL PINS OMITTED FOR CLARITY. 02643-034 TFS 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 34. Interfacing to the ADSP-218x Figure 35. Interfacing to the DSP563xx Rev. B | Page 24 of 28 02643-035 SCLK DSP563xx1 AD7466/AD7467/AD7468 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7466/AD7467/ AD7468 should be designed such that the analog and digital sections are separated and confined to certain areas. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the devices are in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7466/AD7467/AD7468. Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7466/AD7467/AD7468 to avoid noise coupling. The power supply lines to the devices should use as large a trace as possible to provide low impedance paths and to reduce the effects of glitches on the power-supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough on the board. A microstrip technique is the best choice, but is not always possible with a double-sided board. With this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also very important. All analog supplies should be decoupled with 10 F tantalum in parallel with 0.1 F capacitors to AGND. All digital supplies should have a 0.1 F ceramic disc capacitor to DGND. To achieve the best performance from these decoupling components, the user should keep the distance between the decoupling capacitor and the VDD and GND pins to a minimum, with short track lengths connecting the respective pins. EVALUATING THE PERFORMANCE OF THE AD7466 AND AD7467 The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via an evaluation board controller. To evaluate the ac and dc performance of the AD7466 and AD7467, the evaluation board controller can be used in conjunction with the AD7466/AD7467CB evaluation board and other Analog Devices evaluation boards ending in the CB designator. The software allows the user to perform ac tests (fast Fourier transform) and dc tests (histogram of codes) on the AD7466 and AD7467. See the technical note in the evaluation board package for more information. Rev. B | Page 25 of 28 AD7466/AD7467/AD7468 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 1.45 MAX 0.50 0.30 0.15 MAX 0.22 0.08 10 4 0 SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AB Figure 36. 6-Lead Small Outline Transistor Package [SOT-23] (RT-6) Dimensions shown in millimeters 3.00 BSC 8 3.00 BSC 1 5 4.90 BSC 4 PIN 1 0.65 BSC 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 37. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. B | Page 26 of 28 0.80 0.60 0.40 AD7466/AD7467/AD7468 ORDERING GUIDE Model AD7466BRT-REEL AD7466BRT-REEL7 AD7466BRT-R2 AD7466BRTZ-REEL3 AD7466BRTZ-REEL73 AD7466BRM AD7466BRM-REEL AD7466BRM-REEL7 AD7466BRMZ3 AD7466BRMZ-REEL3 AD7466BRMZ-REEL73 AD7467BRT-REEL AD7467BRT-REEL7 AD7467BRT-R2 AD7467BRTZ-REEL3 AD7467BRTZ-REEL73 AD7467BRM AD7467BRM-REEL AD7467BRM-REEL7 AD7468BRT-REEL AD7468BRT-REEL7 AD7468BRT-R2 AD7468BRTZ-REEL3 AD7468BRTZ-REEL73 AD7468BRM AD7468BRM-REEL AD7468BRM-REEL7 AD7468BRMZ3 AD7468BRMZ-REEL3 AD7468BRMZ-REEL73 EVAL-AD7466CB4 EVAL-AD7467CB4 EVAL-CONTROL BRD25 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Linearity Error (LSB)1 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 1.5 max 0.5 max 0.5 max 0.5 max 0.5 max 0.5 max 0.5 max 0.5 max 0.5 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 0.2 max 1 Package Option2 RT-6 RT-6 RT-6 RT-6 RT-6 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 RT-6 RT-6 RT-6 RT-6 RT-6 RM-8 RM-8 RM-8 RT-6 RT-6 RT-6 RT-6 RT-6 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Evaluation Board Evaluation Board Control Board Branding CLB CLB CLB C2T C2T CLB CLB CLB C2T C2T C2T CMB CMB CMB CMU CMU CMB CMB CMB CNB CNB CNB CNU CNU CNB CNB CNB CNU CNU CNU Linearity error refers to integral nonlinearity. RT = SOT-23, RM = MSOP. Z = Pb-free part. 4 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 5 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a complete evaluation kit, you need to order a particular ADC evaluation board (such as EVAL-AD7466CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant evaluation board technical notes for more information. 2 3 Rev. B | Page 27 of 28 AD7466/AD7467/AD7468 NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02643-0-4/05(B) Rev. B | Page 28 of 28