Reprinted from ELECTRONIC PRODUCTS JANUARY 2000
24th Annual
Product of the
Year Awards
From the thousands of products introduced in 1999, the editors of Electronic Products have
chosen the most outstanding. The selections are based on significant advances in technolo-
gy or its application, a decided innovation in design, or a substantial gain in price-perfor-
mance. As usual, picking winners was made dif ficult by the many impressive products an-
nounced during the year. Here is a product by Atmel chosen as a 1999 award winner.
E L E C T R O N I C P R O D U C T S
The AT94Kxx family of field-pro-
grammable system-level ICs (FP-
SLICs) makes possible, for the
first time, single-chip systems for small
projects that don’t justify the invest-
ment of an ASIC. At launch, the de-
vices were backed by a complete EDA
tool suite that includes co-verification
of the processor icode and the FPGA
HDL description.
The devices include the company’s
AVR 8-bit processor core (see Electron-
ic Products, May 1998, p. 104), along
with up to 40,000 gates of the AT40K
FPGA family. Other common micro-
controller peripherals such as UART,
SPI, timer/counters, and a hardware
multiplier are also integrated along
with 32 Kbytes of program SRAM.
The family also features a facility for
partial reconfiguration of the FPGA
while the system is running. Several
configurations could be stored in
ROM, and substituted as necessary.
For example, a cell-phone could
change from WCDMA to GSM as it
moved from one country to another.
isons of different hardware/software
partitions, predicting the performance
and power consumption of each possi-
bility. More than 50 pushbutton macro
generators produce hard or soft param-
eterizable cores for the FPGA section.
The user can specify a multiplier (for
example, as “8 x 8” or “12 x 2”) and
need not know any HDL.
System Designer runs on Windows
95/98/NT. The AT94K FPSLIC family
has three members, with 40,000,
20,000, and 10,000 FPGA gates. (AT94,
from $19.90 ea/20,000—samples avail-
able now; System Designer annual sub-
scription, $495—available now.)
Atmel, San Jose, CA
Hotline 800-29-ATMEL
literature@atmel.com
System Designer, the tool suite for
the family, includes co-verification of the
FPGA hardware and the AVR code from
the beginning (see diagram). The suite
includes an instruction-set simulator for
the AVR and a HDL FPGA design simu-
lator that work together before any actu-
al hardware is involved.
The System Designer EDA toolset
supports co-verification of firmware and
HDL, allowing a design to be complete-
ly tested in simulation before any silicon
prototype is needed. A C-like macro lan-
guage can be used to supply the debug
environment with system macros for
host file I/O simulation, reset, startup,
shutdown, loops, if statements, and re-
turn statements. Interrupt simulation
can launch specific interrupts periodi-
cally or at a specific cycle count.
The software allows what-if compar-
AT94Kxx field-programmable system-level ICs
The AT94 micro-
processor/FPGA
allows code and
logic develop-
ment to proceed
hand in hand.
HDL ENTRY
HDL PLANNER
HDL SYNTHESIS
TECHNOLOGY
MAPPING
PLACE AND ROUTE
FPGA BITSTREAM
FPGA IDS BASE
FUNCTIONAL
CO-VERIFICATION
BACK ANNOTATED
CO-VERIFICATION
WAVEFORM
VIEWER
WAVEFORM
VIEWER
C/ASSEMBLY
CODE ENTRY
AVR STUDIO
COMPLIER
AVR
PROGRAMMING
CODE
AVR STUDIO BASE
CO-VERIFICATION
FP SLIC PROGRAMMING
SYSTEM DESIGNER
FPGA/µP enables
single-chip systems
with co-verification of
hardware and code
