TECHNICAL NOTE Memory for Plug & Play DDR/DDR2 (For memory module) SPD Memory BR34E02FVT-W, BR34E02NUX-W Description BR34E02FVT-W is 256x8 bit Electrically Erasable PROM (Based on Serial Presence Detect) Features 256x8 bit architecture serial EEPROM Wide operating voltage range: 1.7V-3.6V Two-wire serial interface High reliability connection using Au pads and Au wires Self-Timed Erase and Write Cycle Page Write Function (16byte) Write Protect Mode Settable Reversible Write Protect Function: 00h-7Fh Write Protect 1 (Onetime Rom) : 00h-7Fh Write Protect 2 (Hardwire WP PIN) : 00h-FFh Low Power consumption Write (at 1.7V ) : 0.4mA (typ.) Read (at 1.7V ) : 0.1mA(typ.) Standby ( at 1.7V ) : 0.1A(typ.) DATA security Write protect feature (WP pin) Inhibit to WRITE at low VCC Compact package: TSSOP-B8, VSON008X2030 High reliability fine pattern CMOS technology Rewriting possible up to 1,000,000 times Data retention: 40 years Noise reduction Filtered inputs in SCL / SDA Initial data FFh at all addresses BR34E02-W Series Capacity Bit format 2Kbit 256X8 Type BR34E02-W Power Source Voltage 1.7V3.6V TSSOP-B8 VSON008X2030 Oct. 2008 Absolute Maximum Ratings (Ta=25) Parameter Supply Voltage Symbol VCC Rating -0.3+6.5 330(BR34E02FVT-W) Power Dissipation Pd 300(BR34E02NUX-W) Storage Temperature Tstg -65+125 Operating Temperature Topr -40+85 Terminal Voltage (A0) -0.310.0 Terminal Voltage (etcetera) -0.3VCC+0.3 * Reduce by 3.3mW(*1), 3.0 mW(*2)/C over 25C Unit V *1 *2 mW V V Recommended operating conditions Parameter Supply Voltage Input Voltage Symbol VCC IN Rating 1.73.6 0VCC Unit V V Memory cell characteristicsTa=25, VCC=1.7V3.6V Specification Parameter Write / Erase Cycle *1 Data Retention *1 Unit Min. Typ. Max. 1,000,000 Cycles 40 Years *1:Not 100% TESTED Electrical characteristics - DCUnless otherwise specified Ta=-40+85, VCC=1.7V3.6V Parameter Symbol Specification Min. Typ. Max. Unit Test Condition "H" Input Voltage VIH1 0.7 VCC - Vcc+0.3 V "L" Input Voltage VIL1 - - 0.3 VCC V "L" Output Voltage 1 VOL1 -0.3 - 0.4 V IOL=2.1mA2.5VVCC3.6VSDA "L" Output Voltage 2 VOL2 - - 0.2 V IOL=0.7mA1.7VVCC2.5VSDA Input Leakage Current 1 ILI1 -1 - 1 A VIN=0VVCCA0,A1,A2,SCL Input Leakage Current 2 ILI2 -1 - 15 A VIN=0VVCCWP Input Leakage Current 3 ILI3 -1 - 20 A VIN=VHV(A0) Output Leakage Current ILO -1 - 1 A VOUT=0VVCC ICC1 - - 1.0 ICC2 - - 3.0 ICC3 - - 0.5 Standby Current ISB - - 2.0 A0 HV Voltage VHV 7 - 10 Operating Current Note: This IC is not designed to be radiation-resistant. 2/20 VCC=1.7V,fSCL=100HztWR=5ms Byte Write Page Write Write Protect VCC =3.6V,fSCL=100Hz, tWR=5ms mA Byte Write Page Write Write Protect VCC =3.6V,fSCL=100Hz mA Random Read Current Read Sequential Read A VCC =3.6V,SDA,SCL= VCC A0,A1,A2=GND,WP=GND mA V VHV-Vcc4.8V Electrical characteristics - ACUnless otherwise specified Ta=-40+85, VCC =1.7V3.6V Parameter FAST-MODE 2.5VVCC5.5V Min. Typ. Max. 400 0.6 1.2 0.3 0.3 0.6 0.6 0 100 0.1 0.9 0.1 0.6 1.2 5 Symbol Clock Frequency fSCL tHIGH Data Clock High Period tLOW Data Clock Low Period tR SDA and SCL Rise Time *1 tF SDA and SCL Fall Time *1 tHD:STA Start Condition Hold Time tSU:STA Start Condition Setup Time tHD:DAT Input Data Hold Time tSU:DAT Input Data Setup Time tPD Output Data Delay Time tDH Output Data Hold Time tSU:STO Stop Condition Setup Time tBUF Bus Free Time tWR Write Cycle Time Noise Spike Width (SDA tI and SCL) tHDWP WP Hold Time tSUWP WP Setup Time tHIGHWP WP High Period STANDARD-MODE 1.7VVCC5.5V Min. Typ. Max. 100 4.0 4.7 1.0 0.3 4.0 4.7 0 250 0.1 3.5 0.1 4.0 4.7 5 Unit kHz s s s s s s ns ns s s s s ms 0.1 0.1 s 0 0.1 1.0 0 0.1 1.0 ns s s *1Not 100 TESTED Fast / Standard Modes Fast mode and Standard mode differ only in operation frequency. Operations performed at 100kHz are considered in "Standard-mode", while those conducted at 400kHz are in "Fast-mode". Please note that these clock frequencies are maximum values. At lower power supply voltage it is difficult to operate at high speeds. The EEPROM can operate at 400kHz, between 2.5V and 3.6V, and at 100kHz from 1.7V-2.5V. Synchronous Data Timing tR tF tHIGH SCL SCL tHD:STA tSU:DAT tLOW tHD:DAT SDA (IN) SDA tBUF tPD DATA(n) DATA(1) D1 D0 ACK ACK tDH tWR SDA (OUT) STOP BIT WP Fig.1-(a) Synchronous Data Timing WP tSUWP SDA data is latched into the chip at the rising edge of SCL clock. Output data toggles at the falling edge of SCL clock. Fig.1-(d) WP Timing Of The Write Operation SCL DATA(n) DATA(1) SCL SDA tSU:STA tHD:STA D1 tSU:STO D0 ACK ACK HIGH : WP SDA WP STOP BIT START BIT Fig.1-(b) Start/Stop Bit Timing SCL SDA D0 ACK WRITE DATA(n) tWR STOP CONDITION START CONDITION tWR Fig.1-(e) WP Timing Of The Write Cancel Operation For WRITE operation, WP must be "Low" from the rising edge of the clock (which takes in D0 of first byte) until the end of tWR. (See Fig.1-(d) ) During this period, WRITE operation can be canceled by setting WP "High".See Fig.1-(e) When WP is set to "High" during tWR, WRITE operation is immediately ceased, making the data unreliable. It must then be re-written. Fig.1-(c) Write Cycle Timing 3/20 Block diagram PROTECT_MEMORY_ARRY A0 1 8 VCC 2Kbit_MEMORY_ARRY 8bit 8bit ADDRESS DECODER A1 2 8bit SLAVE , WORD ADDRESS REGISTER START A2 3 DATA REGISTER 7 WP STOP 6 SCL CONTOROL LOGIC ACK GND 4 HIGH VOLTAGE GEN. 5 SDA VCC LEVEL DETECT Fig.2 Block Diagram Pinout diagram and description Pin Name A0 1 BR34E02FVT-W 7 WP A2 3 BR34E02NUX-W 6 SCL GND 4 Functions VCC GND Ground 0V A0,A1,A2 IN Slave Address Set. SCL IN Serial Clock Input SDA IN / OUT WP IN 8 VCC A1 2 Input/Output Power Supply Slave and Word Address, *1 Serial Data Input, Serial Data Output 5 SDA Write Protect Input *2 *1 Open drain output requires a pull-up resistor. Fig.3 Pin Configuration *2 WP Pin has a Pull-Down resistor. Please leave unconnected or connect to GND when not in use. 6 5 5 4 4 SPEC 3 1 0.8 3 2 Ta=85 Ta=-40 Ta=25 2 Ta=85 Ta=-40 Ta=25 1 2 3 4 0 1 2 VCC[V] 2 34:I C Fig.4 "H" Input Voltage VIH (A0,A1,A2,SCL,SDA,WP) SPEC 0.4 Ta=85 SPEC 0 1 0.6 Ta=25 0.2 1 0 0 VOL1[V] 6 VIL1,2[V] VIH1,2[V] Electrical characteristics curves The following characteristic data are typ. value. 3 Ta=-40 0 4 0 1 2 3 4 VCC[V] IOL1[mA] Fig.5 "L" Input Voltage VIL (A0,A1,A2,SCL,SDA,WP) Fig.6 "L" Output Voltage VOL1-IOL1 (VCC=2.5V) 1 1.2 16 SPEC SPEC 1 0.8 12 Ta=85 0.4 0.6 8 0.4 Ta=25 SPEC ILI2[A] ILI1[ A] VOL2[V] 0.8 0.6 Ta=85 Ta=25 Ta=-40 4 0.2 Ta=85 Ta=25 Ta=-40 0.2 Ta=-40 0 0 0 1 2 3 4 IOL2[mA] Fig.7 "L" Output Voltage VOL2-IOL2 (VCC=1.7V) 0 0 1 2 3 4 VCC[V] Fig.8 Input Leakage Current ILI1 (A0,A1,A2,SCL,SDA) 4/20 0 1 2 3 4 VCC[V] Fig.9 Input Leakage Current ILI2 (WP) 0.6 2.5 SPEC1 3 2.5 1.5 SPEC2 1 =100kHz DATA=AAh 0.3 1.5 1 Ta=85 0.2 Ta=25 Ta=85 Ta=-40 0.5 SPEC 2 0.4 SCL=400kHz(VCC2.5V) fSCL=100kHz(1.7VVccV) DATA=AA 2 ICC3[mA] ICC1,2[mA] SPEC 0.5 ISB[A] 3.5 Ta=25 0.5 0.1 0 0 0 0 1 2 3 0 4 1 2 3 0 4 VCC[V] Ta=25 Ta=-40 SPEC2 4 4 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 10 1 2 3 1 0 0 4 1 2 3 4 0 SPEC1,2 4 1 Ta=-40 Ta=25 Ta=85 SPEC1 0 3 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 Ta=-40 Ta=25 Ta=85 1 0 tHD:DAT(HIGH)[s] tSU:STA[s] 2 SPEC1 1 2 3 4 0 1 VCC[V] 2 Ta=85 Ta=25 Ta=-40 -50 -100 SPEC1:FAST-MODE SPEC2:STANDARD-MODE -150 0 0 4 50 SPEC2 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 3 Fig.15 Data Clock Low Period tLow 5 SPEC2 4 2 VCC[V] Fig.14 Data Clock High Period tHigh 5 3 1 VCC[V] VCC[V] Fig.13 Clock Frequency fSCL Ta=85 Ta=25 Ta=-40 SPEC1 0 1 tHD:STA[s] SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 Ta=-40 Ta=25 Ta=85 SPEC1 1 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 3 tLOW[s] 3 tHIGH[s] fSCL[kHz] 1000 SPEC1 4 5 SPEC2 SPEC2 3 Fig.12 Standby Current ISB 5 Ta=85 2 VCC[V] Fig.11 Read Operating Current ICC3 (fSCL=400kHz) 10000 0 1 VCC[V] Fig.10 Write Operating Current ICC1,2 (fSCL=100kHz,400kHz) 100 Ta=85 Ta=25 Ta=-40 Ta=-40 3 -200 4 0 VCC[V] 1 2 3 4 VCC[V] Fig.16 Start Condition Hold Time tHD:STA Fig. St t C SPEC1,2 tSU:DAT(HIGH)[ns] tHD:DAT(LOW)[s] 0 SPEC1:FAST-MODE -50 SPEC2:STANDARD-MODE -100 Ta=85 -150 0 1 300 200 200 SPEC1 100 2 3 4 VCC[V] Fig.19 Data Hold Time tHD:DAT(LOW) Ta=85 Ta=25 Ta=-40 0 SPEC2 100 Ta=85 0 Ta=25 -100 SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=-40 -200 Ti 300 -100 Ta=25 S t tSU:DAT(LOW)[ns] 50 diti Fig.18 Data Hold Time tHD:DAT(High) SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=-40 -200 -200 0 1 2 3 4 VCC[V] Fig.20 Input Data Setup Time tSU:DAT(HIGH) 5/20 0 1 2 3 4 VCC[V] Fig.21 Input Data Setup Time tSU:DAT(LOW) 4 4 5 SPEC2 SPEC2 2 Ta=85 Ta=25 Ta=-40 SPEC1 1 SPEC2 0 SPEC1 0 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 1 3 VCC[V] Fig.22 Output Data Delay Time tPD SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 Ta=85 Ta=25 Ta=-40 SPEC1 0 1 2 4 3 1 SPEC1 0 2 Ta=85 Ta=25 Ta=-40 SPEC2 0 1 tSU:STO[s] tDH[s] SPEC1:FAST-MODE SPEC2:STANDARD-MODE tPD[s] 4 3 3 3 0 4 1 2 3 4 VCC[V] VCC[V] Fig.23 Output Data Hold Time tDH Fig.24 Stop Condition Setup Time tSU:STO 5 0.6 6 SPEC2 SPEC1,2 4 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0.5 5 tWR[ms] SPEC1:FAST-MODE SPEC2:STANDARD-MODE 2 SPEC1 Ta=85 2 Ta=85 1 3 2 3 4 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0 1 VCC[V] 0 3 0.4 Ta=-40 Ta=25 0.4 0 Ta=-40 Ta=85 0.2 2 3 4 2 3 SPEC1,2 1 Ta=25 Ta=85 tHIGH:WP[s] 0 0.8 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0.6 0.4 -0.4 Ta=-40 Ta=25 Ta=85 0.2 Ta=-40 -0.6 0 0 1 2 3 4 VCC[V] Fig.31 WP Setup Time tSU:WP 0 1 2 VCC[V] 3 Fig.32 WP High Period tHigh:WP 6/20 1 2 3 4 Fig.30 Noise Spike Width tI(SDA L) 1.2 -0.2 SPEC1,2 VCC[V] Fig.29 Noise Spike Width tI(SDA H) SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=85 0.2 0 4 VCC[V] SPEC1,2 Ta=25 0 1 VCC[V] 0.2 Ta=-40 0.3 0.1 0 Fig.28 Noise Spike Width tI(SCL L) 4 0.4 SPEC1,2 0 1 3 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0.5 Ta=25 0.3 2 Fig.27 Noise Spike Width tI(SCL H) 0.6 0.1 SPEC1,2 0 1 VCC[V] Ta=85 0.1 tSU:WP[s] 0 4 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0.5 tI(SDA H)[s] tI(SCL L)[s] 2 0.6 SPEC1:FAST-MODE SPEC2:STANDARD-MODE 0.2 Ta=85 0.2 Fig.26 Write Cycle Time tWR 0.6 0.3 0.3 VCC[V] Fig.25 Bus Free Time tBUF 0.5 Ta=25 SPEC1,2 0 1 0.4 0.1 1 Ta=25 Ta=-40 0 0 Ta=25 tI(SDA L)[s] tBUF[s] 3 Ta=-40 tI(SCL H)[s] Ta=-40 4 4 2 Data transfer on the I C BUS 2 Data transfer on the I C BUS The BUS is considered to be busy after the START condition and free a certain time after the STOP condition. Every SDA byte must be 8-bits long and requires an ACKNOWLEDGE signal after each byte. The devices have Master and Slave configurations. The Master device initiates and ends data transfer on the BUS and generates the clock signals in order to permit transfer. The EEPROM in a slave configuration is controlled by a unique address. Devices transmitting data are referred to as the Transmitter. The devices receiving the data are called Receiver. START Condition (Recognition of the START bit) All commands are proceeded by the start condition, which is a High to Low transition of SDA when SCL is High. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.1-(b) START/STOP Bit Timing) STOP Condition (Recognition of STOP bit) All communications must be terminated by a stop condition, which is a Low to High transition of SDA when SCL is High. (See Fig.1-(b) START/STOP Bit Timing) Write Protect By Soft Ware Set Write Protect command and permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Acknowledge Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS after transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the -COM. When outputting the data during read operation, the Transmitter is the EEPROM. During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When outputting the data during read operation the receiver is the -COM.) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word (word address and write data). In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an Acknowledge. If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to standby mode. Device Addressing Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits of the slave address are the "device type indentifier." For this EEPROM it is "1010." (For WP register access this code is "0110".) The next three bits identify the specified device on the BUS (device address). The device address is defined by the state of the A0,A1 and A2 input pins. This IC works only when the device address input from the SDA pin corresponds to the status of the A0,A1 and A2 input pins. Using this address scheme allows up to eight devices to be connected to the BUS. 7/20 The last bit of the stream (R/W...READ/WRITE) determines the operation to be performed. R/W=0 R/W=1 Slave Address Set Pin A2 A1 A0 A2 A1 WRITE (including word address input of Random Read) READ Device Type 1010 A0 Device Address A2 A1 A0 A2 A1 Read Write Mode R/W R/W A0 Access Area 2kbit Access to Memory Access to Permanent Set Write Protect Memory Access to Set Write Protect Memroy Access to Clear Write Protect MEmory 0110 GND GND VHV 0 0 1 R/W GND Vcc VHV 0 1 1 R/W WRITE PROTECT PIN(WP) When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level), it is enable to write 256 words (all address). If permanent protection is done by Write Protect command, lower half area (007Fh address) is inhibited writing regardless of WP pin state. WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use. Confirm Write Protect Resistor by ACK According to state of Write Protect Resistor, ACK is as follows. State of Write WP Input Input Command ACK Address Protect Registor PSWP, SWP, CWP No ACK In case, Page or Byte Write protect by PSWP ACK WA7WA0 (007Fh) 0 In case, protect by SWP 1 In case, Not protect 0 1 SWP CWP PSWP Page or Byte Write (007Fh) SWP CSP PSWP Page or Byte Write PSWP, SWP, CWP No ACK No ACK Write Cycle(tWR) No ACK ACK D7D0 No ACK No - No ACK ACK ACK - No ACK ACK ACK No Yes Yes ACK WA7WA0 ACK D7D0 No ACK No - No ACK ACK ACK ACK - No ACK D7D0 - No ACK No ACK No ACK ACK ACK ACK Page or Byte Write PSWP, SWP, CWP Page or Byte Write ACK State of Write Protect Registor Command In case, protect by PSWP PSWP, SWP, CWP SWP CWP PSWP PSWP, SWP, CWP In case, Not protect Data No ACK ACK ACK ACK ACK ACK In case, protect by SWP ACK 8/20 No No No No ACK No ACK ACK Yes ACK ACK WA7WA0 D7D0 Yes ACK No ACK No ACK WA7WA0 D7D0 No ACK No - is Don't Care ACK Address ACK Data ACK No ACK No ACK No ACK No ACK No ACK No ACK ACK No ACK No ACK ACK No ACK No ACK ACK No ACK No ACK WA7WA0 - Command Write Cycle During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte. In the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that can be written at one time is 16 bytes. S T A R T SDA LINE W R I T E SLAVE ADDRESS WORD ADDRESS WA 7 1 0 1 0 A2 A1 A0 S T O P DATA WA 0 D7 D0 A C K A C K R A / C W K Fig.33 Byte Write Cycle Timing S T A R T SDA L IN E S LA V E ADDRESS W R I T E W ORD A D D R E S S (n ) WA 7 1 0 1 0 A 2A 1A 0 R A / C W K D A TA (n) WA 0 D7 A C K S T O P D A TA (n + 1 5) D0 D0 A C K A C K Fig.34 Page Write Cycle Timing With this command the data is programmed into the indicated word address. When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. Once programming is started no commands are accepted for tWR (5ms max.). This device is capable of sixteen-byte Page Write operations. If the Master transmits more than sixteen words prior to generating the STOP condition, the address counter will "roll over" and the previously transmitted data will be overwritten. When two or more byte of data are input, the four low order address bits are internally incremented by one after the receipt of each word, while the four higher order bits of the address (WA7WA4) remain constant. 9/20 Command Read Cycle During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and Current Read Cycle. The Random Read Cycle reads the data in the indicated address. The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the Sequential Read Cycle it is possible to continuously read the next data. S T A R T SDA L IN E W R I T E SLAVE ADDRESS W ORD A D D R E S S (n ) WA 7 1 0 1 0 A 2 A 1A 0 S T A R T WA 0 R A / C W K It is necessary to input "High" at last ACK timing. SLAVE ADDRESS R E A D S T O P D A TA (n) 1 0 1 0 A 2 A 1A 0 D7 D0 A C K R A / C W K A C K Fig.35 Random Read Cycle Timing S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2 A1 A0 S T O P DATA D7 It is necessary to input "High" at last ACK timing. D0 A C K R A / C W K Fig.36 Current Read Cycle Timing Random Read operation allows the Master to access any memory location indicated by word address. In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If an Acknowledge is detected and no STOP condition is generated by the Master (-COM), the device will continue to transmit data. (It can transmit all data (2kbit 256word)) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to standby mode. If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input Acknowledge with "High" always, then input a STOP condition. S T A R T SDA L IN E R E A D SLAVE ADDRESS 1 0 1 0 A 2A 1A 0 D7 R A / C W K Fig.37 D A T A (n ) S T O P D A T A (n + x) D0 D7 A C K A C K Sequential Read Cycle Timing With Current Read 10/20 D0 A C K It is necessary to input "High" at last ACK timing. Write Protect Cycle S T A R T SDA L IN E W R I T E SLAVE ADDRESS W ORD ADDRESS 0 1 1 0 A 2A 1A 0 * D ATA * R A / C W K WP S T O P * * A C K A C K *:D O N 'T C A R E Fig. 38 Permanent Write Protect Cycle Permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Set Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACK in each protect state. S T A R T SDA L IN E WP SLAVE ADDRESS W R I T E 0 1 1 0 0 0 1 W ORD ADDRESS * D ATA * R A / C W K S T O P * A C K * A C K *:D O N 'T C A R E Fig. 39 Set Write Protect Cycle Permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Set Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACk in each protect state. 11/20 S T A R T SDA L IN E W R I T E SLAVE ADDRESS 0 1 1 0 0 1 1 W ORD ADDRESS * WP D ATA * R A / C W K S T O P * A C K * A C K *:D O N 'T C A R E Fig. 40 Clear Write Protect Cycle Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Clear Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACk in each protect state. Software Reset Execute software reset in the event that the device is in an unexpected state after power up and/or the command input needs to be reset. Below are three typesFig.39 -(a), (b), (c) of software reset: During dummy clock, release the SDA BUS (tied to VCC by a pull-up resistor). During this time the device may pull the SDA line Low for Acknowledge or the outputting of read data.If the Master sets the SDA line to High, it will conflict with the device output Low, which can cause current overload and result in instantaneous power down, which may damage the device. DUMMY CLOCKx14 SCL 1 2 13 STARTx2 14 COMMAND SDA COMMAND Fig.39-(a) DUMMY CLOCKx14 + START+START START 1 SCL START DUMMY CLOCKx9 2 8 9 COMMAND SDA COMMAND Fig.39-(b) START + DUMMY CLOCKx9 + START STARTx9 SCL 1 2 3 7 8 SDA 9 COMMAND COMMAND Fig.39-(c) STARTx9 * COMMAND starts with start condition. 12/20 Acknowledge polling Since the IC ignores all input commands during the internal write cycle, no ACK signal will be returned. When the Master sends the next command after the Write command, if the device returns an ACK signal it means that the program is completed. No ACK signal indicates that the device is still busy. Using Acknowledge polling decreases the waiting time by tWR=5ms. When operating Write or Current Read after Write, first transmit the Slave address (R/W is"High" or "Low"). After the device returns the ACK signal continue word address input or data output. During the internal write cycle, no ACK will be returned. THE FIRST WRITE COMMAND (ACK=High) S T A R T WRITE COMMAND S T A R T S O P S T A R T A C K H SLAVE ADDRESS SLAVE ADDRESS A C K H tWR THE SECOND WRITE COMMAND S T A R T SLAVE ADDRESS S T A R T A C K H A C K L SLAVE ADDRESS WORD ADDRESS tWR A C K L DATA A C K L S O P After the internal write cycle is completed, ACK will be returned (ACK=Low). Then input next Word Address and data. Fig.40 Successive Write Operation By Acknowledge Polling WP effective timing WP is normally fixed at "H" or "L". However, in case WP needs to be controlled in order to cancel the Write command, pay attention to "WP effective timing" as follows: The Write command is canceled by setting WP to "H" within the WP cancellation effective period. The period from the START condition to the rising edge of the clock (which takes in the data DO - the first byte of the Page Write data) is the `invalid cancellation period'. WP input is considered inconsequential during this period. The setup time for the rising edge of the SCL, which takes in DO, must be more than 100ns. The period from the rising edge of SCL (which takes in the data D0) to the end of internal write cycle (tWR) is the `effective cancellation period'. When WP is set to "H" during tWR, Write operation is stopped, making it necessary to rewrite the data. It is not necessary to wait for tWR (5ms max.) after stopping the Write command by WP because the device is in standby mode. The rising edge of the clock which take in D0 SCL SDA D1 D0 The rising edge of SDA SCL SDA ACK D0 AN ENLARGEMENT AN ENLARGEMENT SDA WP S A T SLAVE C WORD A K R ADDRESS L ADDRESS T ACK A A C C D2 D7 D6 D5 D0 D1 D4 D3 K K L L DATA A C K L S T O P tWR WP cancellation WP cancellation Stop of the write invalid period effective period operation Data is not No data will be written Fig.41 WP effective timing 13/20 guaranteed Command cancellation from the START and STOP conditions Command input is canceled by successive inputs of START and STOP conditions. (Refer to Fig.42) However, during ACK or data output, the device may set the SDA line to Low, making operation of the START and STOP conditions impossible, and thus preventing reset. In this case execute reset by software. (Refer to Fig.39) The internal address counter will not be determined when operating the Cancel command by the START and STOP conditions during Random, Sequential or Current Read. Operate a Random Read in this case. SCL SDA 1 0 1 0 START CONDITION STOP CONDITION Fig.42 Command cancellation by the START and STOP conditions during input of the Slave Address I/O Circuit SDA Pin Pull-up Resistor A pull-up resistor is required because SDA is an NMOS open drain. Determine the resistor value of (RPU) by considering the VIL and IL, and VOL-IOL characteristics. If a large RPU is chosen, the clock frequency needs to be slow. A smaller RPU will result in a larger operating current. Maximum RPU The maximum of RPU can be determined by the following factors. The SDA rise time determined by RPU and the capacitance of the BUS line(CBUS) must be less than tR. In addition, all other timings must be kept within the AC specifications. When the SDA BUS is High, the voltage A at the SDA BUS is determined from the total input leakage(IL) of all devices connected to the BUS. RPU must be higher than the input High level of the microcontroller and the device, including a noise margin 0.2VCC. RPU RPU 0.8VCC-VIH IL SDA PIN A Examples: When VCC =3V, IL=10A, VIH=0.7 VCC According to RPU BR34E02 Microcontroller VCC-ILRPU-0.2 VCC VIH 0.8x3-0.7x3 -6 10x10 IL IL THE CAPACITANCE 300 k OF BUS LINE (CBUS) Fig.43 I/O Circuit 14/20 Minimum RPU The minimum value of RPU is determined by following factors. Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low. VCC-VOL IOL RPU RPU VCC-VOL IOL VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROM including the recommended noise margin of 0.1VCC. VOLMAX VIL-0.1 VCC Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC, According to RPU 3-0.4 3x10 -3 867 VOL=0.4V VIL=0.3x3 =0.9V so that condition is met and And SCL Pin Pull-up Resistor When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required. However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended. Several k are recommended for the pull-up resistor in order to drive the output port of the microcontroller. A0, A1, A2, WP Pin connections Device Address Pin (A0, A1, A2) connections The status of the device address pins is compared with the device address sent by the Master. One of the devices that is connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that are not used as device address (N.C.Pins) may be High, Low, or Hi-Z. WP Pin connection The WP input allows or prohibits write operations. When WP is High, only Read is available and Write to all address is prohibited. Both Read and Write are available when WP is Low. In the event that the device is used as a ROM, it is recommended that the WP input be pulled up or connected to VCC. When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled. Microcontroller connection Concerning Rs The open drain interface is recommended for the SDA port in the I2C BUS. However, if the Tri-state CMOS interface is applied to SDA, insert a series resistor (Rs) between the SDA pin of the device and the pull up resistor RPU is recommended, since it will serve to limit the current between the PMOS of the microcontroller, and the NMOS of the EEPROM. Rs also protects the SDA pin from surges. Therefore, Rs is able to be used though open drain inout of the SDA port. ACK RPU SCL RS SDA 'H'OUTPUT OF CONTROLLER "L" OUTPUT OF EEPROM CONTROLLER The "H" output of controller and the "L" output of EEPROM may cause current overload to SDA line. EEPROM Fig.44 I/O Circuit Fig.45 Input/Output Collision Timing 15/20 Rs Maximum The maximum value of Rs is determined by following factors. SDA rise time determined by RPU and the capacitance value of the BUS line (CBUS) of SDA must be less than tR. In addition, the other timings must be within the timing conditions of the AC. When the output from SDA is Low, the voltage of the BUS at A is determined by RPU, and Rs must be lower than the input Low level of the microcontroller, including recommended noise margin (0.1VCC). VCC RPU RS (VCC-VOL)xRS RPU+RS A VOL RS IOL BUS CAPACITANCE VIL + VOL+0.1VCCVIL VIL-VOL-0.1VCC 1.1VCC-VIL x RPU Examples : When VCC=3V VIL=0.3VCC VOL=0.4V RPU=20k EEPROM CONTROLLER According to RS 0.3x3-0.4-0.1x3 1.1x3-0.3x3 x 20x103 1.67 k Fig.46 I/O Circuit Rs Minimum The minimum value of Rs is determined by the current overload during BUS conflict. Current overload may cause noises in the power line and instantaneous power down. The following conditions must be met, where "I" is the maximum permissible current, which depends on the Vcc line impedance as well as other factors. "I" current must be less than 10mA for EEPROM. Vcc RS RS RPU RS "L" OUTPUT I Vcc I Examples: When VCC=3V, I=10mA RS "H" OUTPUT MAXIMUM CURRENT CONTROLLER 3 10x10-3 300 EEPROM Fig.47 I/O Circuit 16/20 2 I C BUS Input / Output equivalent circuits Input (A0,A2,SCL) Fig.48 Input Pin Circuit Input / Output (SDA) Fig.49 Input / Output Pin Circuit Input (A1) Fig.50 Input Pin Circuit Input (WP) Fig.51 Input Pin Circuit 17/20 Power Supply Notes VCC increases through the low voltage region where the internal circuit of IC and the microcontroller are unstable. In order to prevent malfunction, the IC has P.O.R and LVCC functionality. During power up, ensure that the following conditions are met to guaranty P.O.R. and LVCC operability. 1. "SDA='H'" and "SCL='L' or 'H'". 2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up. tR VCC Recommended conditions of tR, tOFF, Vbot tR tOFF Vbot tOFF Below 10ms Vbot Above 10ms Below 0.3V Below 100ms Above 10ms Below 0.2V 0 Fig.52 VCC rising wavefrom 3. Prevent SDA and SCL from being "Hi-Z". In case that condition 1. and/or 2. cannot be met, take following actions. A If unable to keep Condition 1 (SDA is "Low" during power up) Make sure that SDA and SCL are "High" as in the figure below. VCC tLOW SCL SDA After Vcc becomes stable After Vcc becomes stable tDH tSU:DAT Fig.53 SCL="H" and SDA="L" tSU:DAT Fig.54 SCL="L" and SDA="L" B If unable to keep Condition 2 After the power stabilizes, execute software reset. (See page 9,10) C If unable to keep either Condition 1 or 2 Follow Instruction A first, then B LVCC Circuit The LVCC circuit prevents Write operation at low voltage and prevents inadvertent writing. A voltage below the LVCC voltage (1.2V typ.) prohibits Write operation. VCC Noise Bypass Capacitor Noise and surges on the power line may cause abnormal function. It is recommended that bypass capacitors (0.1F) be attached between VCC and GND externally. Cautions On Use 1) Descrived numeric values and data are design representative values, and the values are not guaranteed. 2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. 3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. 4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. 5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. 6) Terminal to terminal short circuit and wrong packaging When to package LSI on to a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. 7) Use in a strong electromagnetic field may cause malfunction, therfore, evaluate design sufficiently. 18/20 Selection of order type B R ROHM type 3 BUS type 4 E 0 Product type 2 F V T W Package type Capacity 02=2K E Double Cell FVT:TSSOP-B8 NUX:VSON008X2030 2 Package specifications E2:reel shape emboss taping TR: reel shape emboss taping Package Specifications TSSOP-B8 <Dimension> <Tape and Reel information> Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 1234 1234 1234 1234 (Unit:mm) 1234 1234 1234 1234 1Pin Reel Direction of feed When you order , please order in times the amount of package quantity. VSON008X2030 <Dimension> <Tape and Reel information> Embossed carrier tape Tape Quantity 4000pcs Direction of feed TR (The direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) 1Pin Direction of feed Reel When you order , please order in times the amount of package quantity. (Unit:mm) 19/20 Catalog No.08T506A '08.10 ROHM (c) Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. 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