RM9220
Preliminary
RM9220 Integrated Multiprocessor
PMC-2021652 PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC.,
© Copyright PMC-Sierra, Inc. 2003–2004.
Issue 5
AND FOR ITS CUSTOMERS’ INTERNAL USE
All rights reserved.
FEATURES
The RM9220 Integrated Multiprocessor
builds on the success of PMC-Sierra's
next generation MIPS-based E9K
processors by providing features specifi-
cally suited for network processing appli-
cations. It provides:
• Dual CPU cores compatible with the
MIPS64 Instruction Set Architecture.
• High-speed integrated DDR SDRAM
Controller, SysAD, Local Bus,
HyperTransport, Ethernet MAC
interfaces. Option to bypass the
Ethernet MAC interface to provide a
high-speed Generic Packet Interface
(GPI).
DUAL 1 GHz PROCESSORS
Each processor features:
• A dual issue superscalar 7-stage
pipeline.
• 16-Kbyte, 4-way set associative L1
Instruction and Data caches.
• 256 Kbyte, 4-way set associative L2
cache with deterministic access time
for highest performance. L2 cache is
ECC protected.
• Fast Packet Cache™ mode to assist
packet data processing.
• 8K entry branch prediction table.
• Fully associative 64-entry TLB with
dual pages.
• Multiple reads with out-of-order return.
• High-performance Floating Point Unit
(IEEE 754).
• Fixed-point DSP instructions.
CACHE AND I/O COHERENCY
• Maintains hardware cache coherency
with the 5-State MOESI protocol. All
cache transfers between processors
occur at the CPU pipeline frequency.
• Supports full hardware I/O coherency
over HyperTransport, SysAD, Ethernet
MAC/GPI networking interfaces
allowing I/O devices access to
coherent memory.
• Provides Direct Deposit Cache mode
allowing the DMA of packet headers
directly into L2 cache from
HyperTransport, SysAD, Ethernet
MAC and Generic Packet interfaces.
160 Gbps MULTI-PORT PACKET
SWITCH
• Connects processors to memory and
I/O interfaces.
• Supports simultaneous transfers on all
ports.
200 MHz MEMORY CONTROLLER
• Supports 25.6 Gbps memory.
• Supports DDR SDRAM options.
• Supports 2 Gbytes using 512 Mbit
SDRAM and 4 Gbytes using 1 Gbit
SDRAM.
NETWORKING INTERFACES
• Provides a 500 MHz HyperTransport
interface that supports 16 Gbps
aggregate bandwidth.
• Provides 3 Ethernet MAC or Generic
Packet Interfaces:
•Ethernet MAC interfaces support
standards-based TBI (1000 Mbps),
GMII (1000 Mbps) and MII (10/100
Mbps) interface modes.
•Generic Packet Interface supports
8-bit, 16-bit and 32-bit operation at
104 MHz using LVTTL I/O levels or
at 208 MHz using HSTL I/O levels.
•Dedicated multi-channel DMA for
Ethernet MAC/GPI interfaces.
• Provides a 200 MHz SysAD interface
for high bandwidth connections.
• Provides a 33 MHz Local Bus interface
for connectivity to boot-up and
configuration devices.
• Supports 16550-like DUART and 2BI.
ADDITIONAL FEATURES
• Provides 8 Kbytes integrated low
latency scratch RAM.
• Provides an integrated on-chip EJTAG
Debug module to ensure easy
debugging of hardware and software
and a Trace Buffer to allow tracing
instruction execution for debugging.
• Provides a flexible 4-channel DMA
control architecture providing DMA to
BLOCK DIAGRAM
y
DDR SDRAM
Controller
Packet Switch
Microprocessor
Interrupt
Controller
DUART/2BI
Local Bus
Controller
HyperTransport Bus
EJTAG
Debug
256 Kbyte
L2 Cache
256 Kbyte
L2 Cache
Processor Switch
8 Kbyte
Integrated
RAM
1 GHz
E9000 Processor
1 GHz
E9000 Processor
MII
GMII
TBI
FIFO
FIFO
FIFO
DMA
DMA
DMA
GE+
GE+
GE+
SysAD Bus
Controller
DMA
Controller
Timers
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
RM9220 Integrated Multiprocessor
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PMC-2021652 (P5)
© Copyright PMC-Sierra, Inc. 2003–2004.
All rights reserved.
For a complete list of PMC-Sierra’s
trademarks and registered trademarks,
visit: http://www.pmc-sierra.com/legal/
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL US
E
RM9220
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
any block, scatter/gather support, and
external DMA request support.
• Provides a vectored, prioritized
interrupt controller that supports:
•256 prioritized interrupts.
•Programmable interrupt delivery
modes, for inter-processor as well
as external and HyperTransport
interrupts.
• Provides 2 integrated Performance
Counters:
•Counts over 30 processor events.
•Enables full characterization and
analysis of application software.
•Provides 6 additional timers for
Watchdog and general purpose
timing for software.
• 672-pin FCBGA package, 27x27 mm.
THIRD PARTY SUPPORT
OPERATING SYSTEMS
• SMP Linux.
• VxWorks MP from Wind River.
EJTAG EMULATORS
•Wind River.
• Corelis.
EVALUATION BOARDS
• ATX Evaluation Board.
COMPANION CHIPS
• Wide range of companion chips
available to interface with SysAD and
HyperTransport.
APPLICATIONS
• Enterprise LAN Switches and Routers.
• Enterprise and Service Provider WAN
Switches and Routers.
• Multiservice Access Switches and
Routers.
• High-end Server Network Interface
Cards.
• Wireless Base Stations.
• Storage Networking.
•Security.
APPLICATIONS
RM9220
Multiprocessor
PCI or PCI-X
Bridge/Tunnel
Security
Co-Processor
SDRAM
4-port
HyperTransport
Switch
10/100/1000
Ethernet
Tranceivers
Gigabit Ethernet
Over Fiber Optics
POS-PHY Level 3
Components
Or FPGA
Or ASIC
System Controllers
Or FPGA
Or ASIC
HyperTransport
MII/GMII
TBI
GPI-8/16/32
SysAD
