MC74HC541AN - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

3–1 REV 1

 Motorola, Inc. 1995

10/95

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! "

 "

High–Performance Silicon–Gate CMOS

The MC54/74HC541A is identical in pinout to the LS541. The device

inputs are compatible with Standard CMOS outputs. External pullup

resistors make them compatible with LSTTL outputs.

The HC541A is an octal non–inverting buffer/line driver/line receiver

designed to be used with 3–state memory address drivers, clock drivers, and

other bus–oriented systems. This device features inputs and outputs on

opposite sides of the package and two ANDed active–low output enables.

The HC541A is similar in function to the HC540A, which has inverting

outputs.

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2 to 6V

•Low Input Current: 1µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements

•Chip Complexity: 134 FETs or 33.5 Equivalent Gates

18 Y1

17 Y2

16 Y3

15 Y4

14 Y5

13 Y6

12 Y7

11 Y8

OE1

OE2 1

Output

Enables

Data

Inputs Non–Inverting

Outputs

PIN 20 = VCC

PIN 10 = GND

LOGIC DIAGRAM

Pinout: 20–Lead Packages (Top View)

1920 18 17 16 15 14

21 34567

VCC

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND



FUNCTION TABLE

Inputs Output Y

OE1 OE2 A

Z = High Impedance

X = Don’t Care

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

MC54/74HC541A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 35

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 75

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP or SOIC Package

Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

Guaranteed Limit

Symbol Parameter Condition

VCC

–55 to 25°C≤85°C≤125°C Unit

VIH Minimum High–Level Input Voltage Vout = 0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low–Level Input Voltage Vout = VCC – 0.1V

|Iout| ≤ 20µA2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High–Level Output

Voltage Vin = VIL

|Iout| ≤ 20µA2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIL |Iout| ≤ 3.6mA

|Iout| ≤ 6.0mA

|Iout| ≤ 7.8mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low–Level Output

Voltage Vin = VIH

|Iout| ≤ 20µA2.0

4.5

6.0

0.1

Vin = VIH |Iout| ≤ 3.6mA

|Iout| ≤ 6.0mA

|Iout| ≤ 7.8mA

3.0

4.5

6.0

0.26

0.33

0.40

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC541A

High–Speed CMOS Logic Data

DL129 — Rev 6 3–3 MOTOROLA

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

VCC

Symbol Unit≤125°C≤85°C–55 to 25°C

VCC

ConditionParameter

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

IOZ Maximum Three–State Leakage

Current Output in High Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0 ±0.5 ±5.0 ±10.0 µA

ICC Maximum Quiescent Supply

Current (per Package) Vin = VCC or GND

Iout = 0µA6.0 4 40 160 µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

VCC

Guaranteed Limit

Symbol Parameter

VCC

–55 to 25°C≤85°C≤125°C Unit

tPLH,

tPHL Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3) 2.0

3.0

4.5

6.0

100

120

tPLZ,

tPHZ Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4) 2.0

3.0

4.5

6.0

110

140

165

tPZL,

tPZH Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4) 2.0

3.0

4.5

6.0

110

140

165

tTLH,

tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 3) 2.0

3.0

4.5

6.0

Cin Maximum Input Capacitance 10 10 10 pF

Cout Maximum Three–State Output Capacitance (Output in High

Impedance State) 15 15 15 pF

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Figure 1.

VCC

GND

INPUT A

OUTPUT Y

tPLH

OE1 or OE2 50%

VCC

GND

OUTPUT Y

tPZL

OUTPUT Y

tPZH

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

10%

90%

tPLZ

tPHZ

50%

tPHL

90%

50%

10%

tTLH

tTHL

Figure 2.

SWITCHING WAVEFORMS

90%

50%

10%

50%

MC54/74HC541A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–4

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

TEST CIRCUITS

Figure 3. Figure 4.

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT 1k

Ω

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ and tPZH.

PIN DESCRIPTIONS

INPUTS

A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,

9) — Data input pins. Data on these pins appear in non–in-

verted form on the corresponding Y outputs, when the out-

puts are enabled.

CONTROLS

OE1, OE2 (PINS 1, 19) — Output enables (active–low).

When a low voltage is applied to both of these pins, the out-

puts are enabled and the device functions as an non–invert-

ing buffer. When a high voltage is applied to either input, the

outputs assume the high impedance state.

OUTPUTS

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,

13, 12, 11) — Device outputs. Depending upon the state of

the output enable pins, these outputs are either non–invert-

ing outputs or high–impedance outputs.

VCC

To 7 Other

Buffers

LOGIC DETAIL

One of Eight

Buffers

INPUT A

OE1

OE2

OUTPUT Y

MC54/74HC541A

High–Speed CMOS Logic Data

DL129 — Rev 6 3–5 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE

POSITION AT SEATING PLANE, AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A23.88 25.15 0.940 0.990

B6.60 7.49 0.260 0.295

C3.81 5.08 0.150 0.200

D0.38 0.56 0.015 0.022

F1.40 1.65 0.055 0.065

G2.54 BSC 0.100 BSC

H0.51 1.27 0.020 0.050

J0.20 0.30 0.008 0.012

K3.18 4.06 0.125 0.160

L7.62 BSC 0.300 BSC

M0 15 0 15

N0.25 1.02 0.010 0.040

_ _ _ _

1 10

SEATING

PLANE

HGK

NJM

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

J20 PL

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A25.66 27.171.010 1.070

B6.10 6.600.240 0.260

C3.81 4.570.150 0.180

D0.39 0.550.015 0.022

G2.54 BSC0.100 BSC

J0.21 0.380.008 0.015

K2.80 3.550.110 0.140

L7.62 BSC0.300 BSC

M0 15 0 15

N0.51 1.010.020 0.040

_ __ _

E1.27 1.770.050 0.070

–A–

SEATING

PLANE

D20 PL

–T–

0.25 (0.010) T

F1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D DIMENSION

AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

0.010 (0.25) B S

D20X

0.010 (0.25)

P10X

18X K

–T–

SEATING

PLANE

RX 45

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A12.65 12.95 0.499 0.510

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.50 0.90 0.020 0.035

G1.27 BSC 0.050 BSC

J0.25 0.32 0.010 0.012

K0.10 0.25 0.004 0.009

M0 7 0 7

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

_ _ _ _

MC54/74HC541A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–6

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MC54/74HC541A/D

*MC54/74HC541A/D*

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