TOSHIBA TC74HCT 138AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HCT138AP, TC74HCT138AF, TC74HCT138AFN 3-TO-8 LINE DECODER (Note) The JEDEC SOP (FN) is not available in Japan. The TC74HCT138A is a high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high, G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static P (DIP16-P-300-2.54A) Weight : 1.00g (Typ.) aT 16 Sr Pern acer YE 1 1 F (SOP16-P-300-1.27) FN (SOL16-P-150-1.27) Weight : 0.189 (Typ.) Weight : 0.13g (Typ.) GTA PIN ASSIGNMENT discharge or transient excess voltage. A 1 o VS 7 16 Vee FEATURES: B20 [] 15 Yo High Speed: see eeneesaneneeensesenessnsesasenees tod = 17ns(typ.) at Veco =5V Cc 3 L 7] 14 Y1 e Low Power Dissipation -:++++++++++++ loc = 4eA(Max.) at Ta = 25C Ga 40 13 2 e Compatible with TTL outputs +: Vy =2V(Min.) = ~ Vi. = 0.8V(Max.) G2B 5 [I f] 12 3 Wide interfacing abilty +--+ LSTTL, NMOS, CMOS G1 67 f] 11 4 Output Drive Capability ------------ 10 LSTTL Loads Y7 7 L P] 10 Y5 Symmetrical Output Impedance---| lox | = lot = 4mA(Min.) GND 8 J Alo Ye Balanced Propagation Delays--- toLH=tpHL e Pin andFunction Compatible with 74LS138 (TOP VIEW) IEC LOGIC SYMBOL BIN / OCT 1 0 0 2 1 1 2 2 3 3 4 4 5 5 6 6 7 7 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. 1997-08-07 1/6TOSHIBA TC74HCT 138AP/AF/AFN TRUTH TABLE INPUTS OUTPUTS ENABLE SELECT ~ = _ = SELECTED OUTPUT = = yo | Y1 | Y2 | Y3 | Y4/ Y5 | Y6 | Y7 G1 |G2A|G2B] C B A L|xf{txfxfxif{x?Hy?H{uHfHifaHofuHfutfa NONE x {Hx x] xf{x Hf af Ht Hf] aH] ATHY NONE x |x fH{|x {xx Pao alaf af af af ala NONE Hfe>e~P ey? eye fel ula f Hf aHf[aH fafa YO H/e]e{ei{>e{urefuoteteflarof Hf aot afudfa Y1 H/ ec] ef e{~uo{tefueit of elu af afudfa Y2 HH? te} e] ey? aH] AH] HATH tl af aA aA a 3 H/ec]ef{~H{ ef] efuret of Hf aH eft afaudfa Y4 HH? te; eT AHP LT AHP AT ATA aA aA [eT aA A Y5 HH? te; eT HP AH] tty aH {ATH {AHA [A [ea Y6 H/|t]|t{]H{|H|H{HH{|H{ HH] H{HO{L Y7 X : Don't Care LOGIC DIAGRAM 5 SELECT DATA INPUTS OUTPUTS ENABLE J INPUTS 961001EBA2 @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-08-07 2/6TOSHIBA TC74HCT 138AP/AF/AFN ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT *500mW in the range of Ta= Supply Voltage Range Vec 0.5~7 Vv 40C~65C. From Ta =65C 05~ to 85C a derating factor of DC Input Voltage Vin 0.5~Vec + 0.5 V 10mW/C shall be applied DC Output Voltage Vout 0.5~Vec + 0.5 Vv until 300mW. Input Diode Current li +20 mA Output Diode Current lox +20 mA Dc Output Current lout +25 mA DC Vec /Ground Current lee +50 mA Power Dissipation Pp 500 (DIP)* / 180 (SOP) mw Storage Temperature Tstg 65~150 C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vec 4.5~5.5 Vv Input Voltage Vin O~Vec Vv Output Voltage Vout O~Vec Vv Operating Temperature Topr 40~85 a @ Input Rise and Fall Time tr, te 0~500 ns DC ELECTRICAL CHARACTERISTICS Ta =25C Ta = -40~85C PARAMETER SYMBOL TEST CONDITION Vec UNIT (Vv) | MIN. | TYP. | MAX.) MIN. | MAX. : 4.5 High - Level _ _ _ Input Voltage Vin 55 2.0 2.0 Vv 4.5 Low - Level _ _ _ Input Voltage Vit 55 0.8 0.8 Vv High - Level V Vin= ln =20eA | 45] 44 | 45 | 44 - V Output Voltage OP Maori. ligge4ma 1 45| 418 | 4317 [413] Low - Level V Vin= lo. = 20 LA 4.5 _ 0.0 0.1 _ 0.1 Vv Output Voltage Sl} MworMii igpe4 mA 45| |o17 | 026] | 0.33 Input Leakage Current lin Vin =Vec or GND 5.5 _ _ +0.1 _ +1.0 A _ _ _ _ L Quiescent Supply PER weave ve 2.4V - = = Current ?Vin = U.oV OF 2. _ _ _ lc | OTHER INPUT:Vcc or GND 3.5 2.0 2.9 | mA 1997-08-07 3/6TOSHIBA TC74HCT 138AP/AF/AFN AC ELECTRICAL CHARACTERISTICS ( C, = 15pF, Vcc =5V, Ta= 25C, Input t,=t;=6ns ) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT t Output Transition Time L. _ 4 8 THL Propagation Delay Time toy _ 17 28 (A, B, CY) toHL ns Propagation Delay Time toy _ 15 25 (G1i-Y) tou Propagation Delay Time toy _ 17 28 (G2-Y) tone AC ELECTRICAL CHARACTERISTICS ( C, = 50pF, Input t, = t;=6ns) Ta=25C Ta = 40~85C PARAMETER SYMBOL | TEST CONDITION Vec(W)| MIN. | TYP. |MAX.| MIN. | MAX. UNIT a: : tty 4.5 _ 8 15 _ 19 Output Transition Time tru 55 _ 7 14 _ 18 Propagation Delay Time toLH 4.5 _ 21 33 _ 44 (A, B, CY) tout 5.5 18 30 40 ns Propagation Delay Time tou 4.5 - 19 30 - 38 (G1-Y) tpHL 5.5 - 17 27 - 34 Propagation Delay Time toi 4.5 _ 22 33 _ 41 (G2-Y) tox 5.5 _ 20 30 37 Input Capacitance Cin _ 5 10 _ 10 F Power Dissipation Capacitance | Cpp (1) _ 55 P Note (1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without lead. Average operating current can be obtained by the equation: Icc (Opr) =Cpp * Vc * fin + lec 1997-08-07 4/6TOSHIBA TC74HCT 138AP/AF/AFN DIP 16PIN OUTLINE DRAWING (DIP16-P-300-2.54A) Unit in mm os =f h 6.420.2 7.62 L U U L L {| [| 19.75MAX 19,.25%0.2 0.95+0.1 | rn oe 0.51 MIN [esi0 2 4.1540.3 3.310.3 O.735TYP | 0.5+0.1 10.25 0.25 Gi Weight : 1.00g (Typ.) SOP 16PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300-1.27) Unit in mm .34+0.2 7.840.3 7.62 {300mil) HEHEHE 4 0.705TYP Fl | 1.27 10.8MAX 10.310.2 Toto 710.1] 0.157845 0.810.2 Weight : 0.18g (Typ.) 1997-08-07 5/6TOSHIBA SOP 16PIN (150mil BODY) OUTLINE DRAWING (SOL16-P-150 -1.27) TC74HCT 138AP/AF/AFN Unit in mm Weight : 0.13g (Typ.) O0.505TYP 16 9 BHHHHHRAH 3.920.1 1 & 1 6.0+0.2 ink | 8 9.90.1 ot 0.42+0.07 (10.25 1.375+40.2 0.1] 0.17540.075 1.75MAX (Note) This package is not available in Japan. 0.15%: 1997-08-07 6/6