© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 6
1Publication Order Number:
MC10EL51/D
MC10EL51, MC100EL51
5VECL Differential Clock D
Flip-Flop
Description
The MC10EL/100EL51 is a differential clock D flip-flop with reset.
The device is functionally similar to the E151 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E151 the EL51 is ideally
suited for those applications which require the ultimate in AC
performance.
The reset input is an asynchronous, level triggered signal. Data
enters the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition
of the clock. The differential clock inputs of the EL51 allow the device
to be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input (pulled down to VEE) conditions.
The 100 Series contains temperature compensation.
Features
•475 ps Propagation Delay
•2.8 GHz Toggle Frequency
•ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
•PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
•Internal Input Pulldown Resistors on D, R, and CLK
•Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
•Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
•Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
•Transistor Count = 73 devices
•Pb−Free Packages are Available *For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KL51
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
KEL51
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
2M M G
G
14
4X M G
G
14
HL51
ALYWG
G
1
8
HEL51
ALYW
G
1
8
(Note: Microdot may be in either location)
H = MC10
K = MC100
4X = MC10
2M= MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M= Date Code
G= Pb−Free Package
MC10EL51, MC100EL51
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2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. Logic Diagram and Pinout Assignment
D
Q
CLK
CLK
R
D
R
Table 1. TRUTH TABLE
D*
L
H
X
R*
L
L
H
CLK*
Z
Z
X
Q**
L
H
L
Z = LOW to HIGH Transition
R ECL Reset Input
D ECL Data Input
CLK, CLK ECL Clock Inputs
Q, Q ECL Data Outputs
VCC Positive Supply
VEE Negative Supply
Table 2. PIN DESCRIPTION
* Pin will default low when left open.
**Pin will default low when inputs are left open.
PIN FUNCTION
EP Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 8 V
VEE NECL Mode Power Supply VCC = 0 V −8 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
−6
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 ± 5% °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol Wave Solder Pb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
MC10EL51, MC100EL51
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3
Table 4. 10EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 1)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 29 24 29 24 29 mA
VOH Output HIGH Voltage (Note 5) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV
VOL Output LOW Voltage (Note 2) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV
VIH Input HIGH Voltage (Single−Ended) 3770 4110 3870 4190 3940 4280 mV
VIL Input LOW Voltage (Single−Ended) 3050 3500 3050 3520 3050 3555 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
2.5 4.6 2.5 4.6 2.5 4.6 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.3 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 5. 10EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 4)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 29 24 29 24 29 mA
VOH Output HIGH Voltage (Note 5) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV
VOL Output LOW Voltage (Note 5) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV
VIH Input HIGH Voltage (Single−Ended) −1230 −890 −1130 −810 −1060 −720 mV
VIL Input LOW Voltage (Single−Ended) −1950 −1500 −1950 −1480 −1950 −1445 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
−2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.3 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
MC10EL51, MC100EL51
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4
Table 6. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 7)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 29 24 29 30 36 mA
VOH Output HIGH Voltage (Note 8) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV
VOL Output LOW Voltage (Note 8) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV
VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV
VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
2.5 4.6 2.5 4.6 2.5 4.6 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 7. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 10)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 29 24 29 30 36 mA
VOH Output HIGH Voltage (Note 11) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
VOL Output LOW Voltage (Note 11) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV
VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
−2.5 −0.4 −2.5 −0.4 −2.5 −0.4 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
11. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
12. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
MC10EL51, MC100EL51
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5
Table 8. AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −5.0 V (Note 13)
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fmax Maximum Toggle Frequency 1.8 2.8 2.2 2.8 2.2 2.8 GHz
tPLH
tPHL
Propagation Delay
to Output CLK
R
325
305
465
455
605
605
385
355
475
465
565
565
440
410
530
510
620
620
ps
tSSetup Time 150 0 150 0 150 0 ps
tHHold Time 250 100 250 100 250 100 ps
tRR Reset Recovery 400 200 400 200 400 200 ps
tPW Minimum Pulse Width
CLK, Reset
400 400 400 ps
VPP Input Swing (Note 14) 150 1000 150 1000 150 1000 mV
tJITTER Cycle−to−Cycle Jitter TBD TBD TBD ps
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
100 225 350 100 225 350 100 225 350 ps
13.10 Series: VEE can vary +0.25 V / −0.5 V.
100 Series: VEE can vary +0.8 V / −0.5 V.
14.VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
MC10EL51, MC100EL51
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6
ORDERING INFORMATION
Device Package Shipping†
MC10EL51D SOIC−898 Units / Rail
MC10EL51DG SOIC−8
(Pb−Free)
98 Units / Rail
MC10EL51DR2 SOIC−82500 / Tape & Reel
MC10EL51DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC10EL51DT TSSOP−8100 Units / Rail
MC10EL51DTG TSSOP−8
(Pb−Free)
100 Units / Rail
MC10EL51DTR2 TSSOP−82500 / Tape & Reel
MC10EL51DTR2G TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC10EL51MNR4 DFN8 1000 / Tape & Reel
MC10EL51MNR4G DFN8
(Pb−Free)
1000 / Tape & Reel
MC100EL51D SOIC−898 Units / Rail
MC100EL51DG SOIC−8
(Pb−Free)
98 Units / Rail
MC100EL51DR2 SOIC−82500 / Tape & Reel
MC100EL51DR2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EL51DT TSSOP−8100 Units / Rail
MC100EL51DTG TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EL51DTR2 TSSOP−82500 / Tape & Reel
MC100EL51DTR2G TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EL51MNR4 DFN8 1000 / Tape & Reel
MC100EL51MNR4G DFN8
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D −ECL Clock Distribution Techniques
AN1406/D −Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D −Metastability and the ECLinPS Family
AN1568/D −Interfacing Between LVDS and ECL
AN1672/D −The ECL Translator Guide
AND8001/D −Odd Number Counters Design
AND8002/D −Marking and Date Codes
AND8020/D −Termination of ECL Logic Devices
AND8066/D −Interfacing with ECLinPS
AND8090/D −AC Characteristics of ECL Devices
MC10EL51, MC100EL51
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7
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC10EL51, MC100EL51
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8
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
MC10EL51, MC100EL51
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9
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
A
D
E
B
C0.10
PIN ONE
2 X
REFERENCE
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
8 X
A1
SEATING
PLANE
e/2 e
8 X
K
NOTE 3
b
8 X 0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K0.20 −−−
L0.25 0.35
14
85
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC10EL51/D
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