PRELIMINARY ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR GENERAL DESCRIPTION Features The ICS871002I-02 is a high performance Jitter ICS Attenuator designed for use in PCI ExpressTM HiPerClockSTM systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS871002I-02 has two PLL bandwidth modes: 350kHz and 2000kHz. The 350kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 2000kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The ICS871002I-02 can be set for different modes using the F_SELx pins as shown in Table 3C. * Two 0.7V differential output pairs rd * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 640MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 20ps (typical) * 3.3V operating supply * Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages TM The ICS871002I-02 uses IDT 3 Generation FemtoClock PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL BANDWIDTH BW_SEL 0 = PLL Bandwidth: ~350kHz (default) 1 = PLL Bandwidth: ~2000kHz PIN ASSIGNMENT BLOCK DIAGRAM IREF OE + Pullup F_SEL[1:0] Pullup:Pulldown 2 BW_SEL Pulldown 0 = 350kHz 1 = 2000kHz CLK Pulldown nCLK Pullup Phase Detector VCO Output Divider 00 /5 01 /4 10 /2 (default) 11 /1 Q0 nQ0 nQ0 IREF FB_OUT nFB_OUT MR BW_SEL F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 VDD Q1 nQ1 nFB_IN FB_IN GND nCLK CLK OE ICS871002I-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body 98 - 640 MHz Q1 G Package Top View nQ1 FB_IN Pulldown nFB_IN Pullup /5 (fixed) FB_OUT nFB_OUT MR Pulldown The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 1 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 20 nQ0, Q0 Output 2 IREF Input 3, 4 FB_OUT, nFB_OUT Output 5 MR Input 6 BW_SEL Input 7, 9 8 F_SEL1, F_SEL0 VDDA Power 10, 19 VDD Power 11 OE Input 12 CLK Input 13 nCLK Input 14 GND Power 15 FB_IN Input Input 16 nFB_IN Input 17, 18 nQ1, Q1 Output Description Differential output pair. HCSL interface levels. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode Qx/nQx clock outputs. Differential feedback output pair. HCSL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB_OUT) to go low and the inver ted Pulldown outputs (nQx, nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bandwidth select input. 0 = 350kHz, 1 = 2000kHz. Pulldown See Table 3B. Pullup, Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3C. Pulldown Analog supply pin. Core supply pin. Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pullup See Table 3A. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Pulldown Non-inver ting differential feedback input. Pullup Inver ting differential feedback input. Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Typical Maximum Units TABLE 3B. PLL BANDWIDTH CONTROL TABLE TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Input OE 0 1 Minimum Outputs Q[1:0]/nQ[1:0] FB_OUT/nFB_OUT HiZ Enabled Enabled Enabled Input BW_SEL 0 PLL Bandwidth 350kHz (default) 1 2000kHz TABLE 3C. F_SELX FUNCTION TABLE Inputs Input Frequency (MHz) 100 F_SEL1 0 F_SEL0 0 Divider 5 Output Frequency (MHz) 100 100 0 1 4 125 100 1 0 2 250 (default) 100 1 1 1 50 0 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 2 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 86.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.97 3.3 3.63 V VDD - 0.13 3.3 VDD VDDA Analog Supply Voltage IDD Power Supply Current 75 mA IDDA Analog Supply Current 13 mA V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current F_SEL1, OE F_SEL0, MR, BW_SEL Test Conditions Minimum VDD = 3.63V VDD = 3.63V Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 A VDD = VIN = 3.63V VDD = VIN = 3.63 150 A F_SEL1, OE VDD = 3.63V, VIN = 0V -150 A F_SEL0, MR, BW_SEL VDD = 3.63V, VIN = 0V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical CLK, VDD = VIN = 3.63V FB_IN Input High Current IIH nCLK, 5 VDD = VIN = 3.63V nFB_IN CLK, VDD = VIN = 63V FB_IN Input Low Current IIL nCLK, -150 VDD = VIN = 3.63V nFB_IN VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 3 Maximum Units 150 A A 150 A A 1.3 V VDD - 0.85 V ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 5. AC CHARACTERISTICS, VDD = 3.3V10%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum fMAX Output Frequency t jit(cc) Cycle-to-Cycle Jitter ; NOTE 1 VHIGH Voltage High 660 VLOW Voltage Low -150 VOVS Max. Voltage, Overshoot VUDS Min. Voltage, Undershoot Vrb Ringback Voltage VCROSS Absolute Crossing Voltage VCROSS Total Variation of VCROSS over all edges tR / tF Output Rise/Fall Time tR /tF Rise/Fall Time Variation tRFM Rise/Fall Matching odc Output Duty Cycle Typical 98 PLL Mode Maximum Units 640 MHz 850 mV 20 ps mV VHIGH + 0.3 -0.3 250 measured between 0.175V to 0.525V 175 45 V V 0.2 V 550 mV 140 mV 700 ps 125 ps 125 ps 55 % NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 4 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION 100 33 VDD Measurement Point VDDA 49.9 HCSL 100 33 GND nCLK, nFB_IN 2pF V Measurement Point 49.9 2pF 475 CMR GND 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT nQ0, nQ1, nFB_OUT Q0, Q1, FB_OUT V Cross Points PP CLK, FB_IN DIFFERENTIAL INPUT LEVEL nQ0, nQ1, nFB_OUT t PW odc = Q0, Q1, FB_OUT PERIOD t PW t x 100% tcycle n+1 tjit(cc) = tcycle n - tcycle n+1 1000 Cycles t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 0.525V tcycle n VDD CYCLE-TO-CYCLE JITTER 0.525V VSW I N G Clock 0.175V Outputs 0.175V tR tF OUTPUT RISE/FALL TIME IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 5 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS871002I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. DIFFERENTIAL OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 6 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50 R4 120 Zo = 60 CLK CLK Zo = 50 Zo = 60 nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional - R3 and R4 can be 0 FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 7 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY RECOMMENDED TERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50U impedance. FIGURE 4A. RECOMMENDED TERMINATION Figure 4B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50U impedance. FIGURE 4B. RECOMMENDED TERMINATION IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 8 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS871002I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS871002I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (75mA + 15mA) = 326.7mW Power (outputs)MAX = 47.75mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 47.75mW = 95.5mW Total Power_MAX (3.63V, with all outputs switching) = 326.7mW + 95.5mW = 422.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.422W * 86.7C/W = 121C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 0 1 2.5 86.7C/W 82.4C/W 80.2C/W 9 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. VDDO VOUT RL 50 IC FIGURE 5. HCSL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. DD Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V /R ) * (V OH_MAX Pd_L = (V L -V DD_MAX ) OH_MAX /R ) * V OL_MIN L OL_MIN Pd_H = (0.85V /50) * (3.63V - 0.85V) = 47.3mW Pd_L = (0.15V/50) * 0.15V = 0.45mW Total Power Dissipation per output pair = Pd_H + Pd_L = 47.75mW IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 10 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 86.7C/W 82.4C/W 80.2C/W TRANSISTOR COUNT The transistor count for ICS871002I-02 is: 1704 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 11 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 12 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS871002AGI-02 ICS71001I-02 20 Lead TSSOP tube -40C to 85C ICS871002AGI-02T ICS71001I-02 20 Lead TSSOP 2500 tape & reel -40C to 85C ICS871002AGI-02LF TBD 20 Lead "Lead-Free" TSSOP Tray -40C to 85C ICS871002AGI-02LFT TBD 20 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM 0.7V DIFFERENTIAL JITTER ATTUNUATOR 13 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007 ICS871002I-02 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSTM JITTER ATTENUATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. 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