DIFFERENTIAL-TO-0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS871002I-02
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 1 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS871002I-02 is a high performance Jitter
Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express
clocks are generated from a low bandwidth, high
phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS871002I-02 has two PLL bandwidth modes: 350kHz and
2000kHz. The 350kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 2000kHz bandwidth provides the best
tracking skew and will pass most spread profiles, but the jitter
attenuation will not be as good as the lower bandwidth modes.
The ICS871002I-02 can be set for different modes using the
F_SELx pins as shown in Table 3C.
The ICS871002I-02 uses IDT 3rd Generation FemtoClockTM PLL
technology to achieve the lowest possible phase noise. The
device is packaged in a small 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
Features
•Two 0.7V differential output pairs
•One differential clock input
•CLK and nCLK supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
•Output frequency range: 98MHz - 640MHz
•Input frequency range: 98MHz - 128MHz
•VCO range: 490MHz - 640MHz
•Cycle-to-cycle jitter: 20ps (typical)
•3.3V operating supply
•Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: ~350kHz (default)
1 = PLL Bandwidth: ~2000kHz
PLL BANDWIDTH
÷5 (fixed)
VCO
98 - 640 MHz
Phase
Detector
Output Divider
00 ÷5
01 ÷4
10 ÷2 (default)
11 ÷1
Q0
nQ0
Q1
nQ1
FB_OUT
nFB_OUT
BW_SEL
CLK
nCLK
FB_IN
nFB_IN
F_SEL[1:0]
MR
OE
Pulldown
Pullup:Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pullup
Pulldown
2
-
+
IREF
0 = 350kHz
1 = 2000kHz
PIN ASSIGNMENT
ICS871002I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nQ0
IREF
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
VDDA
F_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
VDD
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 2 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH CONTROL TABLE
tupnI
htdiwdnaBLLPLES_WB
0)tluafed(zHk053
1zHk0002
TABLE 3C. F_SELX FUNCTION TABLE
ycneuqerFtupnI
)zHM(
stupnI ycneuqerFtuptuO
)zHM(1LES_F0LES_FrediviD
001005 001
001014 521
001102 )tluafed(052
001111 005
tupnIstuptuO
EO]0:1[Qn/]0:1[QTUO_BFn/TUO_BF
0ZiHdelbanE
1delbanEdelbanE
rebmuNemaNepyTnoitpircseD
02,10Q,0QntuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
2FERItupnI 574(rotsisernoi
sicerpdexifA Ωasedivorpdnuorgotnipsihtmorf)
.stuptuokcolcxQn/xQedom-tnerruclaitnereffidrofdesutnerrucec
nerefer
,3
4
,TUO_BF
TUO_BFn tuptuO .slevelecafretniLSCH.riaptuptuokcabdeeflaitnereffiD
5RMtupnInwodlluP
erasred
ividlanretnieht,HGIHcigolnehW.teseRretsaMHGIHevitcA
detrevniehtdnawologot)TUO_BF,xQ(stuptuoeurtehtgnisuacteser
sredividlanretnieht,WOLcigolnehW.hgihogot)TUO_BFn,xQn(stuptuo
.slevelecafretniLTTVL/SOMCVL.del
baneerastuptuoehtdna
6LES_WBtupnInwodlluP .zHk0002=1,zHk053=0.tupnitceleshtdiwdnaBLLP
.B3elbaTeeS
,7
9
,1LES_F
0LES_F tupnI ,pulluP
nwodlluP .C3elbaTeeS.slevelecafretniLTTVL/SOMCVL.sniptcelesycneuqerF
8V
ADD
rewoP.nipylppusgolanA
91,01V
DD
rewoP.nipylppuseroC
11EOtupnIpulluP
eht,WOLnehW.evitcaerastuptuoeht,HGIHnehW.nipelbanetuptuO
.slevelecafretn
iLTTVL/SOMCVL.etatsecnadepmihgihanierastuptuo
.A3elbaTeeS
21KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevn
i-noN
31KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
41DNGrewoP.dnuorgylppusrewoP
51NI_BFtupnInwodlluP.tupnikcab
deeflaitnereffidgnitrevni-noN
61NI_BFntupnIpulluP.tupnikcabdeeflaitnereffidgnitrevnI
81,711Q,1QntuptuO.slevele
cafretniLSCH.riaptuptuolaitnereffiD
:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTe
eS.srotsisertupnilanretniotrefer
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 3 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 86.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Character istics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 79.23.336.3V
V
ADD
egatloVylppuSgolanAV
DD
31.0–3.3V
DD
V
I
DD
tnerruCylppuSrewoP 57Am
I
ADD
tnerruCylppuSgolanA 31Am
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIV
DD
V36.3=2V
DD
3.0+V
V
LI
egatloVwoLtupnIV
DD
V36.3=3.0-8.0V
I
HI
tupnI
tnerruChgiH
EO,1LES_FV
DD
V=
NI
V36.3=5Aµ
LES_WB,RM,0LES_FV
DD
V=
NI
36.3=051Aµ
I
LI
tupnI
tnerruCwoL
EO,1LES_FV
DD
V,V36.3=
NI
V0=051-Aµ
LES_WB,RM,0LES_FV
DD
V,V36.3=
NI
V0=5-Aµ
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI
,KLC
NI_BF V
DD
V=
NI
V36.3=051Aµ
,KLCn
NI_BFn V
DD
V=
NI
V36.3=5 Aµ
I
LI
tnerruCwoLtupnI
,KLC
NI_BF V
DD
V=
NI
V36=051Aµ
,KLCn
NI_BFn V
DD
V=
NI
V36.3=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON 5.0+DNGV
DD
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 4 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 89046zHM
t)cc(tij1ETON;rettiJelcyC-ot-elcyCedoMLLP02sp
V
HGIH
hgiHegatloV 066058Vm
V
WOL
woLegatloV 051-Vm
V
SVO
toohsrevO,egatloV.xaM V
HGIH
3.0+V
V
SDU
toohsrednU,egatloV.niM 3.0-V
V
br
egatloVkcabgniR 2.0V
V
SSORC
egatloVgnissorCetulosbA 052055Vm
ΔV
SSORC
VfonoitairaVlatoT
SSORC
segdellarevo 041Vm
t
R
t/
F
emiTllaF/esiRtuptuO neewtebderusaem
V525.0otV571.0 571007sp
Δt
R
/Δt
F
noitairaVemiTllaF/esiR 521sp
t
MFR
gnihctaMllaF/esiR 521sp
cdoelcyCytuDtuptuO 5455%
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:1ETON
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 5 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
DIFFERENTIAL INPUT LEVEL3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
V
CMR
Cross Points
V
PP
GND
CLK,
FB_IN
nCLK,
nFB_IN
VDD
Clock
Outputs 0.175V
0.525V 0.525V
0.175V
tRtF
VSWING
nQ0, nQ1,
nFB_OUT
➤
➤
➤
➤
tcycle n tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
OUTPUT RISE/FALL TIME
Q0, Q1,
FB_OUT
nQ0, nQ1,
nFB_OUT
475Ω
Measurement
Point
33Ω100Ω
100Ω
33Ω
Measurement
Point
49.9Ω
49.9Ω
HCSL
GND
2pF
2pF
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
Q0, Q1,
FB_OUT
VDD
VDDA
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 6 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS871002I-02 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD and VDDA should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, power supply isolation is required.
Figure 1 illustrates how a 10Ω resistor along with a 10μF and a
0.01μF bypass capacitor should be connected to each VDDA pin.
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
DIFFERENTIAL OUTPUTS
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 7 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
HCSL
*R3 33
*R4 33
CLK
nCLK
2.5V 3.3V
Zo = 50Ω
Zo = 50Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 8 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
RECOMMENDED T ERMINATION
Figure 4A is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ù impedance.
FIGURE 4A. RECOMMENDED TERMINATION
Figure 4B is the recommended termination for applications
which require a point to point connection and contain the driver
FIGURE 4B. RECOMMENDED TERMINATION
and receiver on the same PCB. All traces should all be 50Ù
impedance.
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 9 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS871002I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS871002I-02 is the sum of the core power plus the analog power plus the power dissipated in
the load(s).
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (75mA + 15mA) = 326.7mW
•Power (outputs)MAX = 47.75mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 47.75mW = 95.5mW
Total Power_MAX (3.63V, with all outputs switching) = 326.7mW + 95.5mW = 422.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.422W * 86.7°C/W = 121°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 10 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
DD
– 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
– V
OH_MAX
)
Pd_L = (V
OL_MIN
/R
L
) * V
OL_MIN
Pd_H = (0.85V
/50Ω) * (3.63V – 0.85V) = 47.3mW
Pd_L = (0.15V/50Ω) * 0.15V = 0.45mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 47.75mW
FIGURE 5. HCSL DRIVER CIRCUIT AND TERMINATION
IC
VOUT
RL
50
VDDO
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 11 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS871002I-02 is: 1704
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 86.7°C/W 82.4°C/W 80.2°C/W
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 12 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
LOBMYS sretemilliM
NIMXAM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°
0°8
aaa--01.0
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 13 ICS871002AGI-02 REV. A SEPTEMBER 14, 2007
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 9. ORDERING INFORMATION
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20-IGA200178SCI20-I10017SCIPOSSTdaeL02ebutC°58otC°0
4-
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Innovate with IDT and accelerate your future networks. Contact:
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800-345-7015
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Corporate Headquarters
Integrated Device Technology, Inc.
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800 345 7015
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Integrated Device Technology
Singapore (1997) Pte. Ltd.
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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS871002I-02
DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY
