APW7085 2A, 26V, 380kHz, Asynchronous Step-Down Converter General Description Features * * * The APW7085 is a 2A, asynchronous, step-down converter with integrated 100m P-channel MOSFET. The device, with current-mode control scheme, can convert 4.5~26V input voltage to the output voltage adjustable from 0.8 to 90% VIN to provide excellent output voltage regulation. Wide Input Voltage from 4.5V to 26V Output Current up to 2A Adjustable Output Voltage from 0.8V to 90%VIN - 0.8V Reference Voltage - 2.5% System Accuracy * * The APW7085 regulates the output voltage in automatic PSM/PWM mode operation, depending on the output current, for high efficiency operation over light to full load current. The APW7085 is also equipped with power-onreset, soft-start, and whole protections (undervoltage, over- temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 5A. 100m Integrated P-Channel Power MOSFET High Efficiency up to 91% - Pulse-Skipping Mode (PSM) / PWM Mode Operation * Current-Mode Operation - Stable with Ceramic Output Capacitors - Fast Transient Response * * * * Power-On-Reset Monitoring This device, available in an 8-pin SOP-8 package, provides a very compact system solution with minimal external components. Fixed 380kHz Switching Frequency in PWM Mode Built-in Digital Soft-Start Output Current-Limit Protection with Frequency Foldback * * * * * 100 90 70% Undervoltage Protection Efficiency (%) Over-Temperature Protection <5A Quiescent Current during Shutdown SOP-8 Package Lead Free and Green Devices Available (RoHS Compliant) C1 10F VIN U1 APW7085 R1 1% C6 C5 GND 0.01 0.1 1 Output Current, IOUT (A) 10 Applications * * * * * * * VOUT +3.3V D1 EN R4 40 0 0.001 L1 2A UGND COMP 50 10 +12V LX VIN VOUT=3.3V 60 20 C2 VIN C3 70 30 Simplified Application Circuit VCC VOUT=5V 80 C4 22F FB R2 1% C7 (Optional) LCD Monitor / TV Set-Top Box Portable DVD Wireless LAN ADSL, Switch HUB Notebook Computer Step-down Converters Requiring High Efficiency and 2A Output Current ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 1 www.anpec.com.tw APW7085 Ordering and Marking Information Package Code K : SOP-8 Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7085 Assembly Material Handling Code Temperature Range Package Code APW7085 XXXXX APW7085 K : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration VIN EN UGND VCC 1 8 2 7 3 6 4 5 GND FB COMP LX SOP-8 Top View Absolute Maximum Ratings Symbol VIN (Note 1) Parameter VIN Supply Voltage (VIN to GND) VLX LX to GND Voltage VCC VCC Supply Voltage (VCC to GND) Rating Unit -0.3 ~ 30 V > 100ns -2 ~ VIN+0.3 < 100ns -5 ~ VIN+6 VIN > 6.2V -0.3 ~ 6.5 VIN 6.2V < VIN+0.3 V V VUGND_GND UGND to GND Voltage -0.3 ~ VIN+0.3 V VVIN_UGND VIN to UGND Voltage -0.3 ~ 6.5V V EN to GND Voltage 20 FB, COMP to GND Voltage V -0.3 ~ VCC +0.3 Maximum Junction Temperature V C 150 TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds C -65 ~ 150 C 260 Note 1: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. Thermal Characteristics Symbol JA Parameter Typical Value Junction-to-Ambient Resistance in free air (Note 2) Unit o SOP-8 80 C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 2 www.anpec.com.tw APW7085 Recommended Operating Conditions (Note 3) Symbol VIN Parameter VIN Supply Voltage Range Unit 4.5 ~ 26 V VCC Supply Voltage 4.0 ~ 5.5 V VOUT Converter Output Voltage 0.8 ~ 90% VIN V IOUT Converter Output Current TA TJ 0~2 A VCC Input Capacitor 0.22 ~ 2.2 F VIN-to-UGND Input Capacitor 0.22 ~ 2.2 F Ambient Temperature Junction Temperature -40 ~ 85 o -40 ~ 125 o C C Note 3: Refer to the typical application circuits Electrical Characteristics Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7085 Min Typ Max 1.0 2.0 Unit SUPPLY CURRENT IVIN IVIN_SD IVCC IVCC_SD VIN Supply Current VFB = 0.85V, VEN=3V, LX=Open - mA VIN Shutdown Supply Current VEN = 0V, VIN=26V - - 5 A VCC Supply Current VEN = 3V, VCC = 5.0V, VFB=0.85V - 0.7 - mA VCC Shutdown Supply Current VEN = 0V, VCC = 5.0V - - 1 A VCC 4.2V LINEAR REGULATOR Output Voltage VIN = 5.2 ~ 26V, IO = 0 ~ 8mA 4.0 4.2 4.5 V Load Regulation IO = 0 ~ 8mA -60 -40 0 mV Current-Limit VCC > POR Threshold 8 - 30 mA VIN = 6.2 ~ 26V, IO = 0 ~ 10mA 5.3 5.5 5.7 V Load Regulation IO = 0 ~ 10mA -80 -60 0 mV Current-Limit VIN = 6.2 ~ 26V 10 - 30 mA 3.7 3.9 4.1 V - 0.15 - V 2.3 2.5 2.7 V - 0.2 - V - 3.5 - V - 0.2 - V V VIN-to-UGND 5.5V LINEAR REGULATOR Output Voltage (VVIN-UGND) POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS VCC POR Voltage Threshold VCC rising VCC POR Hysteresis EN Lockout Voltage Threshold VEN rising EN Lockout Hysteresis VIN-to-UGND Lockout Voltage Threshold VVIN-UGND rising VIN-to-UGND Lockout Hysteresis REFERENCE VOLTAGE VREF Reference Voltage Output Voltage Accuracy - 0.8 - TJ = 25oC, IOUT=0A, VIN=12V -1.0 - +1.0 TJ = -40 ~ 125oC, IOUT = 0 ~ 2A, VIN = 4.5 ~ 26V -2.5 - +2.5 % Line Regulation VIN = 4.5V to 26V, IOUT = 0A - 0.36 - % Load Regulation IOUT = 0 ~ 2A - 0.4 - % Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 3 www.anpec.com.tw APW7085 Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC. Symbol Parameter Test Conditions APW7085 Unit Min Typ Max 340 380 420 kHz - 80 - kHz - 93 - % - 200 - ns - 400 - A/V OSCILLATOR and DUTY FOSC Free Running Frequency VIN = 4.5 ~ 26V Foldback Frequency VFB = 0V Maximum Converter's Duty Cycle Minimum Pulse Width of LX VIN = 4.5 ~ 26V CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain COMP = Open 60 80 - dB - 0.2 - TJ=25oC - 100 140 m Current-Sense Resistance P-Channel Power MOSFET Resistance PROTECTIONS ILIM P-Channel Power MOSFET Current-limit Peak Current 3 4 5 A VUV FB Under-Voltage Threshold VFB falling 66 70 74 % FB Under-Voltage Hysteresis - 40 - mV FB Under-Voltage Debounce - 2 - s Over-Temperature Trip Point - 150 - o o TOTP Over-Temperature Hysteresis C - 50 - C 9 10.8 12 ms SOFT-START, ENABLE and INPUT CURRENTS tSS Soft-Start Interval Preceding Delay before Soft-Start 9 10.8 12 ms EN Shutdown Voltage Threshold VEN falling, VIN = 4 ~ 26V 0.5 - - V EN Enable Voltage Threshold VEN rising, VIN = 4 ~ 26V - - 2.1 V 12 - 17 V - - 4 A EN Pin Clamped Voltage IEN=10mA P-Channel Power MOSFET Leakage Current VEN = 0V, VLX = 0V, VIN = 26V IFB FB Pin Input Current VFB = 0.8V -100 - +100 nA IEN EN Pin Input Current VEN < 3V -500 - +500 nA Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 4 www.anpec.com.tw APW7085 Typical Operating Characteristics Switching Frequency vs. Junction Temperature 420 0.812 410 Switching Frequency, FOSC (KHz) Reference Voltage, VREF (V) Reference Voltage vs. Junction Temperature 0.816 0.808 0.804 0.800 0.796 0.792 0.788 400 390 380 370 360 350 340 0.784 -50 -25 0 25 50 75 100 125 150 -50 -25 Junction Temperature, TJ (oC) Output Voltage vs. Supply Voltage 50 75 100 125 150 3.36 3.35 3.35 I OUT = 1A 3.34 3.34 Output Voltage, VOUT (V) Output Voltage, VOUT (V) 25 Output Voltage vs. Output Current 3.36 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 4 6 8 3.24 0.0 10 12 14 16 18 20 22 24 26 0.5 1.0 1.5 2.0 Supply Voltage, VIN (V) Output Current, IOUT (A) VIN Input Current vs. Supply Voltage Current-Limit Level (Peak Current) vs. Junction Temperature 1.6 5.0 VFB =0.85V Current-Limit Level, ILIM (A) 1.4 VIN Input Current, IVIN (mA) 0 Junction Temperature, TJ (oC) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 4 8 12 16 20 24 4.0 3.5 3.0 -50 28 -25 0 25 50 75 100 125 150 Junction Temperature, TJ (oC) VIN Supply Voltage, VIN (V) Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 4.5 5 www.anpec.com.tw APW7085 Typical Operating Characteristics (Cont.) Efficiency vs. Output Current EN Clamp Voltage vs. EN Input Current 100 18 90 16 EN Clamp Voltage, VEN (V) VOUT=5V 80 Efficiency (%) 70 VOUT=3.3V 60 50 40 30 20 10 0 0.001 14 12 TJ =-30oC 10 TJ =25oC 8 TJ =100oC 6 4 2 0 0.01 0.1 1 10 1 Output Current, IOUT (A) 10 100 1000 10000 EN Input Current, IEN (A) Operating Waveforms (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) Power On Power Off VIN IOUT=2A IOUT=2A VIN 1 1 VOUT VOUT 2 3 2 IL1 IL1 3 CH1 : VIN , 5V/div CH2 : VOUT , 1V/div CH3 : IL1 , 1A/div Time : 5ms/div CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 1A/div Time : 5ms/div Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 6 www.anpec.com.tw APW7085 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) EN Shutdown IOUT=2A IOUT=2A VEN VEN 1 1 2 VOUT VOUT 2 IL1 IL1 3 3 CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1 , 1A/div Time : 5ms/div CH1 : VEN , 5V/div CH2 : VOUT , 2V/div CH3 : IL1, 1A/div Time : 5ms/div Short Circuit Over Current IOUT =2~4A VOUT is shorted to GND by a short wire VLX 1 VLX 1 VOUT 2 VOUT 2 IL1 IL1 3 3 CH1 : VLX , 10V/div CH2 : VOUT , 1V/div CH3 : IL1 , 2A/div CH1 : VLX , 10V/div CH2 : VOUT , 50mV/div CH3 : IL1 , 2A/div Time : 50ms/div Time : 50s/div Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 7 www.anpec.com.tw APW7085 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H ) Load Transient Response Load Transient Response IOUT= 50mA-> 2A ->50mA IOUT rising/falling time=10s VOUT 1 1 IOUT= 0.5A-> 2A ->0.5A IOUT rising/falling time=10s VOUT IL1 IL1 2 2 CH1 : VOUT , 200mV/div CH1 : VOUT , 200mV/div CH2 : IL1 , 1A/div CH2 : IL1 , 1A/div Time : 50s/div Time : 50s/div Switching Waveform IOUT=0.2A Switching Waveform IOUT=2A VLX VLX 1 1 IL1 IL1 2 2 CH1 : VLX , 5V/div CH2 : IL1 , 200mA/div Time : 1s/div Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 CH1 : VLX , 5V/div CH2 : IL1 , 1A/div Time : 1s/div 8 www.anpec.com.tw APW7085 Operating Waveforms (Cont.) (Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H) Line Transient VIN= 12~26V VIN rising/falling time=20s VIN VOUT 2 IL1 1 3 CH1 : VIN , 5V/div CH2 : VOUT , 100mA/div (Voffset=3.3V) CH3 : IL1 , 2A/div Time : 100s/div Pin Description PIN NAME FUNCTION 1 VIN Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. 2 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Pull up with 100k resistor for automatic startup. 3 UGND Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a ceramic capacitor (1F typ.) between VIN and UGND for noise decoupling and stability of the linear regulator. 4 VCC Bias input and 4.2V linear regulator's output. This pin supplies the bias to some control circuits. The 4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V power supply is connected with VCC. Connect a ceramic capacitor (1F typ.) between VCC and GND for noise decoupling and stability of the linear regulator. 5 LX Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. Connect the pin to output LC filter. 6 COMP Output of error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required for noise decoupling. 7 FB Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V. Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V to 90% VIN. 8 GND Power and Signal Ground. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 9 www.anpec.com.tw APW7085 Block Diagram VIN Current Sense Amplifier 4.2V Regulator and Power-On-Reset VCC Current Limit VCC POR 70%VREF UG Soft-Start and Fault Logic UVP Gate Driver Soft-Start Inhibit UGND Gate Control FB VREF 0.8V Error Amplifier LX Current Compartor COMP VIN Slope Compensation ENOK 2.5V EN Over Temperature Protection Enable 0.8V FB 5.5V Oscillator 380KHz GND VIN-to-UGND Linear Regulator Typical Application Circuits 1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors) VIN C1 10F 4.5~26V 1 C2 1F VIN 4 VCC UGND C3 1F LX R3 100k VIN 3 5 VOUT 6 22F R1 1% EN COMP R4 FB GND 8 C6 7 R2 1% C7 (Optional) C5 Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 0.8V~90%VIN C4 /2A D1 U1 APW7085 2 L1 2A 10 www.anpec.com.tw APW7085 Typical Application Circuits (Cont.) Recommended Feedback Compensation Network Components List: VIN (V) VOUT (V) L1 (H) C4 (F) C4 ESR (m) R1 (k) R2 (k) C7 (pF) R4 (k) C5 (pF) C6 (pF) 24 12 15 22 5 140 10 15 100.0 820 22 24 12 15 44 3 140 10 15 200.0 820 22 24 5 10 22 5 63 12 22 43.0 1800 22 24 5 10 44 3 63 12 22 82.0 1800 22 12 5 10 22 5 63 12 30 43.0 1000 22 12 5 10 44 3 63 12 30 82.0 1000 22 12 3.3 10 22 5 46.9 15 39 27.0 1500 22 12 3.3 10 44 3 46.9 15 39 56.0 1500 22 12 2 4.7 22 5 30 20 39 18.0 2200 22 12 2 4.7 44 3 30 20 39 36.0 2200 22 12 1.2 3.3 22 5 7.5 15 100 10.0 3600 22 12 1.2 3.3 44 3 7.5 15 100 20.0 3600 22 5 3.3 3.3 22 5 46.9 15 47 27.0 560 22 5 3.3 3.3 44 3 46.9 15 47 56.0 560 22 5 1.2 2.2 22 5 7.5 15 200 10.0 1500 22 5 1.2 2.2 44 3 7.5 15 200 20.0 1500 22 5 0.8 2.2 22 5 0 NC NC 6.8 2200 22 5 0.8 2.2 44 3 0 NC NC 15.0 2200 22 2. Dual Power Inputs Step-down Converter (VIN=4.5~26V) VIN +5V C1 10F 1 D2 Schottky Diode 4.5~26V C2 1F VIN 4 VCC UGND C3 1F LX R3 100k VIN 3 5 VOUT 6 22F R1 1% EN COMP R4 FB GND 8 C6 7 R2 1% C7 (Optional) C5 Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 0.8V~90%VIN C4 /2A D1 U1 APW7085 2 L1 2A 11 www.anpec.com.tw APW7085 Typical Application Circuits (Cont.) 3. 4.5~5.5V Single Power Input Step-down Converter VIN C1 10F 4.5~5.5V 1 C2 1F VIN 4 VCC UGND C3 1F LX R3 100k VIN 3 L1 2A 5 VOUT U1 APW7085 2 6 R1 1% EN COMP FB R4 7 22F R2 1% GND 8 C6 0.8V~90%VIN C4 /2A D1 C7 (Optional) C5 4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors) VIN C1 2.2F C8 +12V 470F 1 C2 1F VIN 4 VCC UGND C3 1F LX 3 L1 10H 2A 5 VOUT +3.3V/2A R3 100k VIN 6 R1 46.9K 1% EN COMP R4 39K FB GND 8 C6 22pF D1 U1 APW7085 2 C5 1500pF Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 7 R2 15K 1% 12 C4 470F (ESR=30m) C7 39pF www.anpec.com.tw APW7085 Typical Application Circuits (Cont.) 5. -8V Inverting Converter with 4.5~5.5V Single Power Input VIN 4.5~5.5V C1 10F 1 R3 100k VIN 2 UGND EN LX 4 C3 1F C6 22pF 3 5 VCC U1 APW7085 6 C2 1F COMP R4 68k FB 7 PGND R1 90k R2 10k GND 8 C5 560pF D1 L1 10H 2A AGND C7 22pF C4 22F VOUT -8V/2A Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 13 www.anpec.com.tw APW7085 Function Description Main Control Loop physically close to the IC to provide good noise The APW7085 is a constant frequency current mode switching regulator. During normal operation, the internal decoupling. The linear regulator is not intended for powering up any external loads. Do not connect any P-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would be turned external loads to VCC. The linear regulator is also equipped with current-limit protection to protect itself dur- off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets ing over-load or short-circuit conditions on VCC pin. VIN-to-UGND 5.5V Linear Regulator the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier (EAMP). An exter- The built-in 5.5V linear regulator regulates a 5.5V voltage between VIN and UGND pins to supply bias and gate charge for the P-channel Power MOSFET gate driver. The nal resistive divider connected between V OUT and ground allows the EAMP to receive an output feedback linear regulator is designed to be stable with a low-ESR ceramic output capacitor of at least 0.22F. It is also voltage VFB at FB pin. When the load current increases, it causes a slight decrease in V FB relative to the 0.8V equipped with current-limit function to protect itself during over-load or short-circuit conditions between VIN reference, which in turn causes the COMP voltage to increase until the average inductor current matches the and UGND. new load current. The APW7085 shuts off the output of the converters when the output voltage of the linear regulator is below 3.5V VCC Power-On-Reset(POR) and EN Undervoltage Lockout The APW7085 keeps monitoring the voltage on VCC pin (typical). The IC resumes working by initiating a new softstart process when the linear regulator's output voltage to prevent wrong logic operations which may occur when VCC voltage is not high enough for the internal control is above the undervoltage lockout voltage threshold. Digital Soft-Start circuitry to operate. The VCC POR has a rising threshold of 3.9V (typical) with 0.15V of hysteresis. The APW7085 has a built-in digital soft-start to control the output voltage rise and limit the input current surge An external undervoltage lockout (UVLO) is sensed and during start-up. During soft-start, an internal ramp, connected to the one of the positive inputs of the error programmed at the EN pin. The EN UVLO has a rising threshold of 2.5V with 0.2V of hysteresis. The EN UVLO amplifier, rises up from 0V to 1V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference should be programmed by connecting a resistive divider from VIN to EN to GND. voltage. After the VCC, EN and VIN-to-UGND voltages exceed their The device is designed with a preceding delay about 10.8ms (typical) before soft-start process. respective voltage thresholds, the IC starts a start-up process and then ramps up the output voltage to the Output Undervoltage Protection setting of output voltage. Connect a RC network from EN to GND to set a turn-on delay that can be used to sequence In the process of operation, if a short-circuit occurs, the the output voltages of multiple devices. output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the VCC 4.2V Linear Regulator required regulation range. The undervoltage continually monitors the FB voltage after soft-start is completed. If a VCC is the output terminal of the internal 4.2V linear regulator which is powered from VIN and provides power to the APW7085. The linear regulator designed to be load step is strong enough to pull the output voltage lower than the undervoltage threshold, the IC shuts down stable with a low-ESR ceramic output capacitor powers the internal control circuitry. Bypass VCC to GND with a converter's output. The undervoltage threshold is 70% of the nominal output ceramic capacitor of at least 0.22F. Place the capacitor Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 14 www.anpec.com.tw APW7085 Function Description (Cont.) Output Undervoltage Protection (Cont.) voltage. The undervoltage comparator has a built-in 2s noise filter to prevent the chips from wrong UVP shutdown caused by noise. The undervoltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceeding delay. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7085. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature cools by 50oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Enable/Shutdown Driving EN to ground places the APW7085 in shutdown. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down and the quiescent supply current of VIN reduces to <1A (typical). Current-Limit Protection The APW7085 monitors the output current, flowing through the P-channel power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback When the output is shorted to ground, the frequency of the oscillator will be reduced to about 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator's frequency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 15 www.anpec.com.tw APW7085 Application Information Power Sequencing VIN VIN IQ1 The APW7085 can operate with sigle or dual power input(s). In dual-power applications, the voltage (VCC) applied at CIN Q1 VCC pin must be lower than the voltage (VIN) on VIN pin. The reason is the internal parasitic diode from VCC to VIN IL LX VOUT L will conduct due to the forward-voltage between VCC and VIN. Therefore, VIN must be provided before VCC. ICOUT D1 The regulated output voltage is determined by: VOUT ESR COUT Setting Output Voltage R1 = 0.8 (1 + ) R2 IOUT T=1/FOSC (V) VLX Suggested R2 is in the range from 1K to 20K. For portable applications, a 10k resistor is suggested for DT I IOUT R2. To prevent stray pickup, locate resistors R1 and R2 close to APW7085. IL IOUT Input Capacitor Selection IQ1 Each time, when the P-channel power MOSFET (Q1) turns I on, small ceramic capacitors for high frequency decoupling and bulk capacitors is required to supply the surge current. ICOUT VOUT The small ceramic capacitors have to be placed physically close to the VIN and between the VIN and the anode VOUT of the Schottky diode (D1). Figure 1 Converter Waveforms The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable Output Capacitor Selection operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and An output capacitor is required to filter the output and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than supply the load transient current. The filtering requirements are the functions of the switching frequency and the ripple the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) current (I). The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations: of the bulk input capacitor is calculated as the following equation: IRMS = IOUT D (1- D) (A) where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid VOUT + VD VIN + VD ........... (1) I = VOUT *(1 - D) FOSC *L ........... (2) VESR = I *ESR tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current (V) ........... (3) where VD is the forward voltage drop of the diode. rating. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 D= The peak-to-peak voltage of the ideal output capacitor is calculated as the following equations: 16 www.anpec.com.tw APW7085 Application Information (Cont.) Output Capacitor Selection (Cont.) I VCOUT = (V) 8 FOSC COUT and greater core losses. A reasonable starting point for setting ripple current is I 0.4 IOUT(MAX) . Remember, the maximum ripple current occurs at the maximum input ........... (4) For the applications, using bulk capacitors, the VCOUT voltage. The minimum inductance of the inductor is calculated by using the following equation: is much smaller than the V ESR and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is VOUT *(VIN - VOUT) 1.2 380000 *L *VIN shown below: VOUT = I ESR (V) ........... (5) L For the applications, using ceramic capacitors, the VESR is much smaller than the V COUT and can be ignored. VOUT *(VIN - VOUT ) 456000 *VIN (H) ........... (6) where VIN = VIN(MAX) Therefore, the AC peak-to-peak output voltage (VOUT ) is close to VCOUT . Output Diode Selection The load transient requirements are the functions of the The Schottky diode carries load current during the off-time. slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a Therefore, the average diode current is dependent on the P-channel power MOSFET duty cycle. At high input voltages mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the the diode conducts most of the time. As VIN approaches VOUT the diode conducts only a small fraction of the time. current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR The most stressful condition for the diode is when the output is short-circuited. Therefore, it is important to (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. High frequency decoupling capacitors should be placed Under normal load conditions, the average current physically as close to the power pins of the load as possible. Be careful not to add inductance in the circuit conducted by the diode is: ID = board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic VIN - VOUT IOUT VIN + VD The APW7085 is equipped with whole protections to reduce the power dissipation during short-circuit capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the condition. Therefore, the maximum power dissipation of the diode is calculated from the maximum output current Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness as: of the capacitor to high slew-rate transient loading. PDIODE(MAX) = VD *ID(MAX) Inductor Value Calculation where The operating frequency and inductor selection are interrelated in that higher operating frequencies permit IOUT = IOUT(MAX) Remember to keep lead length short and observe proper grounding to avoid ringing and increased dissipation. the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances but results in higher output voltage ripple Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 17 www.anpec.com.tw APW7085 Layout Consideration In high power switching regulator, a correct layout is 5. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. The bulk capacitors C8 are important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized also placed near VIN. Use a wide power ground plane to connect the C1, C8, C4, and Schottky diode to by using short and wide printed circuit traces. Signal and power grounds are to be kept separate and finally provide a low impedance path between the components for large and high slew rate current. combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is D1 a checklist for your layout: 1. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power C1 flow path. If possible, make all the connections on one side of the PCB with wide and copper filled areas. VLX L1 VOUT C4 SOP-8 VIN 2. In Figure 2, the loops with same color bold lines Load GND GND conduct high slew rate current. These interconnecting impedances should be minimized by using wide and Figure 3 Recommended Layout Diagram short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 4. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor C2 should be connected as close to the VIN and UGND pins as possible. + VIN - C2 1 VIN 3 UGND LX 5 4 C3 2 R4 C5 Compensation Network C8 C4 Load VOUT U1 APW7085 EN GND 8 L1 + D1 VCC 6 COMP C6 C1 R1 FB 7 R2 C7 (Optional) Feedback Divider Figure 2 Current Path Diagram Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 18 www.anpec.com.tw APW7085 Package Information SOP-8 D E E1 SEE VIEW A h X 45 c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0 8 0 8 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 19 www.anpec.com.tw APW7085 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.02.00 50 MIN. SOP- 8 P0 4.00.10 T1 P1 8.00.10 C d D W E1 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 -0.00 -0.20 P2 D0 2.00.05 1.5+0.10 -0.00 D1 T 1.5 MIN. A0 B0 F 5.50.05 K0 0.6+0.00 6.400.20 5.200.20 2.100.20 -0.40 (mm) Devices Per Unit Package Type SOP-8 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 Quantity 2500 20 www.anpec.com.tw APW7085 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3C/second max. 3C/second max. 100C 150C 60-120 seconds 150C 200C 60-180 seconds 183C 60-150 seconds 217C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 21 www.anpec.com.tw APW7085 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C 3 Volume mm 350 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Apr., 2008 22 www.anpec.com.tw