Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
2A, 26V, 380kHz, Asynchronous Step-Down Converter
Features
•Wide Input Voltage from 4.5V to 26V
•Output Current up to 2A
•Adjustable Output Voltage from 0.8V to 90%VIN
- 0.8V Reference Voltage
- ±2.5% System Accuracy
•100mΩ Integrated P-Channel Power MOSFET
•High Efficiency up to 91%
- Pulse-Skipping Mode (PSM) / PWM Mode Operation
•Current-Mode Operation
- Stable with Ceramic Output Capacitors
- Fast Transient Response
•Power-On-Reset Monitoring
•Fixed 380kHz Switching Frequency in PWM Mode
•Built-in Digital Soft-Start
•Output Current-Limit Protection with Frequency
Foldback
•70% Undervoltage Protection
•Over-Temperature Protection
•<5µA Quiescent Current during Shutdown
•SOP-8 Package
•Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
The APW7085 is a 2A, asynchronous, step-down converter
with integrated 100mΩ P-channel MOSFET. The device,
with current-mode control scheme, can convert 4.5~26V
input voltage to the output voltage adjustable from 0.8 to
90% VIN to provide excellent output voltage regulation.
The APW7085 regulates the output voltage in automatic
PSM/PWM mode operation, depending on the output
current, for high efficiency operation over light to full load
current. The APW7085 is also equipped with power-on-
reset, soft-start, and whole protections (undervoltage,
over- temperature, and current-limit) into a single package.
In shutdown mode, the supply current drops below 5µA.
This device, available in an 8-pin SOP-8 package, pro-
vides a very compact system solution with minimal exter-
nal components.
•LCD Monitor / TV
•Set-Top Box
•Portable DVD
•Wireless LAN
•ADSL, Switch HUB
•Notebook Computer
•Step-down Converters Requiring High Efficiency
and 2A Output Current
Simplified Application Circuit
Efficiency (%)
Output Current, IOUT (A)
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 110
VOUT=3.3V
VOUT=5V
R2
1%
LX
EN
VIN
GND
COMP
U1
APW7085
FB
UGND
VOUT
+3.3V
L1
2A
D1
VCC
C3
C2
VIN
+12V
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
VIN
C7
(Optional)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw2
Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 30 V
> 100ns -2 ~ VIN+0.3
VLX LX to GND Voltage < 100ns -5 ~ VIN+6 V
VIN > 6.2V -0.3 ~ 6.5
VCC VCC Supply Voltage (VCC to GND) VIN ≤ 6.2V < VIN+0.3 V
VUGND_GND UGND to GND Voltage -0.3 ~ VIN+0.3 V
VVIN_UGND VIN to UGND Voltage -0.3 ~ 6.5V V
EN to GND Voltage 20 V
FB, COMP to GND Voltage -0.3 ~ VCC +0.3
V
Maximum Junction Temperature 150 °C
TSTG Storage Temperature -65 ~ 150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in free air (Note 2)
SOP-8
80 oC/W
Ordering and Marking Information
Pin Configuration
SOP-8
Top View
Absolute Maximum Ratings (Note 1)
Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device.
GND
FB
COMP
LX
VIN
EN
UGND
VCC
8
7
6
5
1
2
3
4
Thermal Characteristics
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
APW7085
Handling Code
Temperature Range
Package Code
Package Code
K : SOP-8
Operating Ambient Temperature Range
I : -40 to 85 C
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device G : Halogen and Lead Free Device
°
Assembly Material
APW7085 K : APW7085
XXXXX XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw3
Recommended Operating Conditions (Note 3)
Symbol Parameter Range Unit
VIN VIN Supply Voltage 4.5 ~ 26 V
VCC Supply Voltage 4.0 ~ 5.5 V
VOUT Converter Output Voltage 0.8 ~ 90% VIN V
IOUT Converter Output Current 0 ~ 2 A
VCC Input Capacitor 0.22 ~ 2.2 µF
VIN-to-UGND Input Capacitor 0.22 ~ 2.2 µF
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Note 3: Refer to the typical application circuits
Electrical Characteristics
APW7085
Symbol
Parameter Test Conditions Min Typ Max Unit
SUPPLY CURRENT
IVIN VIN Supply Current VFB = 0.85V, VEN=3V, LX=Open - 1.0 2.0 mA
IVIN_SD
VIN Shutdown Supply Current VEN = 0V, VIN=26V - - 5 µA
IVCC VCC Supply Current VEN = 3V, VCC = 5.0V, VFB=0.85V - 0.7 - mA
IVCC_SD
VCC Shutdown Supply Current VEN = 0V, VCC = 5.0V - - 1 µA
VCC 4.2V LINEAR REGULATOR
Output Voltage VIN = 5.2 ~ 26V, IO = 0 ~ 8mA 4.0 4.2 4.5 V
Load Regulation IO = 0 ~ 8mA -60 -40 0 mV
Current-Limit VCC > POR Threshold 8 - 30 mA
VIN-to-UGND 5.5V LINEAR REGULATOR
Output Voltage (VVIN-UGND) VIN = 6.2 ~ 26V, IO = 0 ~ 10mA 5.3 5.5 5.7 V
Load Regulation IO = 0 ~ 10mA -80 -60 0 mV
Current-Limit VIN = 6.2 ~ 26V 10 - 30 mA
POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS
VCC POR Voltage Threshold VCC rising 3.7 3.9 4.1 V
VCC POR Hysteresis - 0.15 - V
EN Lockout Voltage Threshold VEN rising 2.3 2.5 2.7 V
EN Lockout Hysteresis - 0.2 - V
VIN-to-UGND Lockout Voltage
Threshold VVIN-UGND rising - 3.5 - V
VIN-to-UGND Lockout Hysteresis - 0.2 - V
REFERENCE VOLTAGE
VREF Reference Voltage - 0.8 - V
TJ = 25oC, IOUT=0A, VIN=12V -1.0 - +1.0
Output Voltage Accuracy TJ = -40 ~ 125oC, IOUT = 0 ~ 2A,
VIN = 4.5 ~ 26V -2.5 - +2.5 %
Line Regulation VIN = 4.5V to 26V, IOUT = 0A - 0.36 - %
Load Regulation IOUT = 0 ~ 2A - 0.4 - %
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw4
Electrical Characteristics (Cont.)
APW7085
Symbol
Parameter Test Conditions Min Typ Max Unit
OSCILLATOR and DUTY
FOSC Free Running Frequency VIN = 4.5 ~ 26V 340 380 420 kHz
Foldback Frequency VFB = 0V - 80 - kHz
Maximum Converter’s Duty Cycle - 93 - %
Minimum Pulse Width of LX VIN = 4.5 ~ 26V - 200 - ns
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance - 400 - µA/V
Error Amplifier DC Gain COMP = Open 60 80 - dB
Current-Sense Resistance - 0.2 - Ω
P-Channel Power MOSFET
Resistance TJ=25oC - 100 140 mΩ
PROTECTIONS
ILIM P-Channel Power MOSFET
Current-limit Peak Current 3 4 5 A
VUV FB Under-Voltage Threshold VFB falling 66 70 74 %
FB Under-Voltage Hysteresis - 40 - mV
FB Under-Voltage Debounce - 2 - µs
TOTP Over-Temperature Trip Point - 150 - oC
Over-Temperature Hysteresis - 50 - oC
SOFT-START, ENABLE and INPUT CURRENTS
tSS Soft-Start Interval 9 10.8 12 ms
Preceding Delay before Soft-Start 9 10.8 12 ms
EN Shutdown Voltage Threshold VEN falling, VIN = 4 ~ 26V 0.5 - - V
EN Enable Voltage Threshold VEN rising, VIN = 4 ~ 26V - - 2.1 V
EN Pin Clamped Voltage IEN=10mA 12 - 17 V
P-Channel Power MOSFET
Leakage Current VEN = 0V, VLX = 0V, VIN = 26V - - 4 µA
IFB FB Pin Input Current VFB = 0.8V -100 - +100
nA
IEN EN Pin Input Current VEN < 3V -500 - +500
nA
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise
specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw5
Typical Operating Characteristics
Reference Voltage, VREF (V)
Junction Temperature, TJ (oC)
Reference Voltage vs. Junction Temperature
Switching Frequency, FOSC (KHz)
Junction Temperature, TJ (oC)
Switching Frequency vs. Junction Temperature
Output Voltage, VOUT (V)
Supply Voltage, VIN (V)
Output Voltage vs. Supply Voltage
Output Voltage, VOUT (V)
Output Current, IOUT (A)
Output Voltage vs. Output Current
Current-Limit Level, ILIM (A)
Junction Temperature, TJ (oC)
Current-Limit Level (Peak Current)
vs. Junction Temperature
VIN Input Current, IVIN (mA)
VIN Supply Voltage, VIN (V)
VIN Input Current vs. Supply Voltage
340
350
360
370
380
390
400
410
420
-50 -25 025 50 75 100 125 150
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
4 6 8 10 12 14 16 18 20 22 24 26
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 4 8 12 16 20 24 28
IOUT = 1AIOUT = 1A
VFB=0.85VVFB=0.85V
0.784
0.788
0.792
0.796
0.800
0.804
0.808
0.812
0.816
-50 -25 025 50 75 100 125 150
3.24
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
3.36
0.0 0.5 1.0 1.5 2.0
3.0
3.5
4.0
4.5
5.0
-50 -25 025 50 75 100 125 150
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
Efficiency (%)
Output Current, IOUT (A)
Efficiency vs. Output Current
EN Clamp Voltage, VEN (V)
EN Input Current, IEN (µA)
EN Clamp Voltage vs. EN Input Current
0
2
4
6
8
10
12
14
16
18
110 100 1000 10000
Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
TJ=-30oCTJ=-30oC
TJ=25oCTJ=25oC
TJ=100oCTJ=100oC
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 110
VOUT=3.3V
VOUT=5V
Power On
CH1 : VIN , 5V/div
CH2 : VOUT , 2V/div
Time : 5ms/div
1
2
3
CH3 : IL1 , 1A/div
VIN
VOUT
IL1
IOUT=2A
Power Off
CH1 : VIN , 5V/div
CH2 : VOUT , 1V/div
Time : 5ms/div
CH3 : IL1 , 1A/div
1
2
3
VIN
VOUT
IL1
IOUT=2A
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw7
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
CH1 : VEN , 5V/div
CH3 : IL1 , 1A/div
Time : 5ms/div
CH2 : VOUT , 2V/div
EN
1
2
3
VEN
VOUT
IL1
IOUT=2A
Shutdown
VEN
VOUT
IL1
CH1 : VEN , 5V/div
CH3 : IL1, 1A/div
Time : 5ms/div
CH2 : VOUT , 2V/div
1
2
3
IOUT=2A
CH1 : VLX , 10V/div
CH2 : VOUT , 1V/div
CH3 : IL1 , 2A/div
Time : 50µs/div
Over Current
IOUT =2~4A
VLX
VOUT
IL1
1
2
3
Short Circuit
VLX
VOUT
IL1
CH1 : VLX , 10V/div
CH2 : VOUT , 50mV/div
CH3 : IL1 , 2A/div
Time : 50ms/div
1
2
3
VOUT is shorted to GND by a short wire
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw8
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH )
Load Transient Response
VOUT
IL1
CH1 : VOUT , 200mV/div
CH2 : IL1 , 1A/div
Time : 50µs/div
1
2
IOUT= 50mA-> 2A ->50mA
IOUT rising/falling time=10µs
CH1 : VOUT , 200mV/div
CH2 : IL1 , 1A/div
Time : 50µs/div
IL1
VOUT
1
2
Load Transient Response
IOUT= 0.5A-> 2A ->0.5A
IOUT rising/falling time=10µs
CH1 : VLX , 5V/div
CH2 : IL1 , 200mA/div
Time : 1µs/div
IL1
VLX
Switching Waveform
IOUT=0.2A
1
2
CH1 : VLX , 5V/div
CH2 : IL1 , 1A/div
Time : 1µs/div
VLX
IL1
Switching Waveform
IOUT=2A
1
2
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw9
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=10µH)
Pin Description
PIN NAME FUNCTION
1 VIN Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-
down
converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between
VIN and GND eliminates switching noise and voltage ripple on the input to the IC.
2 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Pull up with 100kΩ resistor for automatic startup.
3 UGND
Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V
voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a
ceramic capacitor (1µF typ.) between VIN and U
GND for noise decoupling and stability of the linear
regulator.
4 VCC
4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V
power supply is connected with VCC. Connect a ceramic capacitor (1µF typ.) between VCC and
GND for noise decoupling and stability of the linear regulator.
5 LX Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output.
Connect the pin to output LC filter.
6 COMP Output of error amplifier. Connect a series RC network from COMP to GND to compensate the
regulation control loop. In some cases, an additional capacitor from COMP to GND is required for
noise decoupling.
7 FB Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V.
Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V
to 90% VIN.
8 GND Power and Signal Ground.
VIN
VOUT
IL1
CH1 : VIN , 5V/div
CH2 : VOUT , 100mA/div (Voffset=3.3V)
Time : 100µs/div
2
1
3
CH3 : IL1 , 2A/div
Line Transient
VIN= 12~26V VIN rising/falling
time=20µs
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw10
Block Diagram
Typical Application Circuits
1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors)
LX
Gate
Control
VREF
0.8V
Soft-Start
and
Fault Logic
Error
Amplifier
FB
Inhibit
70%VREF UVP
GND
POR
Soft-Start
4.2V Regulator
and
Power-On-Reset
VCC
VCC
Enable
Current Sense
Amplifier
EN
COMP
Oscillator
380KHz
Slope
Compensation
Current
Compartor
0.8V
UGND
VIN
Over
Temperature
Protection
Current
Limit
VIN-to-UGND
Linear Regulator
VIN
5.5V
FB
2.5V ENOK
UG
Gate
Driver
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
U1
APW7085
FB 7
UGND 3
VOUT
0.8V~90%VIN
/2A
L1
2A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~26V
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
R3
100kΩ
VIN
C7
(Optional)
5
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw11
Typical Application Circuits (Cont.)
Recommended Feedback Compensation Network Components List:
VIN
(V) VOUT
(V) L1
(µH) C4
(µF) C4 ESR
(mΩ) R1
(kΩ) R2
(kΩ) C7
(pF) R4
(kΩ) C5
(pF) C6
(pF)
24 12 15 22 5 140
10 15 100.0
820
22
24 12 15 44 3 140
10 15 200.0
820
22
24 5 10 22 5 63 12 22 43.0
1800
22
24 5 10 44 3 63 12 22 82.0
1800
22
12 5 10 22 5 63 12 30 43.0
1000
22
12 5 10 44 3 63 12 30 82.0
1000
22
12 3.3 10 22 5 46.9
15 39 27.0
1500
22
12 3.3 10 44 3 46.9
15 39 56.0
1500
22
12 2 4.7 22 5 30 20 39 18.0
2200
22
12 2 4.7 44 3 30 20 39 36.0
2200
22
12 1.2 3.3 22 5 7.5 15 100
10.0
3600
22
12 1.2 3.3 44 3 7.5 15 100
20.0
3600
22
5 3.3 3.3 22 5 46.9
15 47 27.0
560
22
5 3.3 3.3 44 3 46.9
15 47 56.0
560
22
5 1.2 2.2 22 5 7.5 15 200
10.0
1500
22
5 1.2 2.2 44 3 7.5 15 200
20.0
1500
22
5 0.8 2.2 22 5 0 NC NC 6.8 2200
22
5 0.8 2.2 44 3 0 NC NC 15.0
2200
22
2. Dual Power Inputs Step-down Converter (VIN=4.5~26V)
+5V
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
U1
APW7085
FB 7
UGND 3
VOUT
0.8V~90%VIN
/2A
L1
2A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~26V
C1
10µF
C5
R4
C6
D2
Schottky
Diode
C4
22µF
R1
1%
R3
100kΩ
VIN
C7
(Optional)
5
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw12
3. 4.5~5.5V Single Power Input Step-down Converter
Typical Application Circuits (Cont.)
4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors)
R2
1%
LX
EN
2
VIN
1
GND
8
COMP
6
U1
APW7085
FB 7
UGND 3
VOUT
0.8V~90%VIN
/2A
L1
2A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~5.5V
C1
10µF
C5
R4
C6
C4
22µF
R1
1%
C7
(Optional)
R3
100kΩ
VIN
5
R2
15K
1%
LX
EN
2
VIN
1
GND
8
COMP
6
U1
APW7085
FB 7
UGND 3
VOUT
+3.3V/2A
L1
10µH
2A
D1
VCC
4
C3
1µF
C2
1µF
VIN
+12V
C1
2.2µF
C5
1500pF
R4
39K
C6
22pF
C4
470µF
R1
46.9K
1%
R3
100kΩ
VIN
C8
470µF
C7
39pF
5
(ESR=30mΩ)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw13
Typical Application Circuits (Cont.)
5. -8V Inverting Converter with 4.5~5.5V Single Power Input
LX
EN
2
VIN
1
GND
8
COMP
6
U1
APW7085
UGND 3
L1
10µH
2A
D1
VCC
4
C3
1µF
C2
1µF
VIN
4.5~5.5V
C1
10µF
C5
560pF
R4
68kΩ
C6
22pF C4
22µF
R3
100kΩ
5
R2
10kΩ
FB 7
R1
90kΩ
C7
22pF
PGND
AGND
VOUT
-8V/2A
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw14
Function Description
Main Control Loop
The APW7085 is a constant frequency current mode
switching regulator. During normal operation, the internal
P-channel power MOSFET is turned on each cycle when
the oscillator sets an internal RS latch and would be turned
off when an internal current comparator (ICMP) resets
the latch. The peak inductor current at which ICMP resets
the RS latch is controlled by the voltage on the COMP pin,
which is the output of the error amplifier (EAMP). An exter-
nal resistive divider connected between VOUT and
ground allows the EAMP to receive an output feedback
voltage VFB at FB pin. When the load current increases, it
causes a slight decrease in VFB relative to the 0.8V
reference, which in turn causes the COMP voltage to in-
crease until the average inductor current matches the
new load current.
VCC Power-On-Reset(POR) and EN Undervoltage
Lockout
The APW7085 keeps monitoring the voltage on VCC pin
to prevent wrong logic operations which may occur when
VCC voltage is not high enough for the internal control
circuitry to operate. The VCC POR has a rising threshold
of 3.9V (typical) with 0.15V of hysteresis.
An external undervoltage lockout (UVLO) is sensed and
programmed at the EN pin. The EN UVLO has a rising
threshold of 2.5V with 0.2V of hysteresis. The EN UVLO
should be programmed by connecting a resistive divider
from VIN to EN to GND.
After the VCC, EN and VIN-to-UGND voltages exceed their
respective voltage thresholds, the IC starts a start-up
process and then ramps up the output voltage to the
setting of output voltage. Connect a RC network from EN
to GND to set a turn-on delay that can be used to sequence
the output voltages of multiple devices.
VCC 4.2V Linear Regulator
VCC is the output terminal of the internal 4.2V linear
regulator which is powered from VIN and provides power
to the APW7085. The linear regulator designed to be
stable with a low-ESR ceramic output capacitor powers
the internal control circuitry. Bypass VCC to GND with a
ceramic capacitor of at least 0.22µF. Place the capacitor
physically close to the IC to provide good noise
decoupling. The linear regulator is not intended for
powering up any external loads. Do not connect any
external loads to VCC. The linear regulator is also
equipped with current-limit protection to protect itself dur-
ing over-load or short-circuit conditions on VCC pin.
VIN-to-UGND 5.5V Linear Regulator
The built-in 5.5V linear regulator regulates a 5.5V voltage
between VIN and UGND pins to supply bias and gate
charge for the P-channel Power MOSFET gate driver. The
linear regulator is designed to be stable with a low-ESR
ceramic output capacitor of at least 0.22µF. It is also
equipped with current-limit function to protect itself
during over-load or short-circuit conditions between VIN
and UGND.
The APW7085 shuts off the output of the converters when
the output voltage of the linear regulator is below 3.5V
(typical). The IC resumes working by initiating a new soft-
start process when the linear regulator’s output voltage
is above the undervoltage lockout voltage threshold.
Digital Soft-Start
The APW7085 has a built-in digital soft-start to control the
output voltage rise and limit the input current surge
during start-up. During soft-start, an internal ramp,
connected to the one of the positive inputs of the error
amplifier, rises up from 0V to 1V to replace the reference
voltage (0.8V) until the ramp voltage reaches the reference
voltage.
The device is designed with a preceding delay about
10.8ms (typical) before soft-start process.
Output Undervoltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the
required regulation range. The undervoltage continually
monitors the FB voltage after soft-start is completed. If a
load step is strong enough to pull the output voltage lower
than the undervoltage threshold, the IC shuts down
converter’s output.
The undervoltage threshold is 70% of the nominal output
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw15
Function Description (Cont.)
voltage. The undervoltage comparator has a built-in 2µs
noise filter to prevent the chips from wrong UVP shut-
down caused by noise. The undervoltage protection works
in a hiccup mode without latched shutdown. The IC will
initiate a new soft-start process at the end of the
preceeding delay.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction tempera-
ture of the APW7085. When the junction temperature ex-
ceeds TJ = +150oC, a thermal sensor turns off the power
MOSFET, allowing the devices to cool. The thermal sensor
allows the converter to start a start-up process and
regulate the output voltage again after the junction
temperature cools by 50oC. The OTP is designed with a
50oC hysteresis to lower the average TJ during continuous
thermal overload conditions, increasing lifetime of the IC.
Enable/Shutdown
Driving EN to ground places the APW7085 in shutdown.
When in shutdown, the internal power MOSFET turns off,
all internal circuitry shuts down and the quiescent supply
current of VIN reduces to <1µA (typical).
Current-Limit Protection
The APW7085 monitors the output current, flowing through
the P-channel power MOSFET, and limits the current peak
at current-limit level to prevent loads and the IC from
damages during overload or short-circuit conditions.
Frequency Foldback
When the output is shorted to ground, the frequency of
the oscillator will be reduced to about 80kHz. This lower
frequency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s
frequency will gradually increase to its designed rate
when the feedback voltage on FB again approaches 0.8V.
Output Undervoltage Protection (Cont.)
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw16
Application Information
(V) )
R2
R1
(10.8VOUT +⋅=
Power Sequencing
The APW7085 can operate with sigle or dual power input(s).
Suggested R2 is in the range from 1K to 20KΩ. For
portable applications, a 10kΩ resistor is suggested for
R2. To prevent stray pickup, locate resistors R1 and R2
close to APW7085.
Input Capacitor Selection
Each time, when the P-channel power MOSFET (Q1) turns
on, small ceramic capacitors for high frequency decoupling
and bulk capacitors is required to supply the surge current.
The small ceramic capacitors have to be placed physi-
cally close to the VIN and between the VIN and the anode
of the Schottky diode (D1).
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and
current ratings above the maximum input voltage and
largest RMS current required by the circuit. The capacitor
voltage rating should be at least 1.25 times greater than
the maximum input voltage and a voltage rating of 1.5
times is a conservative guideline. The RMS current (IRMS)
of the bulk input capacitor is calculated as the following
equation:
(A) D)-(1DI IOUTRMS ⋅⋅=
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current
rating.
VIN
VOUT
CIN
COUT
L
Q1
LX
ESR
ILIOUT
IQ1
ICOUT
D1
VIN
Figure 1 Converter Waveforms
IOUT
VLX
T=1/FOSC
IL
IQ1
ICOUT
IOUT
I
I
DT
VOUT
VOUT
Output Capacitor Selection
An output capacitor is required to filter the output and
supply the load transient current. The filtering requirements
are the functions of the switching frequency and the ripple
current (∆I). The output ripple is the sum of the voltages,
having phase shift, across the ESR and the ideal out-
put capacitor. The peak-to-peak voltage of the ESR is
calculated as the following equations:
DIN
DOUT VV VV
D++
=........... (1)
........... (2)
........... (3)
L · FD)-(1 · V
IOSC
OUT
=∆
(V) ESR · I VESR ∆=
where VD is the forward voltage drop of the diode.
The peak-to-peak voltage of the ideal output capacitor is
calculated as the following equations:
In dual-power applications, the voltage (VCC) applied at
VCC pin must be lower than the voltage (VIN) on VIN pin.
The reason is the internal parasitic diode from VCC to VIN
will conduct due to the forward-voltage between VCC and
VIN. Therefore, VIN must be provided before VCC.
Setting Output Voltage
The regulated output voltage is determined by:
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw17
Application Information (Cont.)
Output Capacitor Selection (Cont.)
(V)
CF8I
VOUTOSC
COUT ⋅⋅ ∆
=∆........... (4)
For the applications, using bulk capacitors, the ∆VCOUT
is much smaller than the VESR and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
shown below:
(V) ESRI VOUT ⋅∆=∆........... (5)
For the applications, using ceramic capacitors, the VESR is
much smaller than the ∆VCOUT and can be ignored.
Therefore, the AC peak-to-peak output voltage (∆VOUT ) is
close to ∆VCOUT .
The load transient requirements are the functions of the
slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
mix of capacitors and careful layout. High frequency
capacitors initially supply the transient and slow the
current load rate seen by the bulk capacitors. The bulk
filter capacitor values are generally determined by the ESR
(Effective Series Resistance) and voltage rating require-
ments rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed
physically as close to the power pins of the load as
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the
Equivalent Series Inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness
of the capacitor to high slew-rate transient loading.
Inductor Value Calculation
The operating frequency and inductor selection are
interrelated in that higher operating frequencies permit
the use of a smaller inductor for the same amount of
inductor ripple current. However, this is at the expense of
efficiency due to an increase in MOSFET gate charge
losses. The equation (2) shows that the inductance value
has a direct effect on ripple current.
Accepting larger values of ripple current allows the use of
low inductances but results in higher output voltage ripple
........... (6)
IN(MAX)IN V V=
Output Diode Selection
The Schottky diode carries load current during the off-time.
Therefore, the average diode current is dependent on the
P-channel power MOSFET duty cycle. At high input voltages
the diode conducts most of the time. As VIN approaches
VOUT the diode conducts only a small fraction of the time.
The most stressful condition for the diode is when the
output is short-circuited. Therefore, it is important to
adequately specify the diode peak current and average
power dissipation so as not to exceed the diode ratings.
Under normal load conditions, the average current
conducted by the diode is:
OUT
DIN
OUTIN
DI
V V V- V
I⋅
+
=
The APW7085 is equipped with whole protections to
reduce the power dissipation during short-circuit
condition. Therefore, the maximum power dissipation of
the diode is calculated from the maximum output current
as:
D(MAX)D DIODE(MAX) I · V P=
OUT(MAX)OUT I I=
where
where
Remember to keep lead length short and observe proper
grounding to avoid ringing and increased dissipation.
and greater core losses. A reasonable starting point for
setting ripple current is ∆I ≤ 0.4 ⋅ IOUT(MAX) . Remember, the
maximum ripple current occurs at the maximum input
voltage. The minimum inductance of the inductor is
calculated by using the following equation:
1.2
V· L · 380000 )V-(V · V
IN
OUTINOUT ≤
(H)
V· 456000 )V-(V · V
LIN
OUTINOUT
≥
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw18
Layout Consideration
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator. In
general, interconnecting impedance should be minimized
by using short and wide printed circuit traces. Signal and
power grounds are to be kept separate and finally
combined using ground plane construction or single
point grounding. Figure 2 illustrates the layout, with bold
lines indicating high current paths. Components along
the bold lines should be placed close together. Below is
a checklist for your layout:
1. Begin the layout by placing the power components
first. Orient the power circuitry to achieve a clean power
flow path. If possible, make all the connections on
one side of the PCB with wide and copper filled areas.
2. In Figure 2, the loops with same color bold lines
conduct high slew rate current. These interconnecting
impedances should be minimized by using wide and
short printed circuit traces.
3. Keep the sensitive small signal nodes (FB, COMP)
away from switching nodes (LX or others) on the PCB.
Therefore, place the feedback divider and the feed-
back compensation network close to the IC to avoid
switching noise. Connect the ground of feedback
divider directly to the GND pin of the IC using a
dedicated ground trace.
4. The VCC decoupling capacitor should be right next
to the VCC and GND pins. Capacitor C2 should be
connected as close to the VIN and UGND pins as
possible.
5. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. The bulk capacitors C8 are
also placed near VIN. Use a wide power ground plane
to connect the C1, C8, C4, and Schottky diode to
provide a low impedance path between the com-
ponents for large and high slew rate current.
Figure 2 Current Path Diagram
Figure 3 Recommended Layout Diagram
R2
LX
EN
2
VIN
1
GND
8
COMP
6
5
U1
APW7085
FB 7
L1
VCC
4
C3
+
VIN
-C1
C5
R4
C6
C4
R1
C7
(Optional)
Load
D1
Feedback
Divider
Compensation
Network
UGND
3
C2
+
VOUT
-
C8
SOP-8
C1
L1
D1
C4
Load
VIN
GND
VOUT
GND
VLX
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw19
Package Information
SOP-8
S
Y
M
B
O
LMIN. MAX.
1.75
0.10
0.17 0.25
0.25
A
A1
c
D
E
E1
e
h
L
MILLIMETERS
b0.31 0.51
SOP-8
0.25 0.50
0.40 1.27
MIN. MAX.
INCHES
0.069
0.004
0.012 0.020
0.007 0.010
0.010 0.020
0.016 0.050
0
0.010
1.27 BSC 0.050 BSC
A2 1.25 0.049
0
°
8
°
0
°
8
°
D
e
E
E1
SEE VIEW A
cb
h X 45
°
A
A1A2
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
Note: 1. Follow JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
3.80
5.80
4.80
4.00
6.20
5.00 0.189 0.197
0.228 0.244
0.150 0.157
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw20
Carrier Tape & Reel Dimensions
Devices Per Unit
Package Type Unit Quantity
SOP-8 Tape & Reel 2500
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP- 8
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw21
Reflow Condition (IR/Convection or VPR Reflow)
Classification Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classification Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reliability Test Program
t 25 C to Peak
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Copyright ANPEC Electronics Corp.
Rev. A.5 - Apr., 2008
APW7085
www.anpec.com.tw22
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Classification Reflow Profiles (Cont.)
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838