TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Very Low Power Consumption
D
Typical Supply Current . . . 200 µA
(Per Amplifier)
D
Wide Common-Mode and Differential
Voltage Ranges
D
Low Input Bias and Offset Currents
D
Common-Mode Input Voltage Range
Includes VCC+
D
Output Short-Circuit Protection
D
High Input Impedance . . . JFET-Input Stage
D
Internal Frequency Compensation
D
Latch-Up-Free Operation
D
High Slew Rate . . . 3.5 V/µs Typ
1
2
3
4
8
7
6
5
OFFSET N1
IN–
IN+
VCC–
NC
VCC+
OUT
OFFSET N2
TL061, TL061A . . . D, P, OR PS PACKAGE
TL061B ...P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
VCC–
VCC+
2OUT
2IN–
2IN+
TL062 . . . D, JG, P, PS, OR PW PACKAGE
TL062A . . . D, P, OR PS PACKAGE
TL062B ...D OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN–
1IN+
VCC+
2IN+
2IN–
2OUT
4OUT
4IN–
4IN+
VCC–
3IN+
3IN–
3OUT
TL064 . . . D, J, N, NS, PW, OR W PACKAGE
TL064A, TL064B ...D OR N PACKAGE
(TOP VIEW)
NC – No internal connection
NC
2OUT
NC
2IN–
NC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
1IN–
NC
1IN+
NC
TL062 . . . FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
2IN+
NC NC
NC
NC
V
CC–
VCC+
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC–
NC
3IN+
1IN+
NC
VCC+
NC
2IN+
1IN–
1OUT
NC
3
OUT
3IN– 4OUT
4IN–
2IN–
2
OUT
NC
TL064 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
The JFET-input operational amplifiers of the TL06_ series are designed as low-power versions of the TL08_
series amplifiers. They feature high input impedance, wide bandwidth, high slew rate, and low input offset and
input bias currents. The TL06_ series feature the same terminal assignments as the TL07_ and TL08_ series.
Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar
transistors in an integrated circuit.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C, and the M-suffix devices are characterized for operation over the full military
temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TAVIOMAX
AT 25°CPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
0C to 70 C
15 mV
PDIP (P)
T ube of 50
TL061CP TL061CP
0C to 70 C
15 mV
PDIP (P)
T ube of 50
TL062CP TL062CP
0C to 70 C
15 mV
PDIP (N) T ube of 25 TL064CN TL064CN
0C to 70 C
15 mV
SOIC (D)
T ube of 75 TL061CD
TL061C
0C to 70 C
15 mV
SOIC (D)
Reel of 2500 TL061CDR
TL061C
0C to 70 C
15 mV
SOIC (D)
T ube of 75 TL062CD
TL062C
0C to 70 C
15 mV
SOIC (D)
Reel of 2500 TL062CDR
TL062C
0C to 70 C
15 mV
T ube of 50 TL064CD
TL064C
0C to 70 C
15 mV
Reel of 2500 TL064CDR
TL064C
0C to 70 C
SOP (PS)
Reel of 2000
TL061CPSR T061
0C to 70 C
SOP (PS)
Reel of 2000
TL062CPSR T062
0C to 70 C
SOP (NS) Reel of 2000 TL064CNSR TL064
0C to 70 C
TSSOP (PW)
T ube of 150 TL062CPW
T062
0C to 70 C
TSSOP (PW)
Reel of 2000 TL062CPWR
T062
0C to 70 C
TSSOP (PW)
T ube of 90 TL064CPW
T064
0C to 70 C
Reel of 2000 TL064CPWR
T064
0
°
C to 70
°
C
6 mV
PDIP (P)
T ube of 50
TL061ACP TL061ACP
0°C to 70°C
6 mV
PDIP (P)
T ube of 50
TL062ACP TL062ACP
6 mV
PDIP (N) T ube of 25 TL064ACN TL064ACN
6 mV
SOIC (D)
T ube of 75 TL061ACD
061AC
6 mV
SOIC (D)
Reel of 2500 TL061ACDR
061AC
6 mV
SOIC (D)
T ube of 75 TL062ACD
062AC
SOIC (D)
Reel of 2500 TL062ACDR
062AC
T ube of 50 TL064ACD
TL064AC
Reel of 2500 TL064ACDR
TL064AC
SOP (PS)
Reel of 2000
TL061ACPSR T061A
SOP (PS)
Reel of 2000
TL062ACPSR T062A
3 mV
PDIP (P)
T ube of 50
TL061BCP TL061BCP
3 mV
PDIP (P)
T ube of 50
TL062BCP TL062BCP
3 mV
PDIP (N) T ube of 25 TL064BCN TL064BCN
3 mV
SOIC (D)
T ube of 75 TL062BCD
062BC
SOIC (D)
Reel of 2500 TL062BCDR
062BC
SOIC (D)
T ube of 50 TL064BCD
TL064BC
Reel of 2500 TL064BCDR
TL064BC
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION (continued)
TAVIOMAX
AT 25°CPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
–40 C to 85 C
6 mV
PDIP (P)
T ube of 50
TL061IP TL061IP
–40 C to 85 C
6 mV
PDIP (P)
T ube of 50
TL062IP TL062IP
–40 C to 85 C
6 mV
PDIP (N) T ube of 25 TL064IN TL064IN
–40 C to 85 C
6 mV
SOIC (D)
T ube of 75 TL061ID
TL061I
–40
°
C to 85
°
C
6 mV
SOIC (D)
Reel of 2000 TL061IDR
TL061I
SOIC (D)
T ube of 75 TL062ID
TL062I
SOIC (D)
Reel of 2000 TL062IDR
TL062I
T ube of 50 TL064ID
TL064I
Reel of 2500 TL064IDR
TL064I
–55 C to 125 C
6 mV
CDIP (JG) Tube of 50 TL062MJG TL062MJG
–55 C to 125 C
6 mV
LCCC (FK) T ube of 55 TL062MFK TL062MFK
–55
°
C to 125
°
C
9 mV
CDIP (J) T ube of 25 TL064MJ TL064MJ
9 mV
CFP (W) T ube of 150 TL064MW TL064MW
LCCC (FK) T ube of 55 TL064MFK TL064MFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
symbol (each amplifier)
+
–
IN+
IN– OUT
OFFSET N1
Offset Null/Compensation
TL061 Only
OFFSET N2
schematic (each amplifier)
IN+
50 Ω
100 Ω
C1
V
CC+
OUT VCC–
OFFSET N1
TL061 Only
OFFSET N2
IN–
C1 = 10 pF on TL061, TL062, and TL064
Component values shown are nominal.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
TL06_C
TL06_AC
TL06_BC TL06_I TL06_M UNIT
Supply voltage, VCC+ (see Note 1) 18 18 18 V
Supply voltage, VCC– (see Note 1) –18 –18 –18 V
Differential input voltage, VID (see Note 2) ±30 ±30 ±30 V
Input voltage, VI (see Notes 1 and 3) ±15 ±15 ±15 V
Duration of output short circuit (see Note 4) Unlimited Unlimited Unlimited
Package thermal impedance, (see Notes 5 and 6)
D (8-pin) package 97 97
C/W
Package thermal impedance, (see Notes 5 and 6)
D (14-pin) package 86 86
C/W
Package thermal impedance, (see Notes 5 and 6)
N package 80 80
C/W
Package thermal impedance, θJA (see Notes 5 and 6)
NS package 76 76 °
C/W
Package thermal impedance, θJA (see Notes 5 and 6)
P package 85 85
°C/W
PS package 95 95
PW (8-pin) package 149 149
PW (14-pin) package 113 113
Package thermal impedance, (see Notes 7 and 8)
FK package 5.61
C/W
Package thermal impedance, θJC (see Notes 7 and 8)
J package 15.05
°C/W
Package thermal impedance, θJC (see Notes 7 and 8)
JG package 14.5
°C/W
W package 14.65
Operating virtual junction temperature, TJ150 150 150 °C
Case temperature for 60 seconds FK package 260 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60
J, JG, U, or
300
°
C
Lead temperature 1,6 mm (1/16 inch) from case for 60
seconds
J, JG, U, or
W package
300
°C
Lead temperature 1,6 mm (1/6 inch) from case for 10
seconds
D, N, NS, P, PS,
or PW package
260
260
°C
Lead temperature 1,6 mm (1/6 inch) from case for 10
seconds
D, N, NS, P, PS,
or PW package
260
260
°C
Storage temperature range, Tstg –65 to 150 –65 to 150 –65 to 150 °C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to the midpoint between VCC+ and VCC–.
2. Differential voltages are at IN+ with respect to IN–.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) – TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
8. The package thermal impedance is calculated in accordance with MIL-STD-883.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC±= ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
†
TL061C
TL062C
TL064C
TL061AC
TL062AC
TL064AC
UNIT
MIN TYP MAX MIN TYP MAX
VIO
Input offset voltage
VO = 0,
TA = 25°C 3 15 3 6
mV
VIO
Input offset voltage
VO = 0,
RS =50 ΩTA = Full range 20 7.5
mV
αVIO Temperature coef ficient
of input offset voltage VO = 0, RS =50 Ω,
TA = Full range 10 10 µV/°C
IIO
Input offset current
VO = 0
TA = 25°C 5 200 5 100 pA
IIO
Input offset current
VO = 0
TA = Full range 5 3 nA
IIB
Input bias current‡
VO = 0
TA = 25°C 30 400 30 200 pA
IIB
Input bias current‡
VO = 0
TA = Full range 10 7 nA
VICR
Common-mode
TA = 25°C
±11
–12
to
±11
–12
to
V
VICR
Common-mode
input voltage range
TA = 25°C
±11
to
15
±11
to
15
V
VOM
Maximum peak output
RL = 10 kΩ, TA = 25°C±10 ±13.5 ±10 ±13.5
V
VOM
Maximum peak output
voltage swing RL ≥10 kΩ, TA = Full range ±10 ±10
V
AVD
Large-signal differential
VO =
±
10 V,
TA = 25°C 3 6 4 6
V/mV
AVD
Large-signal differential
voltage amplification
VO = 10 V,
RL ≥10 kΩTA = Full range 3 4
V/mV
B1Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz
riInput resistance TA = 25°C 1012 1012 Ω
CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0,
RS = 50 Ω, TA = 25°C70 86 80 86 dB
kSVR
Supply-voltage rejection ratio
V
CC
=
±
9 V to
±
15 V,
VO = 0, RS = 50 Ω
70
95
80
95
dB
kSVR
Supply-voltage rejection ratio
(∆VCC±/∆VIO)
VO = 0,
RS = 50 Ω
,
TA = 25°C
70
95
80
95
dB
PDTotal power dissipation
(each amplifier) VO = 0,
No load TA = 25°C, 6 7.5 6 7.5 mW
ICC Supply current
(each amplifier) VO = 0,
No load TA = 25°C, 200 250 200 250 µA
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB
†All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for
TA is 0°C to 70°C for TL06_C, TL06_AC, and TL06_BC and –40°C to 85°C for TL06_I.
‡Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in
Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC±= ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
†
TL061BC
TL062BC
TL064BC
TL061I
TL062I
TL064I
UNIT
MIN TYP MAX MIN TYP MAX
VIO
Input offset voltage
VO = 0,
TA = 25°C 2 3 3 6
mV
VIO
Input offset voltage
VO = 0,
RS =50 ΩTA = Full range 5 9
mV
αVIO Temperature coef ficient of
input offset voltage VO = 0, RS =50 Ω,
TA = Full range 10 10 µV/°C
IIO
Input offset current
VO = 0
TA = 25°C 5 100 5 100 pA
IIO
Input offset current
VO = 0
TA = Full range 3 10 nA
IIB
Input bias current‡
VO = 0
TA = 25°C 30 200 30 200 pA
IIB
Input bias current‡
VO = 0
TA = Full range 7 20 nA
VICR Common-mode
input voltage range TA = 25°C±11 –12
to
15 ±11 –12
to
15 V
VOM
Maximum peak output
RL = 10 kΩ, TA = 25°C±10 ±13.5 ±10 ±13.5
V
VOM
Maximum peak output
voltage swing RL ≥10 kΩ, TA = Full range ±10 ±10
V
AVD
Large-signal differential
VO =
±
10 V,
TA = 25°C 4 6 4 6
V/mV
AVD
Large-signal differential
voltage amplification
VO = 10 V,
RL ≥10 kΩTA = Full range 4 4
V/mV
B1Unity-gain bandwidth RL = 10 kΩ, TA = 25°C 1 1 MHz
riInput resistance TA = 25°C 1012 1012 Ω
CMRR Common-mode
rejection ratio VIC = VICRmin, VO = 0,
RS = 50 Ω, TA = 25°C80 86 80 86 dB
kSVR
Supply-voltage rejection ratio
V
CC
=
±
9 V to
±
15 V,
VO = 0, RS = 50 Ω
80
95
80
95
dB
kSVR
Supply-voltage rejection ratio
(∆VCC±/∆VIO)
VO = 0,
RS = 50 Ω
,
TA = 25°C
80
95
80
95
dB
PDTotal power dissipation
(each amplifier) VO = 0,
No load TA = 25°C, 6 7.5 6 7.5 mW
ICC Supply current
(each amplifier) VO = 0,
No load TA = 25°C, 200 250 200 250 µA
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB
†All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified. Full range for
TA is 0°C to 70°C for TL06_C, TL06_AC, and TL06_BC and –40°C to 85°C for TL06_I.
‡Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in
Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
TL061M
TL062M TL064M
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VO = 0,
TA = 25°C 3 6 3 9
mV
VIO
Input offset voltage
VO = 0,
RS =50 ΩTA = –55°C to 125°C 9 15
mV
αVIO Temperature coef ficient
of input offset voltage VO = 0, RS =50 Ω,
TA = –55°C to 125°C10 10 µV/°C
I
Input offset current
V = 0
TA = 25°C 5 100 5 100 pA
IIO
Input offset current
VO = 0
TA = –55°C 20* 20*
nA
IO
O
TA = 125°C 20 20
nA
I
‡
V = 0
TA = 25°C 30 200 30 200 pA
IIB
Input bias current
‡
VO = 0
TA = –55°C 50* 50*
nA
IB
Input bias current
O
TA = 125°C 50 50
nA
VICR Common-mode
input voltage range TA = 25°C±11.5 –12
to
15 ±11.5 –12
to
15 V
VOM
Maximum peak output
RL = 10 kΩ, TA = 25°C±10 ±13.5 ±10 ±13.5
V
VOM
Maximum peak output
voltage swing RL ≥10 kΩ, TA = –55°C to 125°C±10 ±10
V
AVD
Large-signal differential
VO =
±
10 V,
TA = 25°C 4 6 4 6
V/mV
AVD
Large-signal differential
voltage amplification
VO = 10 V,
RL ≥10 kΩTA = –55°C to 125°C 4 4
V/mV
B1Unity-gain bandwidth RL = 10 kΩ, TA = 25°C MHz
riInput resistance TA = 25°C 1012 1012 Ω
CMRR Common-mode
rejection ratio VIC= VICRmin, VO = 0,
RS =50 Ω, TA = 25°C80 86 80 86 dB
kSVR Supply-voltage rejection
ratio (∆VCC±/∆VIO)VCC= ±9 V to ±15 V, VO = 0,
RS =50 Ω, TA = 25°C80 95 80 95 dB
PDTotal power dissipation
(each amplifier) VO = 0,
No load TA = 25°C, 6 7.5 6 7.5 mW
ICC Supply current
(each amplifier) VO = 0,
No load TA = 25°C, 200 250 200 250 µA
VO1/VO2 Crosstalk attenuation AVD = 100, TA = 25°C 120 120 dB
* This parameter is not production tested.
†All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
‡Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in
Figure 15. Pulse techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
operating characteristics, VCC± = ±15 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR
Slew rate at unity gain (see Note 5)
V
I
= 10 V,
CL = 100 pF,
C and I suffix 1.5 3.5
V/µs
SR
Slew rate at unity gain (see Note 5)
CL = 100 pF,
RL = 10 kΩ,
See Figure 1 M suffix 2 3.5
V/
µ
s
trRise time
VI = 20 mV,
RL = 10 k
Ω, 0.2
µs
Overshoot factor
VI = 20 mV,
CL = 100 pF,
RL = 10 k ,
See Figure 1 10% µ
s
VnEquivalent input noise voltage RS = 20 Ω,f = 1 kHz 42 nV/√Hz
NOTE 5: Slew rate at –55°C to 125°C is 0.7 V/µs min.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VI
RL = 2 kΩ
+
–
CL = 100 pF
OUT
Figure 1. Unity-Gain Amplifier
VI
10 kΩ
1 kΩ
RLCL = 100 pF
+
–
OUT
Figure 2. Gain-of-10 Inverting Amplifier
N2
N1
100 kΩ
1.5 kΩ
VCC–
+
–
TL061
IN–
OUT
IN+
Figure 3. Input Offset-Voltage Null Circuit
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Maximum peak output voltage vs Supply voltage 4
Maximum peak output voltage vs Free-air temperature 5
Maximum peak output voltage vs Load resistance 6
Maximum peak output voltage vs Frequency 7
Differential voltage amplification vs Free-air temperature 8
Large-signal dif ferential voltage amplification vs Frequency 9
Phase shift vs Frequency 9
Supply current vs Supply voltage 10
Supply current vs Free-air temperature 11
Total power dissipation vs Free-air temperature 12
Common-mode rejection ratio vs Free-air temperature 13
Normalized unity-gain bandwidth vs Free-air temperature 14
Normalized slew rate vs Free-air temperature 14
Normalized phase shift vs Free-air temperature 14
Input bias current vs Free-air temperature 15
Voltage-follower large-signal pulse response vs T ime 16
Output voltage vs Elapsed time 17
Equivalent input noise voltage vs Frequency 18
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 4
0
0
VOM – Maximum Peak Output Voltage – V
|VCC±| – Supply Voltage – V
±2.5
±5
±7.5
±10
±12.5
±15
246810121416
RL = 10 kΩ
TA = 25°C
See Figure 2
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
VOM
Figure 5
–75
0
VOM – Maximum Peak Output Voltage – V
TA – Free-Air Temperature – °C
±2.5
±5
±7.5
±10
±12.5
±15
–50 –25 0 25 50 75 100 125
VCC± = ±15 V
RL = 10 kΩ
See Figure 2
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
VOM
Figure 6
See Figure 2
TA = 25°C
VCC± = ±15 V
0100
VOM – Maximum Peak Output Voltage – V
RL – Load Resistance – Ω
1 k 10
k
±2.5
±5
±7.5
±10
±12.5
±15
200 400 700 2 k 4 k 7 k
MAXIMUM PEAK OUTPUT VOLTAGE
vs
LOAD RESISTANCE
ÁÁ
ÁÁ
VOM
VCC± = ±12 V
VCC± = ±5 V
f – Frequency – Hz
1 k
0
VOM – Maximum Peak Output Voltage – V
10 k 100 k 1 M 10 M
±2.5
±5
±7.5
±10
±12.5
±15
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
RL = 10 kΩ
TA = 25°C
See Figure 2
ÁÁ
ÁÁ
ÁÁ
VOM
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
Figure 7
†Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
– Differential Voltage Amplification – V/mV
AVD
RL = 10 kΩ
VCC± = ±15 V
1–75 TA – Free-Air Temperature – °C
–50 –25 0 25 50 75 100 125
2
4
10
7
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
Figure 8
AVD
(left scale)
1
0.001
f – Frequency – Hz
10 100 1 k 10 k 100 k 1 M 10 M
0.01
0.1
1
10
100
Phase Shift
135°
90°
180°
45°
0°
VCC± = ±15 V
Rext = 0
RL = 10 kΩ
TA = 25°C
Phase Shift
(right scale)
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
– Large-Signal Differential
AVD
Voltage Amplification – V/mV
Figure 9
†Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 10
TA = 25°C
No Signal
No Load
0
0
246810121416
50
100
150
200
250
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
|VCC±| – Supply Voltage – V
ICC – Supply Current –
Á
Á
Á
I
CC µ
A
±
Figure 11
–75
0
ICC – Supply Current –
TA – Free-Air Temperature – °C
50
100
150
200
250
–50 –25 0 25 50 75 100 125
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
ÁÁ
ICC µA
±
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC± = ±15 V
No Signal
No Load
Figure 12
–75
0
TA – Free-Air Temperature – °C
5
10
15
20
25
30
–50 –25 0 25 50 75 100 125
VCC± = ±15 V
No Signal
No Load
TL064
TL062
TL061
TOTAL POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
PD – Total Power Dissipation – mW
ÁÁ
ÁÁ
PD
Figure 13
81
CMRR – Common-Mode Rejection Ratio – dB
1251007550250–25–50
TA – Free-Air Temperature – °C
–75
82
83
84
85
86
87 VCC± = ±15 V
RL = 10 kΩ
ALL EXCEPT TL06_C
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
†Data at high and low temperatures are applicable only within the specified operating free-air temperature ranges of the various devices.
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0.7
Normalized Unity-Gain Bandwidth and Slew Rate
125
1007550250–25–50 TA – Free-Air Temperature – °C
–75
0.8
0.9
1
1.1
1.2
1.3
1.02
1.01
1
0.99
0.98
0.97
Normalized Phase Shift
1.03
VCC± = ±15 V
RL = 10 kΩ
f = B1 for Phase Shift
Unity-Gain Bandwidth
(left scale) Phase Shift
(right scale)
Slew Rate
(left scale)
NORMALIZED UNITY-GAIN BANDWIDTH,
SLEW RATE, AND PHASE SHIFT
vs
FREE-AIR TEMPERATURE
Figure 14
1251007550250–25
0.01
IIB – Input Bias Current – nA
–50 TA – Free-Air Temperature – °C
0.04
0.1
0.4
1
4
10
40
100
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
ÁÁÁÁÁ
VCC± = ±15 V
ÁÁ
ÁÁ
IIB
Figure 15 Figure 16
–6
Input and Output Voltages – V
t – Time – µs
Input
Output
VCC± = ±15 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
0246810
–4
–2
0
2
4
6
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
vs
TIME
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
–4
– Output Voltage – mV
t – Elapsed Time – µs
0 0.2 0.4 0.6 0.8 1 1.2 1.4
0
4
8
12
16
20
24
28
VCC± = ±15 V
RL = 10 kΩ
TA = 25°C
10%
tr
Overshoot
90%
OUTPUT VOLTAGE
vs
ELAPSED TIME
VO
0
Vn – Equivalent Input Noise Voltage –
f – Frequency – Hz
10
20
30
40
50
60
70
80
90
100
10 40 100 400 1 k 4 k 10 k 40 k 100 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC± = ±15 V
RS = 20 Ω
TA = 25°C
ÁÁ
ÁÁ
VnnV/ Hz
Figure 18
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table of Application Diagrams
APPLICATION DIAGRAM PART
NUMBER FIGURE
Instrumentation amplifier TL064 19
0.5-Hz square-wave oscillator TL061 20
High-Q notch filter TL061 21
Audio-distribution amplifier TL064 22
Low-level light detector preamplifier TL061 23
AC amplifier TL061 24
Microphone preamplifier with tone control TL061 25
Instrumentation amplifier TL062 26
IC preamplifier TL062 27
+
–
–
+
+
–
+
–
TL064
VCC+
VCC–
100 kΩ
Input B
10 kΩ
0.1% 0.1%
10 kΩ
VCC–
VCC+
TL064
Input A
VCC+
TL064
VCC–
100 kΩ
10 kΩ
0.1% 10 kΩ
0.1%
TL064
VCC–
VCC+
100 kΩ
100 kΩ
Output
1 MΩ
Figure 19. Instrumentation Amplifier
TL061
+
–
–15 V
15 V Output
1 kΩ
9.1 kΩ
3.3 kΩ
CF = 3.3 µF
RF = 100 kΩ
3.3 kΩ
f
+
1
2
p
RF
CF
Figure 20. 0.5-Hz Square-Wave Oscillator
TL061
+
–
R2
R1
C1 C2
R3
C3 VCC–
VCC+
OutputInput
C1
+
C2
+
C3
2
+
110 pF
fo
+
1
2
p
R1
C1
+
1kHz
R1 = R2 = 2 × R3 = 1.5 MΩ
Figure 21. High-Q Notch Filter
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
+
–
+
–
TL064 Output C
VCC+
VCC+
Output B
TL064
–
+
VCC+
Output A
TL064
–
+
VCC+
TL064
VCC+
100 kΩ
100 µF
Input
1 µF
1 MΩ
100 kΩ
100 kΩ
Figure 22. Audio-Distribution Amplifier
+
–
TIL601
10 kΩ
15 V
Output
–15 V
5 kΩ
100 pF TL061
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Figure 23. Low-Level Light Detector Preamplifier
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TL061
N2
+
–
0.1 µF10 kΩ
50 Ω
250 kΩ
N1
Output
1 MΩ
VCC+
10 kΩ
10 kΩ
0.1 µF
Figure 24. AC Amplifier
1.2 MΩ100 kΩ
20 µF
+
–
0.1 µF
47 kΩTL061
2.7 kΩ
270 Ω0.003 µF 0.001 µF
0.002 µF
1 µF
10 kΩ
100 kΩ
50 kΩ
0.06 µF
50 kΩ
10 kΩ100 kΩ1 kΩ
0.06 µF
10 kΩ
0.02 µF
100 kΩ
+
Figure 25. Microphone Preamplifier With Tone Control
IN–
IN+
100 kΩ
TL062
TL062
1 kΩ
1 kΩ
100 kΩ
–
+
–
+Output
Figure 26. Instrumentation Amplifier
TL061, TL061A, TL061B, TL062, TL062A
TL062B, TL064, TL064A, TL064B
LOW-POWER JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS078H – NOVEMBER 1978 – REVISED AUGUST 2003
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TL062
220 kΩ
–
+
0.00375 µF
TL062
–
+
10 pF
68 kΩ
0.003 µF
0.03 µF
0.03 µF
10 kΩ3.3 kΩ
0.003 µF
VCC–
VCC+
Output
Input
VCC–
VCC+
10 pF
MIN
MAX
100 kΩ
Treble
MIN
MAX
100 kΩ
Bass
10 kΩ
10 kΩ
+
0.01 µF27 kΩ
100 Ω
Balance 100 Ω
50 pF
+
75 µF
47 µF
5 kΩ
Gain
47 kΩ
1 µF
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
TA = 25°C
VCC± = ±15 V
Max
Treble
Max Bass
200 10 k4 k2 k1 k40040 100
20
15
10
5
0
–5
–10
–15
–20
–25 20 k
25
f – Frequency – Hz
Voltage Amplification – dB
20
IC PREAMPLIFIER RESPONSE CHARACTERISTICS
ÁÁÁ
ÁÁÁ
Min
Treble
ÁÁÁ
ÁÁÁ
Min Bass
Figure 27. IC Preamplifier
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MCFP001A – JANUARY 1995 – REVISED DECEMBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
U (S-GDFP-F10) CERAMIC DUAL FLATPACK
4040179/B 03/95
0.080 (2,03)
0.250 (6,35)
0.019 (0,48)
4 Places
0.300 (7,62) MAX
0.045 (1,14)
0.008 (0,20)
0.050 (1,27)
0.015 (0,38)
0.005 (0,13) MIN
0.026 (0,66)
0.004 (0,10)
0.246 (6,10)
110
56
0.250 (6,35)
0.350 (8,89)0.350 (8,89)
0.250 (6,35)
0.050 (1,27)
Base and Seating Plane
0.280 (7,11)
0.230 (5,84)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
MECHANICAL DATA
MCFP002A – JANUARY 1995 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F14) CERAMIC DUAL FLATPACK
0.360 (9,14)
0.250 (6,35)
87
141
0.235 (5,97)
0.004 (0,10)
0.026 (0,66)
4 Places
0.015 (0,38)
0.045 (1,14)
0.335 (8,51)
0.008 (0,20)
0.045 (1,14)
Base and Seating Plane
0.005 (0,13) MIN
0.019 (0,48)
0.390 (9,91)
0.260 (6,60)
0.080 (2,03)
4040180-2/C 02/02
0.360 (9,14)
0.250 (6,35)
0.280 (7,11) MAX
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
MECHANICAL DATA
MLCC006B – OCTOBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
BB AC AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option 4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14) 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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