Quad, 12-Bit DAC
Voltage Output with Readback
DAC8412/DAC8413
FEATURES
+5 V to ±15 V operation
Unipolar or bipolar operation
True voltage output
Double-buffered inputs
Reset to minimum (DAC8413) or center scale (DAC8412)
Fast bus access time
Readback
APPLICATIONS
Automatic test equipment
Digitally controlled calibration
Servo controls
Process control equipment
FUNCTIONAL BLOCK DIAGRAM
DGND
A0
A1
CS
RESET
LDAC
12 I/O
PORT
CONTROL
LOGIC
DAT
A
I/O
R/W
INPUT
REG A
INPUT
REG B
INPUT
REG C
INPUT
REG D
OUTPUT
REG A
OUTPUT
REG B
OUTPUT
REG C
OUTPUT
REG D
DAC A
DAC B
DAC C
DAC D
V
LOGIC
V
DD
V
REFH
V
REFL
V
SS
V
OUTA
V
OUTB
V
OUTC
V
OUTD
00274-001
Figure 1.
GENERAL DESCRIPTION
The DAC8412/DAC8413 are quad, 12-bit voltage output
DACs with readback capability. Built using a complementary
BiCMOS process, these monolithic DACs offer the user very
high package density.
Output voltage swing is set by the two reference inputs VREFH
and VREFL. By setting the VREFL input to 0 V and VREFH to a
positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with VREFH at 0 V and VREFL at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both VREFH and
VREFL to nonzero voltages. This method of setting output voltage
range has advantages over other bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.
Digital controls allow the user to load or read back data from any
DAC, load any DAC, and transfer data to all DACs at one time.
An active low RESET loads all DAC output registers to midscale
for the DAC8412 and zero scale for the DAC8413.
The DAC8412/DAC8413 are available in 28-lead plastic DIP,
28-lead ceramic DIP, 28-lead PLCC, and 28-lead LCC packages.
They can be operated from a wide variety of supply and reference
voltages with supplies ranging from single +5 V to ±15 V, and
references from +2.5 V to ±10 V. Power dissipation is less than
330 mW with ±15 V supplies and only 60 mW with a +5 V supply.
For MIL-STD-883 applications, contact your local Analog
Devices, Inc. sales office for the DAC8412/DAC8413/883 data
sheet, which specifies operation over the −55°C to +125°C
temperature range. All 883 parts are also available on Standard
Military Drawings 5962-91 76401MXA through 76404M3A.
DIGITAL INPUT CODE (Decimal)
0.500
0.125
512
LINEARITY ERROR (LSB)
0.375
–0.125
–0.250
–0.375
–0.500
0.250
0
+125°C
+25°C
–55°C
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = –55°C, +25°C, +125°C
1024 1536 2046 2548 2560 3072 40960
00274-002
Figure 2. INL vs. Code Over Temperature
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
DAC8412/DAC8413
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 14
Introduction ................................................................................ 14
DACs ............................................................................................ 14
Glitch ............................................................................................ 14
Reference Inputs ......................................................................... 14
Digital I/O ................................................................................... 14
Coding ......................................................................................... 14
Supplies ........................................................................................ 15
Amplifiers .................................................................................... 15
Reference Configurations .......................................................... 16
Single +5 V Supply Operation .................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/09—Rev. E to Rev. F
Updated Figure Numbering .............................................. Universal
Removed Figure 7 ............................................................................. 6
Changes to Ordering Guide .......................................................... 20
6/07—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added CERDIP Package .................................................... Universal
Changes to Specifications Section .................................................. 3
Changes to Absolute Maximum Ratings Section ......................... 7
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 20
3/00—Rev. C to Rev. D
DAC8412/DAC8413
Rev. F | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = +15.0 V, VSS = −15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = −10.0 V,−40°C ≤ TA ≤ +85°C, unless otherwise noted.1
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
ACCURACY
Integral Nonlinearity Error INL E grade ±0.25 ±0.5 LSB
F grade ±1 LSB
Differential Nonlinearity Error DNL Monotonic over temperature −1 LSB
Min-Scale Error VZSE R
L = 2 kΩ ±2 LSB
Full-Scale Error VFSE R
L = 2 kΩ ±2 LSB
Min-Scale Temperature Coefficient TCVZSE R
L = 2 kΩ 15 ppm/°C
Full-Scale Temperature Coefficient TCVFSE RL = 2 kΩ 20 ppm/°C
Linearity Matching Adjacent DAC Matching ±1 LSB
REFERENCE
Positive Reference Input Voltage Range2 VREFL + 2.5 VDD − 2.5 V
Negative Reference Input Voltage Range2
−10 VREFH − 2.5 V
Reference High Input Current IREFH −2.75 +1.5 +2.75 mA
Reference Low Input Current IREFL 0 2 2.75 mA
Large Signal Bandwidth BW −3 dB, VREFH = 0 V to 10 V p-p 160 kHz
AMPLIFIER CHARACTERISTICS
Output Current IOUT RL = 2 kΩ, CL = 100 pF –5 +5 mA
Settling Time tS To 0.01%, 10 V step, RL = 1 kΩ 10 μs
Slew Rate SR 10% to 90% 2.2 V/μs
Analog Crosstalk 72 dB
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH TA = 25°C 2.4 V
Logic Input Low Voltage VINL T
A = 25°C 0.8 V
Logic Output High Voltage VOH IOH = 0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = −1.6 mA 0.4 V
Logic Input Current IIN 1 μA
Input Capacitance CIN 8 pF
Digital Feedthrough3 V
REFH = 2.5 V, VREFL = 0 V 5 nV-sec
LOGIC TIMING CHARACTERISTICS3, 4
Chip Select Write Pulse Width tWCS 80 ns
Write Setup tWS t
WCS = 80 ns 0 ns
Write Hold tWH tWCS = 80 ns 0 ns
Address Setup tAS 0 ns
Address Hold tAH 0 ns
Load Setup tLS 70 ns
Load Hold tLH 30 ns
Write Data Setup tWDS tWCS = 80 ns 20 ns
Write Data Hold tWDH t
WCS = 80 ns 0 ns
Load Data Pulse Width tLDW 170 ns
Reset Pulse Width tRESET 140 ns
Chip Select Read Pulse Width tRCS 130 ns
Read Data Hold tRDH t
RCS = 130 ns 0 ns
Read Data Setup tRDS tRCS = 130 ns 0 ns
Data to High-Z tDZ C
L = 10 pF 200 ns
Chip Select to Data tCSD CL = 100 pF 160 ns
DAC8412/DAC8413
Rev. F | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 14.25 V ≤ VDD ≤ 15.75 V 150 ppm/V
Positive Supply Current IDD V
REFH = 2.5 V 8.5 12 mA
Negative Supply Current ISS −10 −6.5 mA
Power Dissipation PDISS 330 mW
1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.
2 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
3 All parameters are guaranteed by design.
4 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
VDD = VLOGIC = +5.0 V ± 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, VSS = –5.0 V ± 5%, VREFL = −2.5 V, −40°C ≤ TA ≤ +85°C,
unless otherwise noted.1
Table 2.
Parameter Symbol Conditions Min Typ Max Units
ACCURACY
Integral Nonlinearity Error INL E grade ±0.5 ±1 LSB
F grade ±2 LSB
V
SS = 0.0 V, E grade2 ±2 LSB
V
SS = 0.0 V, F grade2
±4 LSB
Differential Nonlinearity Error DNL Monotonic over temperature –1 LSB
Min-Scale Error VZSE VSS = −5.0 V ±4 LSB
Full-Scale Error VFSE VSS = −5.0 V ±4 LSB
Min-Scale Error VZSE VSS = 0.0 V ±8 LSB
Full-Scale Error VFSE V
SS = 0.0 V ±8 LSB
Min-Scale Temperature Coefficient TCVZSE 100 ppm/°C
Full-Scale Temperature Coefficient TCVFSE 100 ppm/°C
Linearity Matching Adjacent DAC matching ±1 LSB
REFERENCE
Positive Reference Input Voltage Range3 VREFL + 2.5 VDD − 2.5 V
Negative Reference Input Voltage Range VSS = 0.0 V 0 VREFH − 2.5 V
V
SS = −5.0 V –2.5 VREFH − 2.5 V
Reference High Input Current IREFH Code 0x000 –1.0 +1.0 mA
Large Signal Bandwidth BW −3 dB, VREFH = 0 V to 2.5 V p-p 450 kHz
AMPLIFIER CHARACTERISTICS
Output Current IOUT RL = 2 kΩ, CL = 100 pF –1.25 +1.25 mA
Settling Time tS To 0.01%, 2.5 V step, RL = 1 kΩ 7 μs
Slew Rate SR 10% to 90% 2.2 V/μs
LOGIC CHARACTERISTICS
Logic Input High Voltage VINH TA = 25°C 2.4 V
Logic Input Low Voltage VINL TA = 25°C 0.8 V
Logic Output High Voltage VOH IOH = 0.4 mA 2.4 V
Logic Output Low Voltage VOL IOL = −1.6 mA 0.45 V
Logic Input Current IIN 1 μA
Input Capacitance CIN 8 pF
LOGIC TIMING CHARACTERISTICS4, 5
Chip Select Write Pulse Width tWCS 150 ns
Write Setup tWS tWCS = 150 ns 0 ns
Write Hold tWH tWCS = 150 ns 0 ns
Address Setup tAS 0 ns
Address Hold tAH 0 ns
Load Setup tLS 70 ns
Load Hold tLH 50 ns
DAC8412/DAC8413
Rev. F | Page 5 of 20
Parameter Symbol Conditions Min Typ Max Units
Write Data Setup tWDS tWCS = 150 ns 20 ns
Write Data Hold tWDH tWCS = 150 ns 0 ns
Load Data Pulse Width tLDW 180 ns
Reset Pulse Width tRESET 150 ns
Chip Select Read Pulse Width tRCS 170 ns
Read Data Hold tRDH tRCS = 170 ns 20 ns
Read Data Setup tRDS tRCS = 170 ns 0 ns
Data to High-Z tDZ C
L = 10 pF 200 ns
Chip Select to Data tCSD CL = 100 pF 320 ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity PSS 100 ppm/V
Positive Supply Current IDD 7 12 mA
Negative Supply Current ISS VSS = −5.0 V −10 mA
Power Dissipation PDISS VSS = 0 V 60 mW
V
SS = −5.0 V 110 mW
1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V.
2 For single-supply operation only (VREFL = 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.
3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4 All parameters are guaranteed by design.
5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
CS
A
0/A1
t
RDS
t
RCS
t
RDH
t
AS
t
AH
t
DZ
t
CSD
R/W
DATA
OUT DATA VALID
HIGH-Z HIGH-Z
00274-003
Figure 3. Data Output (Read Timing)
A0/A1
RESET
LDAC
t
WCS
R/W
CS
DATA IN
t
WS
t
WH
t
AS
t
AH
t
LS
t
LH
t
WDH
t
WDS
t
LDW
t
RESET
00274-004
Figure 4. Data Write (Input and Output Registers) Timing
DAC8412/DAC8413
Rev. F | Page 6 of 20
A
DDRESS
80ns
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
R/W
CS
DATA IN
LDAC
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tWS
tAS
tLS
tWDS
tWH
tLH
tWDH
00274-005
ADDRESS
ONE
Figure 5. Single-Buffer Mode
CS
R/W
A
DDRESS
LDAC
DATA IN
80ns
t
WS
t
AS
t
LS
t
LH
t
LDW
t
WDH
t
WH
t
WDS
DATA1
VALID DATA2
VALID
DATA3
VALID
DATA4
VALID
00274-006
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
Figure 6. Double-Buffer Mode
DAC8412/DAC8413
Rev. F | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 3.
Parameter Rating
VSS to VDD −0.3 V, +33.0 V
VSS to VLOGIC −0.3 V, +33.0 V
VLOGIC to DGND −0.3 V, +7.0 V
VSS to VREFL −0.3 V, +VSS − 2.0 V
VREFH to VDD +2.0 V, +33.0 V
VREFH to VREFL +2.0 V, VSS − VDD
Current into Any VSS pin ±15 mA
Digital Input Voltage to DGND −0.3 V, VLOGIC + 0.3 V
Digital Output Voltage to DGND −0.3 V, +7.0 V
Operating Temperature Range
EP, FP, FPC −40°C to +85°C
AT, BT, BTC −55°C to +125°C
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Power Dissipation Package 1000 mW
Lead Temperature JEDEC Industry Standard
Soldering J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case mounting conditions, that is, a
device in socket.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
28-Lead Plastic DIP (PDIP) 48 22 °C/W
28-Terminal Ceramic Leadless Chip Carrier (LLC) 70 28 °C/W
28-Lead Plastic Leaded Chip Carrier (PLLC) 63 25 °C/W
28-Lead Ceramic Dual In-Line Package (CERDIP) 51 9 °C/W
ESD CAUTION
DAC8412/DAC8413
Rev. F | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
REFH 1
V
OUTB 2
V
OUTA 3
V
SS 4
V
REFL
28
V
OUTC
27
V
OUTD
26
V
DD
25
DGND
5
RESET
6
LDAC
7
V
LOGIC
24
CS
23
A0
22
DB0 (LSB)
8
A1
21
DB1
9
R/W
20
DB2
10
DB11 (MSB)
19
DB3
11
DB10
18
DB4
12
DB9
17
DB5
13
DB8
16
DB6
14
DB7
15
00274-008
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
1282726234
5
6
7
8
9
10
25
24
23
22
21
20
11 19
DGND
RESET
LDAC
DB0 (LSB)
DB1
DB2
V
DD
V
LOGIC
CS
A0
A1
R/W
V
SS
V
OUTA
V
OUTB
V
REFH
V
REFL
V
OUTC
V
OUTD
DB3 DB11 (MSB)
DB4
DB5
DB6
DB7
DB8
DB9
DB10
PIN 1
INDENTFIER
12 13 14 15 16 17 18
00274-009
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
00274-010
DAC8412/
DAC8413
TOP VIEW
(Not to Scale)
5
DGND
6
RESET
7
LDAC
8
DB0 (LSB)
9
DB1
10
DB2
11
DB3
25
V
DD
24
V
LOGIC
23
CS
22
A0
21
A1
20
R/W
19
DB11 (MSB)
26
V
OUTD
27
V
OUTC
28
V
REFL
1
V
REFH
2
V
OUTB
3
V
OUTA
4
V
SS
18
DB10
17
DB9
16
DB8
15
DB7
14
DB6
13
DB5
12
DB4
Figure 7. PDIP/CERDIP Figure 8. PLCC Figure 9. LCC
Table 5. Pin Function Descriptions
Pin Number Mnemonic Description
1 VREFH High-Side DAC Reference Input.
2 VOUTB DAC B Output.
3 VOUTA DAC A Output.
4 VSS Lower Rail Power Supply.
5 DGND Digital Ground.
6 RESET Reset Input and Output Registers to all 0s, Enabled at Active Low.
7 LDAC Load Data to DAC, Enabled at Active Low.
8 DB0 Data Bit 0, LSB.
9 DB1 Data Bit 1.
10 DB2 Data Bit 2.
11 DB3 Data Bit 3.
12 DB4 Data Bit 4.
13 DB5 Data Bit 5.
14 DB6 Data Bit 6.
15 DB7 Data Bit 7.
16 DB8 Data Bit 8.
17 DB9 Data Bit 9.
18 DB10 Data Bit 10.
19 DB11 Data Bit 11, MSB.
20 R/W Active Low to Write Data to DAC. Active high to readback previous data at data bit pins with VLOGIC connected to 5 V.
21 A1 Address Bit 1.
22 A0 Address Bit 0.
23 CS Chip Select, Enabled at Active Low.
24 VLOGIC Voltage Supply for Readback Function. Can be open circuit if not used.
25 VDD Upper Rail Power Supply.
26 VOUTD DAC D Output.
27 VOUTC DAC C Output.
28 VREFL Low-Side DAC Reference Input.
DAC8412/DAC8413
Rev. F | Page 9 of 20
2
TYPICAL PERFORMANCE CHARACTERISTICS
1
–1
6
0
11109871
MAXIMUM LINEARITY ERROR (LSB)
V
REFH
(V)
V
DD
= +15V
V
SS
= –15V
V
REFL
= –10V
T
A
= 25°C
00274-011
Figure 10. DNL vs. VREFH
1
–1
0
321
MAXIMUM LINEARITY ERROR (LSB)
VREFH (V)
V
DD
= 5V
V
SS
= 0V
V
REFL
= 0V
T
A
= 25°C
00274-014
Figure 11. INL vs. VREFH
0.4
–0.6 1000
–0.4
0
0
–0.2
0.2
200
T = HOURS OF OPERATION AT 125°C
400 600 800
FULL-SCALE ERROR (LSB)
X+3σ
X
X–3σ
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
00274-015
Figure 12. Full-Scale Error vs. Time Accelerated by Burn-in
0
–2
–1
2
1
321
MAXIMUM LINEARITY ERROR (LSB)
V
REFH
(V)
V
DD
= 5V
V
SS
= 0V
V
REFL
= 0V
T
A
= 25°C
00274-012
Figure 13. DNL vs. VREFH
0.3
0.1
0.2
108612
MAXIMUM LINEARITY ERROR (LSB)
V
REFH
(V)
V
DD
= +15V
V
SS
= –15V
V
REFL
= 0V
T
A
= 25°C
00274-013
Figure 14. INL vs.VREFH
X+3σ
X
X–3σ
0.3
–0.7 1000
–0.5
0
–0.1
–0.3
0.1
200
T = HOURS OF OPERATION AT 125°C
400 600 800
ZERO-SCALE ERROR (LSB)
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
00274-016
Figure 15. Zero-Scale Error vs. Time Accelerated by Burn-In
DAC8412/DAC8413
Rev. F | Page 10 of 20
0.2
–0.6
–0.4
–75
0
–0.2
0
TEMPERATURE (°C)
75 150
FULL-SCALE ERROR (LSB)
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
DAC A
DAC D
DAC B
DAC C
00274-017
Figure 16. Full-Scale Error vs. Temperature
0.2
–0.6
–0.4
–75
0
–0.2
0
TEMPERATURE (°C)
75 150
ZERO-SCALE ERROR (LSB)
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
DAC A
DAC D
DAC C
DAC B
00274-018
Figure 17. Zero-Scale Error vs. Temperature
DIGITAL INPUT CODE (Decimal)
0.37500
0.08375
0512
LINEARITY ERROR (LSB)
0.26125
–0.09375
–0.18750
–0.23125
–0.37500
0.18750
0
1024 1536 2048 2560 3072 3584 4096
V
REFH
= 10V
V
REFL
= 0V
T
A
= 25°C
00274-019
Figure 18. Channel-to-Channel Matching (VSUPPLY = ±15 V)
1.00
0.25
LINEARITY ERROR (LSB)
0.75
–0.25
–0.50
–0.75
–1.00
0.50
0
DIGITAL INPUT CODE (Decimal)
0 512 1024 1536 2048 2560 3072 3584 4096
V
DD
= 5V
V
SS
= 0V
V
REFH
= 2.5V
T
A
= 25°C
00274-020
Figure 19. Channel-to-Channel Matching (VSUPPLY = +5 V/GND)
13
10
473
7
IDD (mA)
V
REFH
(V)
15913
V
DD
= +15V
V
SS
= –15V
V
REFL
= –10V
00274-021
Figure 20. IDD vs. VREFH (All DACs High)
DIGITAL INPUT CODE (Decimal)
0.500
0.125
512
LINEARITY ERROR (LSB)
0.375
–0.125
–0.250
–0.375
–0.500
0.250
0
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= –55°C, +25°C, +125°C
1024 1536 2048 2560 3072 3584 40960
00274-022
Figure 21. INL vs. Code
DAC8412/DAC8413
Rev. F | Page 11 of 20
–580ns
10
V
TRIG'D
0V
1µs/DIV
9.42µs
1V/DIV
EA
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-026
Figure 22. Positive Slew Rate
–1.96µs
15.5m
V
2mV/DIV
TRIG'D
–4.5mV
2µs/DIV
0
INPUT
–5V
5V/DIV
18.04µs
VDD = +15V
VSS = –15V
VREFH = +10V
VREFL = –10V
TA = 25°C
00274-025
Figure 23. Settling Time (Negative)
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
–1.96µs
32.5m
V
5mV/DIV
TRIG'D
–17.5mV
2µs/DIV
5V
INPUT
0
5V/DIV
18.04µs
1 LSB ERROR BAND
00274-024
Figure 24. Settling Time (Positive)
–580ns
10
V
T
RIG'D
0V
1µs/DIV 9.42µs
1V/DI
EA
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-027
Figure 25. Negative Slew Rate
2.0
0.5
1.5
–0.5
1.0
0
I
VREFH
(mA)
DIGITAL INPUT CODE (Decimal)
511 1023 1535 2047 2559 3071 3583 40950
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-023
Figure 26. IVREFH vs. Code
0.6
1.0
INL (LSB)
LOAD RESISTANCE (kΩ)
0.8
0.4
0.2
0
–0.2
0.01 0.1 1 10 100
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-028
Figure 27. INL vs. Load Resistance
DAC8412/DAC8413
Rev. F | Page 12 of 20
8
12
FULL-SCALE VOLTAGE (V)
LOAD RESISTANCE (kΩ)
10
6
4
2
0
0.01 0.1 1 10 100
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-029
Figure 28. Output Swing vs. Load Resistance
10M10 100k10k1k100
–10
0
–30
–50
–70
GAIN (dB)
FREQUENCY (Hz)
1M
0
V
DD
= +15V
V
SS
= –15V
V
REFH
= 0 ±100mV
V
REFL
= –10V
DATA BITS = +5V
200mV p-p
00274-030
Figure 29. Small Signal Response
TEMPERATURE (°C)
10
–10 150
–6
2
–2
6
750
POWER SUPPLY CURRENT (mA)
V
DD
= +15V
V
SS
= –15V
I
DD
I
SS
–75
00274-031
Figure 30. Power Supply Current vs. Temperature
10 100k10k1k100
60
80
40
20
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
1M
0
100
+PSRR:
V
DD
= +15V ±1Vp
V
SS
= –15V
–PSRR:
V
DD
= +15V
V
SS
= –15V ±1V
V
REFH
= +10V
ALL DATA 0
+PSRR
–PSRR
00274-032
Figure 31. PSRR vs. Frequency
0.10
10
NOISE DENSITY (µV)
NOISE FREQUENCY (Hz)
1
0.01
0.001
1 10 100 1k 10k
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-033
Figure 32. Noise Density vs. Noise Frequency
40
–40 25
–20
–30
–25 –20
0
–10
10
20
30
20151050–5–10–15
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
DATA = 0x000
V
OUT
(V)
I
OUT
(mA)
+I
SC
–I
SC
00274-034
Figure 33. IOUT vs. VOUT
DAC8412/DAC8413
Rev. F | Page 13 of 20
20µV/DIV M 200µs A CH1 12.9mV
1
CH1 MEAN
66.19µV
V
DD
= +15V
V
SS
= –15V
V
REFH
= +10V
V
REFL
= –10V
T
A
= 25°C
00274-035
Figure 34. Broadband Noise
6–6
5
25
15
–5
–15
–25
20
10
0
–10
–20
–4 –2 0 2 4
V
DD
= +15V
V
SS
= 0V
V
REFH
= +10V
V
REFL
= 0V
T
A
= 25°C
DATA = 0x800
V
OUT
(V)
I
OUT
(mA)
+I
SC
–I
SC
00274-036
Figure 35. IOUT vs. VOUT
CH2 1.86V
2
1
1V 4µs
1V
10µs
GLITCH AT DAC OUTPUT
DEGLITCHER OUTPUT
00274-037
Figure 36. Glitch and Deglitched Results
DAC8412/DAC8413
Rev. F | Page 14 of 20
THEORY OF OPERATION
INTRODUCTION
The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel
input DACs featuring a 12-bit data bus with readback capability.
The only differences between the DAC8412/DAC8413 are the
reset functions. The DAC8412 resets to midscale (Code 0x800),
and the DAC8413 resets to minimum scale (Code 0x000).
The ability to operate from a single 5 V supply is a unique
feature of these DACs.
Operation of the DAC8412/DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital-to-analog converters, and the
output amplifiers.
DACS
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either VREFH or VREFL.
GLITCH
Worst-case glitch occurs at the transition between Half-Scale
Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V μs (see Figure 36).
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit (see
Figure 37). When CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad
sample-and-hold amplifier, SMP04, has been used to illustrate
the deglitching result (see ). Figure 36
S/H
CS
DACOUT1
DACOUT
DACOUT
DACOUT1
S/H
HSH
00274-038
S
Figure 37. Data Output (Read Timing)
REFERENCE INPUTS
All four DACs share common reference high (VREFH) and reference
low (VREFL) inputs. The voltages applied to these reference inputs set
the output high and low voltage limits of all four of the DACs.
Each reference input has voltage restrictions with respect to the
other reference and to the power supplies. The VREFL can be set at
any voltage between VSS and VREFH − 2.5 V, and VREFH can be set to
any value between +VDD − 2.5 V and VREFL + 2.5 V. Note that
because of these restrictions, the DAC8412 references cannot be
inverted (that is, VREFL cannot be greater than VREFH).
It is important to note that the DAC8412 VREFH input both sinks
and sources current. In addition, the input current of both VREFH
and VREFL are code-dependent. Many references have limited
current-sinking capability and must be buffered with an
amplifier to drive VREFH. The VREFL has no such special
requirements.
It is recommended that the reference inputs be bypassed with
0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.
DIGITAL I/O
See Table 6 for the digital control logic truth table. Digital I/O
consists of a 12-bit bidirectional data bus, two registers select
inputs, A0 and A1, a R/W input, a RESET input, a chip select (CS),
and a load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Digital
data bits are labeled with the MSB defined as Data Bit 11 and the
LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.
Table 6.
See Figure 38 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers A
(Binary Code 00) through D (Binary Code 11). Decoding of the
registers is enabled by the CS input. When CS is high, no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous LDAC input. By
taking LDAC low while CS is enabled, all output registers can
be updated simultaneously. Note that the tLDW required pulse
width for updating all DACs is a minimum of 170 ns.
The R/W input, when enabled by CS, controls the writing to
and reading from the input register.
CODING
Both DAC8412/DAC8413 use binary coding. The output
voltage can be calculated by
4096
)( NVV
VV REFLREFH
REFL
OUT
×
−
+=
where N is the digital code in decimal.
DAC8412/DAC8413
Rev. F | Page 15 of 20
RESET
The RESET function can be used either at power-up or at any
time during DAC operation. The RESET function is independent
of CS. This pin is active low and sets the DAC output registers
to either center code for the DAC8412, or zero code for the
DAC8413. The reset-to-center code is most useful when the
DAC is configured for bipolar references and an output of 0 V
after reset is desired.
SUPPLIES
Supplies required are VSS, VDD, and VLOGIC. The VSS supply can
be set between −15 V and 0 V. VDD is the positive supply; its
operating range is between 5 V and 15 V.
VLOGIC is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device. If
the readback function is not being used, VLOGIC can be left open-
circuit. While VLOGIC does not supply current to the DAC8412, it
does supply currents to the digital outputs when readback is used.
AMPLIFIERS
Unlike many voltage output DACs, the DAC8412 features buffered
voltage outputs. Each output is capable of both sourcing and
sinking 5 mA at ±10 V, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Table 6. DAC8412/DAC8413 Logic Table
A1 A0 R/W CS RS LDAC Input Register Output Register Mode
DAC
L L L L H L Write Write Transparent A
L H L L H L Write Write Transparent B
H L L L H L Write Write Transparent C
H H L L H L Write Write Transparent D
L L L L H H Write Hold Write input A
L H L L H H Write Hold Write input B
H L L L H H Write Hold Write input C
H H L L H H Write Hold Write input D
L L H L H H Read Hold Read input A
L H H L H H Read Hold Read input B
H L H L H H Read Hold Read input C
H H H L H H Read Hold Read input D
X X X H H L Hold Update all output registers All
X X X H H H Hold Hold Hold All
X X X X L X All registers reset to midscale/zero-scale1 All
X X X H X All registers latched to midscale/zero-scale1 All
1 DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.
DAC8412/DAC8413
Rev. F | Page 16 of 20
WRDB0
WRDB1
WRDB2
WRDB3
WRDB4
WRDB5
WRDB6
WRDB7
WRDB8
WRDB9
WRDB10
RDDACB
RDDACA
WRDACA
WRDACB
RDDACC
WRDACC
RDDACD
WRDACD
READBACKDATAIN_DB10
READOUT
READOUTBAR
READBACKDATAIN_DB11
A1
A0
DGND
R/W
DB11..DB0
V
LOGIC
CS DAC A
DAC B
DAC C
DAC D
WRDB11
INPUT
REGISTER
OUTPUT
REGISTER
V
REFL
V
OUTD
V
OUTC
V
OUTA
V
OUTB
RESE
T
LDAC
V
REFH
V
DD
V
SS
READBACK
DATAOUT_DB11
00274-039
Figure 38. Simplified I/O Logic Diagram
Careful attention to grounding is important for accurate
operation of the DAC8412. This is not because the DAC8412 is
more sensitive than other 12-bit DACs, but because with four
outputs and two references, there is greater potential for ground
loops. Because the DAC8412 has no analog ground, the ground
must be specified with respect to the reference.
REFERENCE CONFIGURATIONS
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either positive or
negative voltage output, and the bipolar configuration can be
either symmetrical or nonsymmetrical.
REF10
+15
V
INPUT
OUTPUT
TRIM 10kΩ
0.2µF
+10V OPERATION
+
+15V
OP400
–15V
V
REFL
V
REFH
DAC8412
OR
DAC8413
0.1µF
//10µF
V
DD
V
SS
00274-040
Figure 39. Unipolar +10 V Operation
+15V
1µF
0.2µF
39kΩ
6.2Ω
6.2Ω
0.2µF
+15V
GAIN
100kΩ
BALANCE
100kΩ
AD688 FOR ±10V
AD588 FOR ±5V
V
DD
V
SS
V
REFL
V
REFH
DAC8412
OR
DAC8413
0.1µF
//10µF
–15V
±5 OR ±10V OPERATION
00274-041
Figure 40. Symmetrical Bipolar Operation
Figure 40 (symmetrical bipolar operation) shows the DAC8412
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of reference operation. Adjustments may not be
required for many applications since the AD688 is a very high
accuracy reference. However, if additional adjustments are
required, adjust the DAC8412 full scale first. Begin by loading
the digital full-scale code (0xFFF), and then adjust the gain
adjust potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the balance adjust to set the center-scale output
voltage to 0.000 V.
DAC8412/DAC8413
Rev. F | Page 17 of 20
The 0.2 μF bypass capacitors shown at the reference inputs in
Figure 40 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 μF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier keeps the amplifier
from oscillating with the capacitive load. This 6.2 Ω resistor has
been found to be large enough to stabilize this circuit. Larger
resistor values are acceptable, provided that the drop across the
resistor does not exceed VBE. Assuming a minimum VBE of 0.6 V
and a maximum current of 2.75 mA, then the resistor should be
under 200 Ω for the loading of a single DAC8412.
Using two separate references is not recommended. Having two
references can cause different drifts with time and temperature;
whereas with a single reference, most drifts track.
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown in
Figure 41. In this configuration, the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.
10k
Ω
0.01µF
10µF
–15V
GND
TRIM
OUTPUT
REF08
0.2µF
V
REFL
V
REFH
DAC8412
OR
DAC8413
0.1µF
//10µF
ZERO TO –10V OPERATION
V
DD
V
SS
00274-042
Figure 41. Unipolar –10 V Operation
Figure 41 shows the DAC8412 configured for –10 V to 0 V
operation. A REF08 with a –10 V output is connected directly
to VREFL for the reference voltage.
SINGLE +5 V SUPPLY OPERATION
For operation with a 5 V supply, the reference voltage should be
set between 1.0 V and 2.5 V for optimum linearity. Figure 42
shows a REF43 used to supply a 2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a 5 V supply with ±5% tolerance. VDD and VLOGIC should be
connected to the same supply. Separate bypassing to each pin
should also be used.
5
V
INPUT
OUTPUT
GND
TRIM
REF43
ZERO TO 2.5V OPERATION
SINGLE 5V SUPPLY
10kΩ
0.2µF
V
REFL
V
REFH
DAC8412
OR
DAC8413
0.1µF
//10µF
10µF 0.01µF
V
DD
V
SS
00274-043
Figure 42. +5 V Single-Supply Operation
DAC8412/DAC8413
Rev. F | Page 18 of 20
OUTLINE DIMENSIONS
1
28
5
11
18
BOTTON
VIEW
19 25
26
412
0.15 (3.81)
REF
0.075
(1.91)
REF
0.028 (0.71)
0.022 (0.56)
0.300 (7.62)
REF
0.055 (1.40)
0.045 (1.14)
0.075 (1.91)
REF
0.020 (0.51)
MIN
0.05 (1.27)
0.095 (2.41)
0.075 (1.90)
0.458 (11.63)
0.442 (11.23) SQ
0.458
(11.63)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
022106-A
Figure 43. 28-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-28-1)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
COMPLIANT TO JEDEC STANDARDS MS-011
071006-A
0.100 (2.54)
BSC
1.565 (39.75)
1.380 (35.05)
0.580 (14.73)
0.485 (12.31)
0.022 (0.56)
0.014 (0.36)
0.200 (5.08)
0.115 (2.92)
0.070 (1.78)
0.050 (1.27)
0.250 (6.35)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
0.625 (15.88)
0.600 (15.24)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.125 (3.17)
28
114
15
Figure 44. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
DAC8412/DAC8413
Rev. F | Page 19 of 20
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
4
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.495 (12.57)
0.485 (12.32) SQ
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.120 (3.04)
0.090 (2.29)
0.056 (1.42)
0.042 (1.07) 0.020 (0.51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
042508-A
Figure 45. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
28
114
15
0.610 (15.49)
0.500 (12.70)
0.005 (0.13)
MIN
0.100 (2.54)
MAX
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
MIN
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
PIN 1
030106-A
Figure 46. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28-2)
Dimensions shown in inches and (millimeters)
DAC8412/DAC8413
Rev. F | Page 20 of 20
ORDERING GUIDE
Model Temperature Range INL Package Description Package Option
DAC8412AT/883C −55°C to +125°C ±0.75 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8412BT/883C −55°C to +125°C ±1.5 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8412BTC/883C −55°C to +125°C ±1.5 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1
DAC8412EP1−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8412EPZ1, 2
−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8412FP1
−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8412FPC1
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8412FPC-REEL1
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8412FPCZ1, 2
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8412FPCZ-REEL1, 2
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8412FPZ1, 2
−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8413AT/883C −55°C to +125°C ±0.75 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8413BT/883C −55°C to +125°C ±1.5 28-Lead Ceramic Dual In-Line Package [CERDIP] Q-28-2
DAC8413BTC/883C −55°C to +125°C ±1.5 28-Terminal Ceramic Leadless Chip Carrier [LCC] E-28-1
DAC8413EP1
−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8413EPZ1, 2
−40°C to +85°C ±0.5 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8413FP1
−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8413FPC1
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8413FPC-REEL1
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8413FPCZ1, 2
−40°C to +85°C ±1 28-Lead Plastic Leaded Chip Carrier [PLCC] P-28
DAC8413FPC-REEL1
−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
DAC8413FPZ1, 2
−40°C to +85°C ±1 28-Lead Plastic Dual In-Line Package [PDIP] N-28-2
1 If burn-in is required, these models are available in CERDIP. Contact sales.
2 Z = RoHS Compliant Part.
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00274-0-9/09(F)