ATL35/900-CSP208 - Atmel Corporation

Features

•High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 (nominal)

•Up to 2.7 Million Used Gates and 976 Pins

•System Level Integration Technology

– Cores: ARM7TDMI™ and AVR® RISC Microcontrollers, OakDSP™ and

LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores

–Memory: SRAM, ROM, CAM and FIFO ; Gate Lev el or Embed ded

•I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB - Output Currents up to 20 mA,

5V Tolerant I/O

•Deep Submicron CAD Flow

Description

The ATL35 Series Gate Array and Embedded Array families are fabricated on a 0.35µ

CMOS process with up to 4 levels of metal. This family features arrays with up to 2.7

million routable gates and 976 pins. The high density and high pin-count capabilities

of the ATL35 family, coupled with the ability to embed mic rocontroller cores, DSP

engines , and memory, al l on the same sili con, make the ATL35 series of array s an

ideal choice for System Level Integration.

Notes : 1. One gate = NAN2

2. Routing site = 4 transistors

3. Nominal 2-input NAND gate FO = 2 at 3.3V

ATL35 Array Organization

Device

Number

4LM

Routable

Gates(1)

3LM

Routable

Gates(1)

Available

Routing

Sites(2)

Max

Pad

Count

Max

I/O

Count Gate

Speed(3)

ATL35/44 4,195 3,729 6,216 44 36 150 ps

ATL35/68 13,230 11,760 19,600 68 60 150 ps

ATL35/84 22,200 19,734 32,890 84 76 150 ps

ATL35/100 33,480 29,760 49,600 100 92 150 ps

ATL35/120 47,839 42,211 75,042 120 112 150 ps

ATL35/132 59,185 52,222 92,840 132 124 150 ps

ATL35/144 71,737 63,298 112,530 144 136 150 ps

ATL35/160 90,514 79,866 141,984 160 152 150 ps

ATL35/184 121,877 1 07,538 191,180 184 176 150 ps

ATL35/208 150,085 1 31,324 250,142 208 200 150 ps

ATL35/228 182,880 1 60,020 304,800 228 220 150 ps

ATL35/256 233,774 2 04,552 389,624 256 240 150 ps

ATL35/304 334,044 2 92,288 556,740 304 288 150 ps

ATL35/352 425,958 3 69,164 757,260 352 336 150 ps

ATL35/388 520,695 4 51,269 925,680 388 372 150 ps

ATL35/432 652,421 5 65,431 1,159,860 432 416 150 ps

ATL35/484 768,033 6 58,314 1,462,920 484 468 150 ps

ATL35/540 964,078 8 26,353 1,836,340 540 516 150 ps

ATL35/600 1,196,371 1,025,460 2,278,802 600 576 150 ps

ATL35/700 1,642,242 1,407,636 3,128,080 700 676 150 ps

ATL35/800 1,999,526 1,691,906 4,101,592 800 776 150 ps

ATL35/900 2,542,995 2,151,765 5,216,400 900 876 150 ps

ATL35/976 2,767,931 2,306,609 6,150,958 976 952 150 ps

Gate Array/

Embedded

Array

ATL35 Series

Rev. 0802E–10/99

ATL35 Series

Design

Design Systems Supported

Atmel supports several major software systems for design

with complete cell libraries, as well as utilities for netlist verification, test vector verification and accurate delay

simulations.

Design Flow and Tools

Atmel’s Gate Array/Embedded Array design flow is

structu red to allow t he designer to c onsolid ate the grea test

number of system components onto the same silicon chip,

using widely available third party design tools. Atmel’s cell

library reflects silicon performance over extremes of

temperatu re, volt age and proc ess, and i nclud es the effec ts

of metal loa ding, inte r-level ca pacit ance and edge rise and

fall times. The design flow includes clock tree synthesis to

customer-specified skew and latency goals. RC extraction

is performed on the final design database and incorporated

into the timing analysis.

The Gate Array/Embedded Array Design Flow, shown on

the following page, provides a pictorial description of the

typical interaction between Atmel’s design staff and the

customer. Atmel will deliver design kits to support the

customer’s synthe sis, ver ification, flo orplanni ng and scan

inserti on activities. Tool s such as Synopsys ™, Cadence®,

Verilog-HDL™, CTgen™, Exemplar™, PathMILL™ and

TimeMILL™ are used, and many others are available.

Should a design include embedded memory (SRAM or

ROM) or an embedded core, Atmel will conduct a design

review with the customer to understand the partition of the

Gate Array/Embedded Array and to define the location of

the memory blocks and/or cores so that an underlayer

layout model can be created.

Following Databa se Acceptance, automated test patter n

generati on (ATPG ) i s perfor m ed, if r eq uire d, o n s can p aths

using Synopsys or Sunrise™ tools, the design is routed,

and post-route RC data is extracted. After post-route

verifica tion an d a F inal De sign Review, the desi gn is tape d

out for fabrication.

The following design systems are supported:

System Version Tools

Cadence®

4.4.3

2.1.p2

4.1-s051

2.5

3.4B

2.3

Opus™ - Schematic and Layout

NC Verilog™ - Verilog Simulator

Pearl™ - Static Path

Verilog-XL™ - Verilog Simulator

Logic Design Planner™ - Floorplanner

BuildGates™ - Synthesis (Ambit)

Mentor/Model Tech™5.2e

B2 and Later Modelsim Verilog and VHDL (VITAL) Simulator

QuickVHDL™

Synopsys™

98.08, 98. 05

5.0.1A

VSS™ - VHDL Simulator

Design Compiler™ - Synthesis

Test Compiler™ - Scan Insertion and ATPG

Primetime™ - Static Path

VCS™ - Verilog Simulator

Exemplar™1998.2f Leonardo Spectrum™ - Synthesis

Syntest V2.2

V2.2

V1.6

TurboCheck - Gate

TurboScan

TurboFault

ATL35 Series

Gate Array/Embedded Array Design Flow

Fabricate

Personality

Tape Out

Personality Layers

Final Design

Review

DVS Assembly

and Test

Place and Route/

Clock Tree

Verification/

Resimulation

Define

Underlayer

Fabricate

Underlayer

Create

Underlayer

Tape Out

Underlayer

Scan/JTAG

Floorplan

Simulation/

Static Path

Synthesis/

Translation/

Conversion

Deliver

Design Kit

Kickoff

Meeting

Atmel

Joint

Database

Handoff

If Embedded Array

Customer

Database

Acceptance

If Embedded Array

ATL35 Series

Pin Definition Requirements

The cor ner pads are rese rved for Power and Ground only.

All other pads are fully programmable as Input, Output,

Bidirectional, Power or Ground. When implementing a

design with 5 V com pliant buffers, one bu ffer sit e must be

reserv ed for the VD D5 pin, which is used to distr ibute 5V

power to the compliant buffers.

Gate Array

Embedded Array

Design Options

Logic Synthesis

Atmel can accept netlists in VHDL (MIL-STD-454, IEEE

STD 1076) or Verilog-HDL format. Atmel fully supports

Synopsys for VHDL™ simulation as well as synthesis.

VHDL or V erilog-HDL is A tmel’s preferred database format

for Gate Array/Embedded Array design.

ASIC Design Translat ion

Atmel has successfully translated existing designs from

most major ASIC vendors (LSI Logic®, Motorola®, SMOS™,

Oki®, N EC®, Fujitsu®, AMI® and others) into Atmel ASICs.

These designs h ave been optimized f or speed an d gate

count and modified to add logic or memory, or replicated as

a pin-for-pin compatible, drop-in replacement.

FPGA and PLD Conversions

Atmel has successfully translated existing FPGA/PLD

designs from most major vendors (Xi linx®, Acte l®, Altera®,

AMD® and Atmel) into Atmel ASICs. There are four pri-

mary reasons to conver t from an FPGA/PLD to an ASIC.

Conversion of high volume devices for a single or com-

bined design is cost effective. Performance can often be

optimi zed for speed o r low powe r consum ption. Several

FPGA/PLDs can be combined onto a single chip to mini-

mize cost while reducing on-board space requirements.

Finally, in situations where an FPGA/PLD was used for

fast cycle time prototyping, an ASIC may provide a lower

cost answer for long-term volume production.

ATL35 Series

Macro Cores

AVR (8-b it RISC) Microcontroller (8515)

The AVR RISC microcontroller is a true 8-bit RISC

architecture, ideally suited for embedded control

applications. The AVR is offered as a gate level, soft macro

in the ATL35 family.

The AVR supp orts a powerful set of 120 ins tructions. The

AVR pre-fetches an instruction during prior instruction

execution, enabling the execution of one instruction per

clock cycle.

The Fast Access RISC register file consists of 32 gene ral

purpose working registers. These 32 registers eliminate the

data transfer delay in the traditional program code intensive

accumulator architectures.

The AVR can i ncorporate up to 8K x 8 program memory

(ROM) and 64K x 8 data memory (SRAM). Also included

are several optional peripherals: UART, 8-bit timer/counter,

16-bit timer /counter, external and internal i nterrupts and

programmable watchdog timer.

AVR (8-bit RISC) ASIC Core

ARM7TDMI Embedded Microcontroller Core

The ARM7TD MI is a powerful 32-bit proces sor offered as

an embedded core in the ATL35 series arrays.

The ARM7TDMI is a member of the Advanced RISC

Machines (ARM) family of general purpose 32-bit micropro-

cessor s, which offer high performance for very low power

consumption.

The ARM architectur e is bas ed on Red uc ed Inst ruc ti on Se t

Computer (RISC) principles, and the instruction set and

related dec od e m ec hani sm are much si mp ler th an those of

microprogrammed Complex Instruction Set Computers.

This simp licity resul ts in a high ins truction throughput and

impressive real-t ime interrupt response from a small and

cost-effective chip.

Pipelining is employed so that all parts of the processing

and memory systems can operate continuously. Typically,

while on e instruction is bein g executed, it s successor is

ATL35 Series

being decoded, and a third instruction is being fetched from

memory.

The ARM memory interface has been designed to allow the

performance potential to be realized without incurring high

costs in the memory system. Speed critical control signals

are pipelined to allow system control functions to be

implemented in standard low-power logic, and these

control signals facilitate the exploitation of the fast local

access modes offered by industry standard SRAMs.

The ARM7TDMI co re includ es sever al optional peripher al

macros. The options offered are Real-time Clock, DMA

Controll er, US ART, Ext er nal Bus Int er face, Interrupt, Ti mer

and Advanced Power Management and Controller.

ARM7TDMI Embedded Microcontroller Core

ATL35 Series

OakDSPCore

Atmel’s embedded OakDSPCore is a 16-bit, general

purpose, low-power, low-voltage and high-speed Digital

Signal Processor (DSP).

OAK is designed for mid-to-high-end telecommunications

and consumer electronics applications, where low-power

and po rtabi li ty are maj or requiremen ts. Am ong the a pplic a-

tions supported are digital cellular telephones, fast

modems, advanced facs imile machines and hard disk drives.

Oak is availabl e as a DSP core i n Atmel’s Gate Arra y cell

library, to be utilized as an engine for DSP-based Gate

Array /E mbe dded A rr ay. I t is s pe ci fie d wi th se veral lev el s o f

modularity in SRAM, ROM, I/O blocks, allowing efficient

DSP-based Gate Array/Embedded Array development.

OAK is aimed at achieving the best cost-performance fac-

tor fo r a given (s mall) sil icon area. A s a key ele ment of a

system -o n-chip, it ta kes into ac count such re qui remen ts as

program size, data memory size, glue logic and power

management.

The Oak core consists of three main execution units oper -

ating in parallel: the Computation/Bit-Manipulation Unit

(CBU), the Data Addressing Arithmetic Unit (DAAU) and

the Program Control Unit (PCU).

The Co re als o con tains ROM and S RAM addr essin g units ,

and Program Control Logic (PCL). All other peripheral

blocks, which are application specific, are defined as part of

the user-specific logic and implemented around the DSP

core on the same silicon die.

Oak has an enhanced set of DSP and general

microprocessor functions to meet most application

requirements. The OAK programming model and

instruction set are aimed at straightforward generation of

efficient and compact code.

LodeDSPCore

The LodeDSPCore will be offered in the ATL35 series

arrays as an embedded core. Lode is an advanced, 16-bit

Digital Signal Processor (DSP) core designed for optimal

performance in digital cellular, speech and voice

communications applications.

The Lode core architecture efficiently performs the

baseband functions - speech c ompression, forward error

correction, and modem functions - required by digital

cellular standards.

Lode i s the fi rst genera l-purpo se D SP that pr ovides tw o

multiplier-accumulators (MACs) that reduce power

consumption by effectively cutting cycle times in half.

Lode’s sui te of user-fr iendl y develo pment tools are easy t o

learn, thus accelerating the time it takes to get your product

to market.

ATL35 Series

ATL35 Series Cell Library

Atmel’s ATL35 S eries ga te array s make use of an exte n-

sive library of cell structures, including logic cells, buffers

and inv er ters, multiplex ers, dec od er s, an d I/ O opti on s. Soft

macros are also available.

The ATL35 Series PLL operates at frequencies of up to

250 MHz with minimal phase error and jitter, making it ideal

for fre quency sy nthesis of hi gh speed on -chip clo cks and

chip to chip synchronization.

Output buffers are programmable to meet the voltage and

current requirements of PCI (20 mA).

These cells are ch ar acter iz ed by use of SPICE mod eli ng at

the transistor level, with performance verified on

manufactur ed test arrays . Characterization is performed

over the rated temperature and voltage ranges to ensure

that the simulation accur ately predicts the perfor mance of

the finished product.

Cell Index

Cell Name Description Gate Count

ADD3X 1-bit Full Adder with Buffered Outputs 10

AND2 2-input AND 2

AND2H 2-input AND - High-drive 3

AND3 3-input AND 3

AND3H 3-input AND - High-drive 4

AND4 4-input AND 3

AND4H 4-input AND - High-drive 4

AND5 5-input AND 5

AOI22 2-input AND into 2-input NOR 2

AOI222 Two, 2-input ANDs into 2-input NOR 2

AOI2223 Three, 2-input ANDs into 3-input NOR 4

AOI2223H Three, 2-input ANDs into 3-input NOR - High-drive 8

AOI222H Two, 2-input ANDs into 2-input NOR - High-drive 4

AOI22H 2-input AND into 2-input NOR - High-drive 4

AOI23 2-input AND into 3-input NOR 3

BUF1 1x Buffer 2

BUF2 2x Buffer 2

BUF2T 2x Tri-state Bus Driver with Active-high Enable 4

BUF2Z 2x Tri-s tate Bus Driver with Active-low Enable 4

BUF3 3x Buffer 3

BUF4 4x Buffer 3

BUF8 8x Buffer 5

BUF12 12x Buffer 8

BUF16 16x Buffer 10

CLA7X 7-input Carry Lookahead 5

DEC4 2:4 Decoder 8

DEC4N 2:4 Decoder with Active-low Enabl e 10

DEC8N 3:8 Decoder with Active-low Enabl e 22

ATL35 Series

DFF D Flip-flop 8

DFFBCPX D Flip-flop with Asynchronous C lear and Preset

with Complementary Outputs 16

DFFBSRX D Flip-flop with Asynchronous Set and Reset

with Complementary Outputs 16

DFFC D Flip-flop with Asynchronous Clear 9

DFFR D Flip-flop with Asynchronous Reset 10

DFFRQ Quad D Flip-flop with Asynchronous Reset 40

DFFS D Flip-flop with Asynchronous Set 9

DFFSR D Flip-flop with Asynchronous Set and Reset 11

DLY1 Delay Buffer 1.0 ns 7

DLY2 Delay Buffer 1.5 ns 9

DLY3 Delay Buffer 2.0 ns 11

DLY4 Delay Buffer 4.5 ns 20

DSS Set scan Flip-flop 12

DSSBCPY Set scan Flip-flop with Clear and Preset 16

DSSBR Set scan Flip-flop with Reset 14

DSSBS Set scan Flip-flop with Set 14

DSSR Set scan D Flip-flop with Reset 12

DSSS Set scan D Flip-flop with Set 14

DSSSR Set scan D Flip-flop with Set and Reset 16

HLD1 Bus Hold Cell 4

INV1 1x Inver ter 1

INV1D Dual 1x Inverter 2

INV1Q Quad 1x Inverter 4

INV1TQ Quad 1x Tri-state Inverter with Active-high Enable 8

INV2 2x Inver ter 1

INV2T 2x Tri-state Inverter with Active-high Enable 3

INV3 3x Inver ter 2

INV4 4x Inver ter 2

INV8 8x Inver ter 4

INV 10 10x Inverter 8

JKF JK F lip-flop 10

JKFBCPX Clear P reset JK Flip -flop with Asynchronous

Clear and Preset and Complementary Outputs 16

JKFC JK Flip-flop with Asynchronous Clear 12

LAT LATCH 6

Cell Inde x (Continued)

Cell Name Description Gate Count

ATL35 Series

LATBG LATCH with Complementary Outputs and Inverted Gate Signal 6

LATBH LATCH with High-drive Complementary Outputs 7

LATR LATCH with Reset 5

LATS LATCH with Set 6

LATSR LATCH with Set and Reset 8

MUX2 2:1 MUX 4

MUX2H 2:1 MUX - High-drive 5

MUX2I 2:1 MUX with Inverted Output 3

MUX2IH 2:1 MUX with Inverted Output - High-drive 4

MUX2N 2:1 MUX with Active-low Enable 5

MUX2NQ Quad 2:1 MUX with Active-low Enable 18

MUX2Q Quad 2:1 MUX 16

MUX3I 3:1 MUX with Inverted Output 6

MUX3IH 3:1 MUX with Inverted Output - High-drive 8

MUX4 4:1 MUX 10

MUX4X 4:1 MUX with Transmission Gate Data Inputs 9

MUX4XH 4:1 MUX with Transmission Gate Data Inputs - High-drive 10

MUX5H 5:1 MUX - High-drive 14

MUX8 8:1 MUX 20

MUX8N 8:1 MUX with Active-low Enable 20

MUX8XH 8:1 MUX with Transmission Gate Data Inputs - High-drive 16

NAN2 2-input NAND 2

NAN2D Dual 2-input NAND 3

NAN2H 2-input NAND - High-drive 2

NAN3 3-input NAND 2

NAN3H 3-input NAND - High-drive 3

NAN4 4-input NAND 3

NAN4H 4-input NAND - High-drive 4

NAN5 5-input NAND 5

NAN5H 5-input NAND - High-drive 6

NAN5S 5-input NAND with Set 3

NAN6 6-input NAND 6

NAN6H 6-input NAND - High-drive 7

NAN8 8-input NAND 7

NAN8H 8-input NAND - High-drive 8

NOR2 2-input NOR 2

Cell Inde x (Continued)

Cell Name Description Gate Count

ATL35 Series

NOR2D Dual 2-input NOR 3

NOR2H 2-input NOR - High-drive 2

NOR3 3-input NOR 2

NOR3H 3-input NOR - High-drive 3

NOR4 4-input NOR 3

NOR4H 4-input NOR - High-drive 5

NOR5 5-input NOR 5

NOR5S 5-input NOR with Set 3

NOR8 8-input NOR 7

OAI22 2-input OR into 2-input NAND 2

OAI222 Two, 2-input ORs into 2-input NAND 3

OAI22224 Four, 2-input ORs into 4-input NAND 8

OAI222H Two, 2-input ORs into 2-input NAND - High-drive 6

OAI22H 2-input OR into 2-input NAND - High-drive 4

OAI23 2-input OR into 3-input NAND 3

ORR2 2-input OR 2

ORR2H 2-input OR - High-drive 3

ORR3 3-input OR 3

ORR3H 3-input OR - High-drive 4

ORR4 4-input OR 3

ORR4H 4-input OR - High-drive 4

ORR5 5-input OR 5

XNR2 2-input Exclusive NOR 4

XNR2H 2-input Exclusive NOR - High-drive 4

XOR2 2-input Exclusive OR 4

XOR2H 2-input Exclusive OR - High-drive 4

Cell Inde x (Continued)

Cell Name Description Gate Count

ATL35 Series

3.3 Volt I/O Buffer Cell Index

Cell Name Description

PFIPCI PCI Input

PFPECLL Positiv e ECL Output

PFPECLR Positiv e ECL Output

PIC CMOS Input

PICH CMOS Input - High-drive

PICI CMOS Inverting Input

PICS CMOS Input with Schmitt Trigger

PICSI CMOS Inverting Input with Schmitt Trigger

PID Differential Input

PO11 2 mA Tri-state Output

PO11F 2 mA Tri-state Output (fast)

PO11S 2 mA Tri-state Output (slow)

PO22 4 mA Tri-state Output

PO22F 4 mA Tri-state Output (fast)

PO22I 4 mA Inverting Tri-state Output

PO22S 4 mA Tri-state Output (slow)

PO33 6 mA Tri-state Output

PO33F 6 mA Tri-state Output (fast)

PO33S 6 mA Tri-state Output (slow)

PO44 8 mA Tri-state Output

PO44F 8 mA Tri-state Output (fast)

PO44S 8 mA Tri-state Output (slow)

PO55 10 mA Tri-state Output

PO55F 10 mA Tri-state Output (fast)

PO55S 10 mA Tri-state Output (slow)

PO66 12 mA Tri-state Output

PO66F 12 mA Tr i-state Output (fast)

PO66S 12 mA Tri-state Output (slow)

PO77 14 mA Tri-state Output

PO77F 14 mA Tr i-state Output (fast)

PO77S 14 mA Tri-state Output (slow)

PO88 16 mA Tri-state Output

PO88F 16 mA Tr i-state Output (fast)

PO88S 16 mA Tri-state Output (slow)

PO99 18 mA Tri-state Output

PO99F 18 mA Tr i-state Output (fast)

PO99S 18 mA Tri-state Output (slow)

POAA Tri-state Output

POAAF Tri-state Output (fast)

POAAS Tri-state Output (slow)

POBB Tri-state Output

POBBF Tri-state Output (fast)

POBBS Tri-state Output (slow)

POCC Tri-state Output

POCCF Tri-state Output (fast)

POCCS Tri-state Output (slow)

PX1 L XTAL Oscillator

PX2 L XTAL Oscillator

PX3 L XTAL Oscillator

PX4 L XTAL Oscillator

3.3 Volt I/O Buffer Cell Index

Cell Name Description

ATL35 Series

5.0 Volt Tolerant(1)

Cell Name Description

PFIPCI PCI Input

PFIPCIV 5V Tolerant PCI Input

PIC CMOS Input

PICH CMOS Input - High-drive

PICI CMOS Inverting Input

PICS CMOS Input with Schmitt Trigger

PICSI CMOS Inverting Input with Schmitt Trigger

PICSV 5V Tolerant CMOS Input with Schmitt Trigger

PICV 5V Tolerant CMOS Input

PO11 2 mA Tri-state Output

PO11F 2 mA Tri-state Output (fast)

PO11S 2 mA Tri-state Output (slow)

PO11V 5V Tolerant 2 mA Tr i-state Output

PO11VF 5V Tolerant 2 mA Tri- state Output (fast)

PO11VS 5V Tolerant 2 mA Tr i-state Output (slow)

PO22 4 mA Tri-state Output

PO22F 4 mA Tri-state Output (fast)

PO22I 4 mA Inverting Tri-state Output

PO22S 4 mA Tri-state Output (slow)

PO22V 5V Tolerant 4 mA Tr i-state Output

PO22VF 5V Tolerant 4 mA Tri- state Output (fast)

PO22VS 5V Tolerant 4 mA Tr i-state Output (slow)

PO33 6 mA Tri-state Output

PO33F 6 mA Tri-state Output (fast)

PO33S 6 mA Tri-state Output (slow)

PO33V 5V Tolerant 6 mA Tr i-state Output

PO33VF 5V Tolerant 6 mA Tri- state Output (fast)

PO33VS 5V Tolerant 6 mA Tr i-state Output (slow)

PO44 8 mA Tri-state Output

PO44F 8 mA Tri-state Output (fast)

PO44S 8 mA Tri-state Output (slow)

PO44V 5V Tolerant 8 mA Tr i-state Output

PO44VF 5V Tolerant 8 mA Tri- state Output (fast)

PO44VS 5V Tolerant 8 mA Tr i-state Output (slow)

PO55 10 mA Tri-state Output

PO55F 10 mA Tr i-state Output (fast)

PO55S 10 mA Tri-state Output (slow)

PO55V 5V Tolerant 10 mA Tri-state Output

PO55VF 5V Tolerant 10 mA Tri-state Output (fast)

PO55VS 5V Tolerant 10 mA Tri-state Output (slow)

PO66 12 mA Tri-state Output

PO66F 12 mA Tr i-state Output (fast)

PO66S 12 mA Tri-state Output (slow)

PO66V 5V Tolerant 12 mA Tri-state Output

PO66VF 5V Tolerant 12 mA Tri-state Output (fast)

PO66VS 5V Tolerant 12 mA Tri-state Output (slow)

PO77 14 mA Tri-state Output

PO77F 14 mA Tr i-state Output (fast)

PO77S 14 mA Tri-state Output (slow)

PO77V 5V Tolerant 14 mA Tri-state Output

PO77VF 5V Tolerant 14 mA Tri-state Output (fast)

PO77VS 5V Tolerant 14 mA Tri-state Output (slow)

PO88 16 mA Tri-state Output

PO88F 16 mA Tr i-state Output (fast)

PO88S 16 mA Tri-state Output (slow)

PO88V 5V Tolerant 16 mA Tri-state Output

PO88VF 5V Tolerant 16 mA Tri-state Output (fast)

PO88VS 5V Tolerant 16 mA Tri-state Output (slow)

PO99 18 mA Tri-state Output

PO99F 18 mA Tr i-state Output (fast)

PO99S 18 mA Tri-state Output (slow)

PO99V 5V Tolerant 18 mA Tri-state Output

PO99VF 5V Tolerant 18 mA Tri-state Output (fast)

PO99VS 5V Tolerant 18 mA Tri-state Output (slow)

POAA Tri-state Output

POAAF Tri-state Output (fast)

POAAS Tri-state Output (slow)

POAAV 5V Tolerant mA Tri-state Output

POAAVF 5V Tolerant mA Tri-state Output (fast)

POAAVS 5V Tolerant mA Tri-state Output (slow)

POBB Tri-state Output

POBBF Tri-state Output (fast)

5.0 Volt Tolerant(1)

Cell Name Description

ATL35 Series

5.0 Volt Compliant(2)

Notes: 1. Tolerant: Can a ccep t a 5. 0 vo lt inpu t b ut us es 3.3 v ol t

power supply.

2. Compliant: Can accept a 5.0 volt input or output.

Requires a 5.0 volt power supply.

POBBS Tri-state Output (slow)

POBB V 5V Tolerant mA Tri-state Output

POBBVF 5V Tolerant mA Tri-state Output (fast)

POBBVS 5V Tolerant mA Tri-state Output (slow)

POCC Tri-state Output

POCCF Tri-state Ou tpu t (fast)

POCCS Tri-state Output (slow)

PX1L XTAL Oscillator

PX2L XTAL Oscillator

PX3L XTAL Oscillator

PX4L XTAL Oscillator

5.0 Volt Tolerant(1)

Cell Name Description Cell Name Description

PICV5 5V Compliant

PO22V5 5V Compliant 4 mA Tri-state Output

PO44V5 5V Compliant 8 mA Tri-state Output

ATL35 Series

Absolute Maxim u m Ratings*

Operating Ambient

Temperature................................................... -55°C to +125°C

Storage Te mperature..................................... -65°C to +150°C

Maxim u m Inpu t Voltag e:

Inputs.......................................................................VDD + 0.5V

5V Tolerant/Compliant ...........................................VDD5 + 0.5V

Maxim u m Op erating Voltage (VDD)................................... 3.6V

Maxim u m Op erating Voltage (VDD5 )................................. 5.5V

*NOTICE: Stresses beyond those listed under

“Absolute Maximum Ratings” may cause

permanent damage to the device. This is a

stress r ating only and func tional operat ion of

the device at t hese or any othe r conditions

beyond those indicated in the operational

sections of this specification is not implied.

Exposure to absol ute ma xi m um rati ng

conditions for extended periods may affect

device reliability.

2.5 Volt DC Characteristics

Applicable over recommended operating temperature and voltage range unless otherwise noted.

Symbol Parameter Buffer Test Condition Min Typ Max Units

TAOperating Temperature All -55 125 °C

VDD Supply Voltage All 2.3 2.5 2.7 V

IIH High-level Input Current CMOS VIN = VDD, VDD = VDD (max) 10 µA

PCI 10

IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max) -10 µA

PCI -10

IOZ High-impedance State

Output Current All VIN = VDD or VSS,

VDD = VDD (max), No pull-up -10 10 µA

IOS Output Short-circuit

Current PO11 VOUT = VDD, VDD = VDD (max) 9 mA

PO11 VOUT = VSS, VDD = VDD (max) 6

VIH High-level Input Voltage CMOS 0.7VDD VPCI 0.475VDD

CMOS Schmitt 0.7VDD 1.5

VIL Low-level Input Voltage CMOS 0.3VDD VPCI 0.325VDD

CMOS Schmitt 1.0 0.3VDD

VHYS Hysteresis CMOS Schmitt 0.5 V

VOH High-level Output Voltage PO11 IOH = 1.4 mA, VDD = VDD (min) 0.7VDD V

PCI IOH = -500 µA 0.9VDD

VOL Low-level Output Voltage PO11 IOL = 1.4 mA, VDD = VDD (min) 0.4 V

PCI IOL = 1.5 mA 0.1VDD

ATL35 Series

3.3 Volt DC Characteristics

Applicable over recommended operating temperature and voltage range unless otherwise noted.

Symbol Parameter Buffer Test Condition Min Typ Max Units

TAOperating Temperature All -55 125 °C

VDD Supply Voltage All 3.0 3.3 3.6 V

IIH High-level Input Current CMOS VIN = VDD, VDD = VDD (max) 10 µA

PCI 10

IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max) -10 µA

PCI -10

IOZ High-impedance State

Output Current All VIN = VDD or VSS,

VDD = VDD (max), No pull-up -10 10 µA

IOS Output Short-circuit

Current PO11 VOUT = VDD, VDD = VDD (max) 14 mA

PO11 VOUT = VSS, VDD = VDD (max) -9

VIH High-level Input Voltage

CMOS, LVTTL 2.0

PCI 0.475VDD

CMOS/TTL-level

Schmitt 2.0 1.7

VIL Low-level Input Voltage

CMOS 0.8

PCI 0.325VDD

CMOS/TTL-level

Schmitt 1.1 0.8

VHYS Hysteresis TTL-level Schmitt 0.6 V

VOH High-level Output Voltage PO11 IOH = 2 mA, VDD = VDD (min) 0.7VDD V

PCI IOH = -500 µA 0.9VDD

VOL Low-level Output Voltage PO11 IOL = 2 mA, VDD = VDD (min) 0.4 V

PCI IOL = 1.5 mA 0.1VDD

ATL35 Series

Testability Techniques

For complex designs, involving blocks of memory and/or

cores, careful attention must be given to design-for-test

techniques. The sheer size of complex designs and the

number o f fun ction al v ec tors tha t wou ld need to b e c reate d

to exercise them fully, strongly suggests the use of more

efficient techniques. Combinations of SCAN paths, multi-

plexed access to memory and/or core blocks, and built-in-

self-test logic mu st be employed, in addition to functional

test patte rns, to pr ovid e both the us er and Atm el the abil ity

to test the finished product.

An example of a highly complex design could include a PLL

for clock management or synthesis, a microcontroller or

DSP engine or both, SRAM to suppor t the micr ocontroller

or DSP engine, and glue logic to support the interconnec-

tivity of each of these blocks. The design of each of thes e

blocks must take into co nsider ation the fact that the manu-

facture d de vi ce wil l b e te ste d on a h igh per fo rmanc e d ig ita l

tester. Combinations of parametric, functional, and struc-

tural tests , defined for digi tal testers, should be emp loyed

to create a suite of manufacturing tests.

The type of block dictates the type of testability techni que

to be e mployed. The PLL will, by construction, provide

access to key nodes so that functional and / or parametric

testing can be performed. Since a digital tester must control

5.0 Volt DC Characteristics

Applicable over recommended operating temperature and voltage range unless otherwise noted.

Symbol Paramete r Buffer Test Condition Min Typ Max U ni ts

TAOperating Temperature All -55 125 °C

VDD Supply Voltage 5V Tolerant 3.0 3.3 3.6 V

VDD5 Supply Voltage 5V Compliant 4.5 5.0 5.5 V

IIH High-level Input Current CMOS VIN = VDD, VDD = VDD (max) 10 µA

IIL Low-level Input Current CMOS VIN = VSS, VDD = VDD (max) -10 µA

IOZ High-imped anc e State

Output Current All VIN = VDD or VSS,

VDD = VDD (max),

No pull up -10 10 µA

IOS Output Short-circuit

Current PO11V VOUT = VDD, VDD = VDD (max) 8mA

PO11V VOUT = VSS, VDD = VDD (max) -7

VIH High-level Input Voltage

PICV, PICV5 2.0 5.0 5.5

PCI 0.475VDD 5.0 5.5

CMOS/TTL-level

Schmitt 2.0 1.7

VIL Low- level Input Voltage

PICV, PICV5 0.5VDD 0.8

PCI 0.325VDD

CMOS/TTL-level

Schmitt 1.1 0.8

VHYS Hysteresis CMOS/TTL-level

Schmitt 0.6 V

VOH High-level Output

Voltage PO11V IOH = -1.7 mA 0.7VDD V

PO11V5 IOH = -1.7 mA 0.7VDD5

VOL Low-level Output

Voltage PO11V, PO11V5 IOL = 1.7 mA 0.5 V

I/O Buffer DC Characteristics

Symbol Parameter Test Condition Typical Units

CIN Capacitance, Input Buffer (die) 3.3V 2.4 pF

COUT Capacitance, Output Buffer (die) 3.3V 5.6 pF

CI/O Capacitanc e, Bidirectional 3.3V 6.6 pF

ATL35 Series

all the clo cks during the tes ting of a Gate Arr ay/Embedde d

Array, provision must be made for the VCO to be

bypassed. Atmel’s PLLs include a multiplexing capability

for ju st this purpose. The addition of a few pins will allow

other portions of the PLL to be isolated for test, without

impinging upon the normal functionality.

In a s im il ar vei n, ac ce ss t o mi cr oc on t rol l er, DSP a n d SRAM

blocks must be provided so that controllability and

observability of the inputs and outputs to the blocks are

achieved with the minimum amount of preconditioning. The

AVR and A RM micr ocontroller s support S CAN testing , as

do the three main execution units of the OakDSP. SRAM

and CAM blocks need to provide access to both addr ess

and data ports so that comprehensive memory tests can be

performed. Mu ltiplexing I/O pins provides a method for

providing this accessibility.

The glue logic can be designed using full SCAN techniques

to enhance its testability.

It should be noted that, in almost all of these cases, the

purpose of the testability technique is to provide Atmel a

means to assess the structural integrity of a Gate

Array/Embedded Array; i.e., sort devices with manufactur -

ing-i nduced defects. All of the tech niques describe d above

should be considered supplemental to a set of patterns

which exercise the functionality of the design in its antici-

pated operating modes.

A dvanced Packaging

The ATL35 Seri es gate arrays are offer ed in a wide va riety

of standard pack ages, including plas tic and ceramic q uad

flatpa cks, th in quad flatp acks, ce ramic pi n grid ar rays , and

ball grid arrays. High volume onshore and offshore contrac-

tors provide assembly and test for commercial product,

with prototype capability in Colorado Springs. Custom

package de signs are also avai lable as requ ired to meet a

customer’s specific needs, and are supported through

Atmel's package design center. When a standard package

cannot meet a customer's need, a package can be

designe d to prec isely fit the applic ation and to ma intain the

performanc e obtained i n silicon . Atmel has delivered cus-

tom-designed packages in a wide variety of configurations.

Note: 1. Partial list

Packaging Options

Package Type Pin Count

PQFP 44, 52, 64, 80, 10 0, 120, 128, 132, 144, 160, 184, 208, 240, 304

Power Quad 144, 160, 208, 240, 304

L/TQFP 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216

PLCC 20, 28, 32, 44, 52, 68, 84

CPGA 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391

CQFP 64, 68, 84, 100, 120, 132, 144, 160, 224, 340

PBGA 121, 169, 208, 217, 225, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456

Super BGA 168, 204, 240, 256, 304, 352, 432, 560, 600

Low-profile Mi ni BGA 132, 144, 160, 180, 208

Chip-scale BGA(1) 40, 49, 56, 64, 81, 84, 96, 100, 128

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-

ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for

any errors which may appear in this document, reserves the right to change devices or s pecifications detailed herein at any time without

notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-

erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. At mel’s products are

not authorized for use as critical components in life support devices or systems.

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