1. General description
The 74HC30; 74HCT30 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC30; 74HCT30 provides a quad 8-input NAND function.
2. Features and benefits
Input levels:
For 74HC30: CMOS level
For 74HCT30: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce eds 20 0 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
74HC30; 74HCT30
8-input NAND gate
Rev. 5 — 13 December 2011 Product data sheet
Table 1. Ordering information
Type number Package
Temperatur e ra nge Name Description Version
74HC30N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT30N
74HC30D 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74HCT30D
74HC30DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT30DB
74HC30PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT30PW
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 2 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna488
A
Y
1
8
B
2C
3D
4E
5F
6G
11 H
12
8
&
mna489
1
2
3
4
5
6
11
12
Fig 3. Logic diagra m
B
A
C
D
F
E
G
H
mna490
Y
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 3 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
74HC30
74HCT30
AV
CC
B n.c.
CH
DG
E n.c.
F n.c.
GND Y
001aal790
1
2
3
4
5
6
78
10
9
12
11
14
13
Table 2. Pin de scription
Symbol Pin Description
A 1 data input
B 2 data input
C 3 data input
D 4 data input
E 5 data input
F 6 data input
GND 7 ground (0 V)
Y 8 data output
n.c. 9 not connected
n.c. 10 not connected
G 11 dat a i nput
H 12 d ata input
n.c. 13 not connected
VCC 14 supply voltage
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 4 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
Table 3. Function table[1]
Input Output
A B C D E F G H Y
LXXXXXXXH
XLXXXXXXH
XXLXXXXXH
XXXLXXXXH
XXXXLXXXH
XXXXXLXXH
XXXXXXLXH
XXXXXXXLH
HHHHHHHHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP14 package [2] - 750 mW
SO14, (T)SSOP14 packages [2] - 500 mW
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 5 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
8. Recommended operating conditions
9. Static characteristics
Table 5. Re commended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC30 74HCT30 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 62 5 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC30
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --2.0- 20 - 40A
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 6 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
10. Dynamic characteristics
CIinput
capacitance -3.5- - - - -pF
74HCT30
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =5.5V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.4 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 60 216 - 275 - 294 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; CL= 50 pF; for load circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC30
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure 5 [1]
VCC = 2.0 V - 41 130 165 195 ns
VCC = 4.5 V - 15 26 33 39 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
VCC = 6.0 V - 12 22 28 33 ns
tttransition time see Figure 5 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 7 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -15- - -pF
74HCT30
tpd propagation delay A, B, C, D, E, F, G, H to Y;
see Figure 5 [1]
VCC = 4.5 V - 16 28 35 42 ns
VCC = 5.0 V; CL=15pF - 12 - - - ns
tttransition time VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V [3] -15- - -pF
Table 7. Dynamic characteristics …continu ed
GND = 0 V; CL= 50 pF; for load circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
001aal792
VOL
VOH
GND
VM
tPHL tPLH
tTHL tTLH
VM
VX
VY
nY output
A, B, C, D,
E, F, G, H
input
VI
Table 8. Measur ement points
Type Input Output
VMVMVXVY
74HC30 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT30 1.3 V 1.3 V 0.1VCC 0.9VCC
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 8 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
Test data is given in Table 9.
Definitions for test circuit:
RT= termination resistance should be equal to the output impedance Zo of the pulse generator.
CL= load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
001aah768
tW
tW
tr
tr
tf
VM
VI
negative
pulse
GND
VI
positive
pulse
GND
10 %
90 %
90 %
10 % VMVM
VM
tf
VCC
DUT
RT
VIVO
CL
G
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC30 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT30 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 9 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
12. Package outline
Fig 7. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 10 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
Fig 8. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 11 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
Fig 9. Package outline SOT337-1 (SSOP14)
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 12 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
Fig 10. Package outline SOT402-1 (TSSOP14)
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 13 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
TTL Transistor-Trans istor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT30 v.5 20111213 Product data sheet - 74HC_HCT30 v.4
Modifications: •Legal pages updated.
74HC_HCT30 v.4 20100504 Product data sheet - 74HC_HCT30 v.3
74HC_HCT30 v.3 20100420 Product data sheet - 74HC_HCT30 v.2
74HC_HCT30 v.2 19970829 Product specification - -
74HC_HCT30 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 14 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
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Short data sheet — A short data sheet is an extract from a full data sheet
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for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
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the quality and reliability of the device.
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 5 — 13 December 2011 15 of 16
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
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Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC30; 74HCT30
8-input NAND gate
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 December 2011
Document identifier: 74HC_HCT30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16