Z8 GPTM Microcontrollers ZGR163L ROM MCU Family Product Specification PS024006-0605 ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer (c) 2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. PS024006-0605 Disclaimer ZGR163L Product Specification iii Revision History Each instance in the Revision History table reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table. Date Revision Level December 02 2004 Page # Description Updated to incorporate minor changes to Figure 44 and Figure 47. Added 4K Parts information in the Ordering Section. 67, 69 81 Removed mask option note, and changed temperature ranges in Table 6 2, 7, 8, and Table 11. Added characterization data to Table 7 and added new 9, 10, 11, 14 Tables 8 and 9. Removed Preliminary designation All January 2005 03 Changed low power consumption value to 5mW. Changed STOP and HALT mode current values to 1.3mA and 0.5mA respectively. Minor corrections to Tables 7, 8, 9. 1, 9, 10, 11 March 2005 04 Minor correction/addition to the Ordering section. 84 June 2005 05 Incorporated 1K and 2K parts All June 2005 06 Changed part number for emulator/programmer. 85 PS024006-0605 Revision History ZGR163L Product Specification iv Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 (P07-P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 (P27-P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 3 (P37-P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 22 26 27 28 36 44 46 49 49 Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 61 Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 65 Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 PS024006-0605 ZGR163L Product Specification v List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. PS024006-0605 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 20-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . 5 28-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . 6 Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 20 Program Memory Map for ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 24 Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Register Pointer--Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 40 Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 51 Stop Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ZGR163L Product Specification vi Figure 33. Stop Mode Recovery Register 2 ((0F) DH:D2-D4, D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . Figure 35. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36. TC8 Control Register ((0D) 00H: Read/Write Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37. T8 and T16 Common Control Functions ((0D) 01H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 38. T16 Control Register ((0D) 02H: Read/Write Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 39. T8/T16 control Register (0D) 03H: Read/Write (Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41. Port Configuration Register (PCON) ((0F)00H: Write Only . . . . . . . Figure 42. Stop Mode Recovery Register ((0F) 0BH: D6-D0=Write Only, D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43. Stop Mode Recovery Register 2 ((0F) 0DH: D2-D4, D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 44. Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . Figure 45. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . Figure 46. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . Figure 47. Port 0 Register (F8H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 48. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . Figure 49. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . Figure 50. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . Figure 51. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 52. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . Figure 53. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . Figure 54. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . Figure 55. 20-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 56. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 57. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 58. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 59. 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 60. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . PS024006-0605 56 57 58 61 62 63 64 65 66 67 68 69 69 70 71 72 73 73 74 74 75 75 76 76 77 78 79 80 ZGR163L Product Specification vii List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. PS024006-0605 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 20-Pin DIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . . 5 28-Pin DIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . . 6 Absolute MaxPS024006-0605imum Ratings . . . . . . . . . . . . . . . . . . . 7 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ZGR163LS DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ZGR163LE DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ZGR163LA DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Port 3 Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CTR0(0D)00h Counter/Timer8 Control Register . . . . . . . . . . . . . . . 29 CTR1(0D)01h T8 and T16 Common Functions . . . . . . . . . . . . . . . . 31 CTR2(0D)02h: Counter/Timer16 Control Register . . . . . . . . . . . . . 34 CTR3(0D)03h T8/T16 Control Register . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 48 IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SMR2(F)0DH:Stop Mode Recovery Register 2* . . . . . . . . . . . . . . . 53 Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Watch-Dog Timer Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 ROM Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ZGR163L Product Specification 1 Features Table 1 lists the features of the ZiLOG's ZGR163L members. Table 1. Features Device ZGR163L ROM MCU Family ROM RAM* (Bytes) I/O Lines 1K/2K/4K/ 8K/16K 237 16/24 Voltage Range 2.0V-3.6V * General purpose PS024006-0605 * * Low power consumption-5mW (typical) * * Speed: 8 MHz * Special architecture to automate both generation and reception of complex pulses or signals: - One programmable 8-bit counter/timer with two capture registers and two load registers - One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception * Six priority interrupts - Three external - Two assigned to counter/timers - One low-voltage detection interrupt * Low voltage detection and high voltage detection flags T = Temperature S = Standard 0 to +70C E = Extended -40 to +105C A = Automotive -40 to +125C Three standby modes: - STOP--1.3A (typical) - HALT--0.5mA (typical) - Low voltage reset Features ZGR163L Product Specification 2 * * * * * Programmable Watch-Dog Timer (WDT) Power-On Reset (POR) Two independent comparators with programmable interrupt polarity Selectable pull-up transistors on ports 0, 2, 3 Mask options - Port 0: 0-3 pull-ups - Port 0: 4-7 pull-ups - Port 2: 0-7 pull-ups - Port 3: 0-3 pull-ups - Watch-Dog Timer at Power On Reset General Description The ZGR163L is a ROM-based member of the MCU family of general purpose microcontrollers. With 1KB to 16KB of program memory and 237B of general purpose RAM, ZiLOG's CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The ZGR163L architecture (Figure 1) is based on ZiLOG's 8-bit microcontroller core with an Expanded Register File allowing access to register-mapped peripherals, input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8 core offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. There are three basic address spaces available to support a wide range of configurations: Program Memory, Register File and Expanded Register File. The register file is composed of 256B of RAM. It includes three I/O port registers, 16 control and status registers, and 237 general-purpose registers. The Expanded Register File consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the ZGR163L offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see Figure 2). Also included are a large number of user-selectable modes and two on-board comparators to process analog signals with separate reference voltages. Power connections use the conventional descriptions listed in Table 2. PS024006-0605 General Description ZGR163L Product Specification 3 Table 2. Power Connections I/O Nibble Programmable Connection Circuit Device Power VCC VDD Ground GND VSS P00 P01 P02 P03 4 P04 P05 P06 P07 4 Register File 256 x 8-Bit Port 0 Port 3 Register Bus Internal Address Bus ROM Up to 16K x 8 Pref1/P30 P31 P32 P33 P34 P35 P36 P37 Z8(R) Core Z8(R) Core Internal Data Bus XTAL Expanded Register File I/O Bit Programmable P20 P21 P22 P23 P24 P25 P26 P27 Watch-Dog Timer Machine Timing & Instruction Control Expanded Register Bus Power VDD VSS Port 2 Power-On Reset Counter/Timer 8 8-Bit Counter/Timer 16 16-Bit 2-Comparators Low Voltage Detection High Voltage Detection Note: Refer to the specific package for available pins. Figure 1. Functional Block Diagram PS024006-0605 General Description ZGR163L Product Specification 4 HI16 LO16 8 8 16-Bit T16 1 2 4 8 Timer 16 16 8 8 SCLK Clock Divider TC16H TC16L HI8 Input Glitch Filter Edge Detect Circuit And/Or Logic Timer 8/16 LO8 8 8 8-Bit T8 8 TC8H Timer 8 8 TC8L Figure 2. Counter/Timers Diagram PS024006-0605 General Description ZGR163L Product Specification 5 Pin Description The pin configuration for the 20-pin DIP/SOIC/SSOP is illustrated in Figure 3 and described in Table 3. The pin configuration for the 28-pin DIP/SOIC/SSOP are depicted in Figure 4 and described in Table 4. P25 P26 P27 P07 VDD XTAL2 XTAL1 P31 P32 P33 1 2 3 4 5 6 7 8 9 10 20-Pin DIP SOIC SSOP 20 19 18 17 16 15 14 13 12 11 P24 P23 P22 P21 P20 VSS P01 P00/Pref1/P30 P36 P34 Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration Table 3. 20-Pin DIP/SOIC/SSOP Pin Identification PS024006-0605 Pin # Symbol Function Direction 1-3 P25-P27 Port 2, Bits 5,6,7 Input/Output 4 P07 Port 0, Bit 7 Input/Output 5 VDD Power Supply 6 XTAL2 Crystal Oscillator Clock Output 7 XTAL1 Crystal Oscillator Clock Input 8-10 P31-P33 Port 3, Bits 1,2,3 Input 11,12 P34, P36 Port 3, Bits 4,6 Output 13 P00/Pref1/P30 Port 0, Bit 0/Analog reference input Port 3, Bit 0 Input/Output for P00 Input for Pref1/P30 14 P01 Port 0, Bit 1 Input/Output 15 VSS Ground 16-20 P20-P24 Port 2, Bits 0,1,2,3,4 Input/Output Pin Description ZGR163L Product Specification 6 P25 P26 P27 P04 P05 P06 P07 VDD XTAL2 XTAL1 P31 P32 P33 P34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-Pin PDIP SOIC SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 Pref1/P30 P36 P37 P35 Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration Table 4. 28-Pin DIP/SOIC/SSOP Pin Identification Pin 1-3 4-7 8 Symbol P25-P27 P04-P07 VDD Direction Input/Output Input/Output Description Port 2, Bits 5,6,7 Port 0, Bits 4,5,6,7 Power supply 9 10 11-13 14 15 16 17 18 XTAL2 XTAL1 P31-P33 P34 P35 P37 P36 Pref1 Output Input Input Output Output Output Output Input 19-21 22 P00-P02 VSS Input/Output Crystal, oscillator clock Crystal, oscillator clock Port 3, Bits 1,2,3 Port 3, Bit 4 Port 3, Bit 5 Port 3, Bit 7 Port 3, Bit 6 Analog ref input; connect to VCC if not used Port 3 Bit 0 Port 0, Bits 0,1,2 Ground 23 24-28 P03 P20-P24 Input/Output Input/Output Port 0, Bit 3 Port 2, Bits 0-4 Absolute Maximum Ratings Stresses greater than those listed in Table 5 might cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at PS024006-0605 Absolute Maximum Ratings ZGR163L Product Specification 7 any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period might affect device reliability. Table 5. Absolute Maximum Ratings Parameter Minimum Maximum Units Ambient temperature under bias -40 +125 C Storage temperature -65 +150 C Voltage on any pin with respect to VSS -0.3 +4.0 V Voltage on VDD pin with respect to VSS -0.3 +3.6 V Maximum current on input and/or inactive output pin -5 +5 mA Maximum output current from active output pin -25 +25 mA 75 mA Maximum current into VDD or out of VSS Notes 1 Note: 1. This voltage applies to all pins except the following: VDD. Standard Test Conditions The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 5). From Output Under Test 150 pF Figure 5. Test Load Diagram PS024006-0605 Standard Test Conditions ZGR163L Product Specification 8 Capacitance Table 6 lists the capacitances. Table 6. Capacitance Parameter Maximum Input capacitance 12pF Output capacitance 12pF I/O capacitance 12pF Note: TA = 25C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND DC Characteristics Table 7. ZGR163LS DC Characteristics Symbol VCC VCH Parameter Supply Voltage Clock Input High Voltage Clock Input Low VCL Voltage Input High Voltage VIH Input Low Voltage VIL VOH1 Output High Voltage Output High Voltage VOH2 (P36, P37, P00, P01) Output Low Voltage VOL1 Output Low Voltage VOL2 (P00, P01, P36, P37) VOFFSET Comparator Input Offset Voltage Comparator VREF Reference Voltage Input Leakage IIL Pull-up Resistance RPU IOL ICC Output Leakage Supply Current PS024006-0605 VCC 2.0-3.6V 2.0-3.6V 2.0-3.6V 2.0-3.6V 2.0-3.6V 2.0-3.6V TA= 0C to +70C Units Conditions Min Typ(7) Max 2.0 V 3.6 V See Note 5 0.8 VCC VCC+0.3 V Driven by External Clock Generator VSS-0.3 0.5 V Driven by External Clock Generator 0.7 VCC VCC+0.3 V VSS-0.3 0.2 VCC V VCC-0.4 V IOH = -0.5mA VCC-0.8 V IOH = -7mA 2.0-3.6V 2.0-3.6V 0.4 0.8 V V 2.0-3.6V 25 mV 2.0-3.6V 0 VDD -1.75 2.0-3.6V 2.0V 3.6V 2.0-3.6V 2.0 V 3.6 V -1 225 75 -1 1 675 275 1 3 5 1.2 2.1 Notes 5 IOL = 4.0mA IOL = 10mA V A K K A mA mA VIN = 0V, VCC Pull-ups disabled VIN = 0V; Pullups selected by mask option VIN = 0V, VCC at 8.0MHz at 8.0MHz 1, 2 1, 2 DC Characteristics ZGR163L Product Specification 9 Table 7. ZGR163LS DC Characteristics (Continued) Symbol ICC1 ICC2 ILV VBO VLVD VHVD Parameter Standby Current (HALT Mode) Standby Current (STOP Mode) VCC 2.0 V 3.6 V 2.0 V 3.6 V 2.0 V 3.6 V Standby Current (Low Voltage) VCC Low Voltage Protection Vcc Low Voltage Detection Vcc High Voltage Detection TA= 0C to +70C Min Typ(7) 0.5 0.8 1.2 1.4 3.5 6.5 0.8 Max 1.6 2.0 8 10 20 30 6 Units mA mA A A A A A Conditions Notes VIN = 0V, Clock at 8.0MHz 1, 2,6 Same as above VIN = 0 V, VCC WDT is not Running 3 2.0 V 8MHz maximum Ext. CLK Freq. 1.8 2.4 V 2.7 V VIN = 0 V, VCC WDT is Running 3 Measured at 1.3V 4 Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when VCC falls below VBO limit. 5. It is strongly recommended to add a filter capacitor (min., 0.1 F), physically close to VCC and VSS pins if operating voltage fluctuations are anticipated, such as those resulting from driving an IR LED. 6. Comparator and Timers are on. Interrupt disabled. 7. Typical values shown are at 25C Table 8. ZGR163LE DC Characteristics TA= -40C to +105C Symbol Parameter VCC Supply Voltage VCH Clock Input High Voltage 2.0-3.6V 0.8 VCC VCL Clock Input Low Voltage 2.0-3.6V VSS-0.3 VIH Input High Voltage 2.0-3.6V 0.7 VCC VCC+0.3 V VIL Input Low Voltage 2.0-3.6V VSS-0.3 0.2 VCC V VOH1 Output High Voltage 2.0-3.6V VCC-0.4 V IOH = -0.5mA VOH2 Output High Voltage (P36, P37, P00, P01) 2.0-3.6V VCC-0.8 V IOH = -7mA VOL1 Output Low Voltage 2.0-3.6V V IOL = 4.0mA PS024006-0605 VCC Min 2.0 V Typ(7) Max Units Conditions Notes 3.6 V 5 VCC+0.3 V 0.5 0.4 V See Note 5 Driven by External Clock Generator Driven by External Clock Generator DC Characteristics ZGR163L Product Specification 10 Table 8. ZGR163LE DC Characteristics (Continued) TA= -40C to +105C Max Units Conditions 2.0-3.6V 0.8 V VOFFSET Comparator Input Offset Voltage 2.0-3.6V 25 mV VREF Comparator Reference Voltage 2.0-3.6V 0 IIL Input Leakage 2.0-3.6V -1 1 A VIN = 0V, VCC Pull-ups disabled RPU Pull-up Resistance 2.0V 200 700 K 3.6V 50 300 K VIN = 0V; Pullups selected by mask option -1 1 A VIN = 0V, VCC Symbol Parameter VCC VOL2 Output Low Voltage (P00, P01, P36, P37) Min Typ(7) Notes IOL = 8.0mA VDD-1.75 V IOL Output Leakage 2.0-3.6V ICC Supply Current 2.0 V 3.6 V 1.2 2.1 3 5 mA mA at 8.0MHz at 8.0MHz 1, 2 1, 2 ICC1 Standby Current (HALT Mode) 2.0 V 3.6 V 0.5 0.8 1.6 2.0 mA mA VIN = 0V, Clock at 8.0MHz Same as above 1, 2,6 ICC2 Standby Current (STOP Mode) 2.0 V 3.6 V 2.0 V 3.6 V 1.2 1.4 3.5 6.5 12 15 30 40 A A A A VIN = 0 V, VCC WDT is not Running 3 VIN = 0 V, VCC WDT is Running 3 A Measured at 1.3V 4 V 8MHz maximum Ext. CLK Freq. ILV Standby Current (Low Voltage) 0.8 6 VBO VCC Low Voltage Protection 1.8 2.15 VLVD Vcc Low Voltage Detection 2.4 V VHVD Vcc High Voltage Detection 2.7 V Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when VCC falls below VBO limit. 5. It is strongly recommended to add a filter capacitor (min., 0.1 F), physically close to VCC and VSS pins if operating voltage fluctuations are anticipated, such as those resulting from driving an IR LED. 6. Comparator and Timers are on. Interrupt disabled. 7. Typical values shown are at 25C PS024006-0605 DC Characteristics ZGR163L Product Specification 11 Table 9. ZGR163LA DC Characteristics TA= -40C to +125C Symbol Parameter VCC VCC Supply Voltage VCH Clock Input High Voltage 2.0-3.6V 0.8 VCC VCL Clock Input Low Voltage 2.0-3.6V VSS-0.3 VIH Input High Voltage 2.0-3.6V 0.7 VCC VCC+0.3 V VIL Input Low Voltage 2.0-3.6V VSS-0.3 0.2 VCC V VOH1 Output High Voltage 2.0-3.6V VCC-0.4 V IOH = -0.5mA VOH2 Output High Voltage (P36, P37, P00, P01) 2.0-3.6V VCC-0.8 V IOH = -7mA VOL1 Output Low Voltage 2.0-3.6V 0.4 V IOL = 4.0mA VOL2 Output Low Voltage (P00, P01, P36, P37) 2.0-3.6V 0.8 V IOL = 8.0mA VOFFSET Comparator Input Offset Voltage 2.0-3.6V 25 mV VREF Comparator Reference Voltage 2.0-3.6V 0 IIL Input Leakage 2.0-3.6V -1 1 A VIN = 0V, VCC Pull-ups disabled RPU Pull-up Resistance 2.0V 200 700 K 3.6V 50 300 K VIN = 0V; Pullups selected by mask option -1 1 A VIN = 0V, VCC Min Typ(7) 2.0 V Max Units Conditions Notes 3.6 V 5 VCC+0.3 V 0.5 V See Note 5 Driven by External Clock Generator Driven by External Clock Generator VDD-1.75 V IOL Output Leakage 2.0-3.6V ICC Supply Current 2.0 V 3.6 V 1.2 2.1 3 5 mA mA at 8.0MHz at 8.0MHz 1, 2 1, 2 ICC1 Standby Current (HALT Mode) 2.0 V 3.6 V 0.5 0.8 1.6 2.0 mA mA VIN = 0V, Clock at 8.0MHz Same as above 1, 2,6 ICC2 Standby Current (STOP Mode) 2.0 V 3.6 V 2.0 V 3.6 V 1.2 1.4 3.5 6.5 15 20 30 40 A A A A VIN = 0 V, VCC WDT is not Running 3 VIN = 0 V, VCC WDT is Running 3 A Measured at 1.3V 4 V 8MHz maximum Ext. CLK Freq. ILV Standby Current (Low Voltage) 0.8 6 VBO VCC Low Voltage Protection 1.8 2.15 PS024006-0605 DC Characteristics ZGR163L Product Specification 12 Table 9. ZGR163LA DC Characteristics (Continued) TA= -40C to +125C VCC Min Typ(7) Max Symbol Parameter Units Conditions VLVD Vcc Low Voltage Detection 2.4 V VHVD Vcc High Voltage Detection 2.7 V Notes Notes: 1. All outputs unloaded, inputs at rail. 2. CL1 = CL2 = 100 pF. 3. Oscillator stopped. 4. Oscillator stops when VCC falls below VBO limit. 5. It is strongly recommended to add a filter capacitor (min., 0.1 F), physically close to VCC and VSS pins if operating voltage fluctuations are anticipated, such as those resulting from driving an IR LED. 6. Comparator and Timers are on. Interrupt disabled. 7. Typical values shown are at 25C PS024006-0605 DC Characteristics ZGR163L Product Specification 13 AC Characteristics Figure 6 and Table 10 describe the Alternating Current (AC) characteristics. 1 3 Clock 2 TIN 7 2 3 7 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Figure 6. AC Timing Diagram PS024006-0605 AC Characteristics ZGR163L Product Specification 14 Table 10. AC Characteristics TA= 0C to +70C (S) -40C to +105C (E) -40C to +125C (A) 8.0MHz No Symbol Parameter VCC Minimum Maximum Watch-Dog Timer Mode Register Units Notes (D1, D0) 1 TpC Input Clock Period 2.0-3.6 121 DC ns 1 2 TrC,TfC Clock Input Rise and 2.0-3.6 Fall Times 25 ns 1 3 TwC Input Clock Width 2.0-3.6 37 ns 1 4 TwTinL Timer Input Low Width 2.0 3.6 100 70 ns 1 5 TwTinH Timer Input High Width 2.0-3.6 3TpC 1 6 TpTin Timer Input Period 2.0-3.6 8TpC 1 7 TrTin,TfTin Timer Input Rise and 2.0-3.6 Fall Timers 8 TwIL Interrupt Request Low Time 2.0 3.6 100 70 9 TwIH Interrupt Request Input High Time 2.0-3.6 5TpC Stop-Mode Recovery Width Spec 2.0-3.6 12 11 Tost Oscillator Start-Up Time 2.0-3.6 12 Twdt Watch-Dog Timer Delay Time 2.0-3.6 2.0-3.6 2.0-3.6 2.0-3.6 5 10 20 80 13 TPOR Power-On Reset 2.0-3.6 2.5 10 Twsm 100 ns 1 ns 1, 2 1, 2 ns 5TpC 3 4 5TpC 4 ms ms ms ms 10 0, 0 0, 1 1, 0 1, 1 ms Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. SMR - D5 = 1. 4. SMR - D5 = 0. PS024006-0605 AC Characteristics ZGR163L Product Specification 15 Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, or LC to the onchip oscillator input. Additionally, an external single-phase clock can be connected to the on-chip oscillator input. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. Port 0 (P07-P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open-drain controlled by bit D2 in the PCON register. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured (Figure 7) as an input port. An optional pull-up transistor is available as a OTP/mask option on all Port 0 bits with nibble select. Notes: Internal pull-ups are disabled on any given pin or group of port pins when programmed into Output mode. The Port 0 direction is reset to its default state following an SMR. PS024006-0605 Pin Functions ZGR163L Product Specification 16 4 Z8(R) Port 0 (I/O) 4 Open-Drain I/O Mask VCC Option Resistive Transistor Pull-up Pad Out In Figure 7. Port 0 Configuration Port 2 (P27-P20) Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 8). These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight pull-up transistors on this port. Bits programmed as outputs are globally programmed as either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as inputs. Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part. P20 can be programmed to access the edge-detection circuitry in Demodulation mode. PS024006-0605 Pin Functions ZGR163L Product Specification 17 Z8(R) Open-Drain I/O Port 2 (I/O) Mask VCC Option Resistive Transistor Pull-up Pad Out In Figure 8. Port 2 Configuration Port 3 (P37-P30) Port 3 is an 8-bit, CMOS-compatible fixed I/O port (see Figure 9). Port 3 consists of four fixed input (P33-P30) and four fixed output (P37-P34), which can be configured under software control for interrupt and as output from the counter/timers. P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs. PS024006-0605 Pin Functions ZGR163L Product Specification 18 Pref1/P30 P31 P32 P33 Z8(R) P34 P35 Port 3 (I/O) P36 P37 R247 = P3M D1 Dig. P31 (AN1) + Pref1 Comp1 - P32 (AN2) P33 1 = Analog 0 = Digital + Comp2 IRQ2, P31 Data Latch An. IRQ0, P32 Data Latch - From Stop Mode Recovery Source of SMR IRQ1, P33 Data Latch Figure 9. Port 3 Configuration Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edgedetection circuit is through P31 or P20 (see "T8 and T16 Common Functions--"T8 PS024006-0605 Pin Functions ZGR163L Product Specification 19 and T16 Common Functions--CTR1(0D)01h" on page 31). Other edge detect and IRQ modes are described in Table 11. Note: Comparators are powered down by entering Stop Mode. For P31-P33 to be used in a Stop Mode Recovery (SMR) source, these inputs must be placed into Digital mode. 2 Table 11. Port 3 Pin Function Summary Pin I/O Pref1/P30 IN P31 IN P32 Counter/Timers Comparator Interrupt RF1 IN AN1 IRQ2 IN AN2 IRQ0 P33 IN RF2 IRQ1 P34 OUT T8 P35 OUT T16 P36 OUT T8/16 P37 OUT P20 I/O AO1 AO2 IN Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see Figure 10). Control is performed by programming bits D5-D4 of CTR1, bit 0 of CTR0, and bit 0 of CTR2. PS024006-0605 Pin Functions ZGR163L Product Specification 20 CTR0, D0 P34 data T8_Out MUX PCON, D0 VDD MUX Pad P34 P3M D1 P31 P31 P30 (Pref1) + - Comp1 CTR2, D0 Out 35 T16_Out VDD MUX Pad P35 CTR1, D6 Out 36 T8/T16_Out VDD MUX Pad P36 PCON, D0 P37 data VDD MUX P3M D1 Pad P37 P32 P32 P33 + - Comp2 Figure 10. Port 3 Counter/Timer Output Configuration PS024006-0605 Pin Functions ZGR163L Product Specification 21 Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 9 on page 18. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Note: Comparators are powered down by entering STOP mode. For P31-P33 to be used in a STOP Mode Recovery source, these inputs must be placed into Digital mode. Comparator Outputs These channels can be programmed to be output on P34 and P37 through the PCON register. Functional Description These devices incorporate special functions to enhance the Z8(R)'s functionality in consumer and battery-operated applications. Program Memory These devices address from 1KB to16KB of program memory. The first 12 Bytes are reserved for interrupt vectors. These locations contain the six 16-bit vectors that correspond to the six available interrupts. RAM The ZGR163L product family features 237 Bytes of general-purpose RAM. See Figure 11. PS024006-0605 Functional Description ZGR163L Product Specification 22 Maximum ROM size Location of first Byte of instruction executed after RESET Not Accessible On-Chip ROM 12 Reset Start Address 11 IRQ5 10 IRQ5 9 IRQ4 8 IRQ4 7 IRQ3 6 IRQ3 5 IRQ2 4 Interrupt Vector (Upper Byte) 3 IRQ2 2 IRQ1 1 IRQ0 0 IRQ0 Interrupt Vector (Lower Byte) IRQ1 Figure 11. Program Memory Map for ROM Expanded Register File The register file has been expanded to allow for additional system control registers and for mapping of additional peripheral devices into the register address area. The Z8 register address space (0 through15 (OFh) has been implemented as 16 banks, with 16 registers per bank. These register banks are known as the ERF (Expanded Register File). PS024006-0605 Functional Description ZGR163L Product Specification 23 Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred to as an expanded register group (see Figure 12). PS024006-0605 Functional Description ZGR163L Product Specification 24 Z8(R) Standard Control Registers Reset Condition D7 D6 D5 D4 D3 D2 D1 D0 Register** Register Pointer 7 6 5 4 3 2 1 0 Working Register Group Pointer Expanded Register Bank Pointer * * Register File (Bank 0)** FF F0 FF SPL U U U U U U U U FE SPH U U U U U U U U FD RP 0 0 0 0 0 0 0 0 FC FLAGS U U U U U U U U FB IMR U U U U U U U U FA IRQ F9 IPR 0 0 0 0 0 0 0 0 U U U U U U U U F8 P01M 1 1 0 0 1 1 1 1 F7 P3M 0 0 0 0 0 0 0 0 F6 P2M 1 1 1 1 1 1 1 1 F5 Reserved U U U U U U U U F4 Reserved U U U U U U U U F3 Reserved U U U U U U U U F2 Reserved U U U U U U U U F1 Reserved F0 Reserved U U U U U U U U U U U U U U U U Expanded Reg. Bank F/Group 0** * (F) 0F WDTMR U U 0 0 1 1 0 1 (F) 0E Reserved * (F) 0D SMR2 0 0 0 0 0 0 0 0 (F) 0C Reserved 7F (F) 0B SMR U 0 1 0 0 0 U 0 (F) 0A Reserved (F) 09 Reserved (F) 08 Reserved (F) 07 Reserved (F) 06 Reserved (F) 05 Reserved (F) 04 Reserved 0F 00 (F) 03 Reserved (F) 02 Reserved (F) 01 Reserved Expanded Reg. Bank 0/Group (0) (0) 03 P3 U 0 * (F) 00 PCON 1 1 1 1 1 1 1 0 Expanded Reg. Bank D/Group 0 (D) 0C LVD * * * (D) 0B HI8 U U U U U U U 0 0 0 0 0 0 0 0 0 (D) 0A LO8 0 0 0 0 0 0 0 0 (D) 09 HI16 (D) 08 LO16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U = Unknown * * (D) 07 TC16H * Is not reset with a Stop-Mode Recovery * (D) 06 TC16L * * (D) 05 TC8H 0 0 0 0 0 0 0 0 (D) 04 TC8L (D) 03 CTR3 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 (D) 02 CTR2 0 0 0 0 0 0 0 0 (D) 01 CTR1 (D) 00 CTR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0) 02 P2 U (0) 00 P0 U ** All addresses are in hexadecimal Is not reset with a Stop-Mode Recovery, except Bit 0 Bit 5 is not reset with a Stop-Mode Recovery Bits 5,4,3,2 not reset with a Stop-Mode Recovery Bits 5 and 4 not reset with a Stop-Mode Recovery Bits 5,4,3,2,1 not reset with a Stop-Mode Recovery 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12. Expanded Register File Architecture PS024006-0605 Functional Description ZGR163L Product Specification 25 The upper nibble of the register pointer (see Figure 13) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and banks 0, F, and D are implemented. A 0h in the lower nibble allows the normal register file (bank 0) to be addressed. Any other value from 1h to Fh exchanges the lower 16 registers to the selected expanded register bank. R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register File Pointer Default Setting After Reset = 0000 0000 Working Register Pointer Figure 13. Register Pointer Example: (See Figure 12 on page 24) R253 RP = 00h R0 = Port 0 R2 = Port 2 R3 = Port 3 But if: R253 RP = 0Dh R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved PS024006-0605 Functional Description ZGR163L Product Specification 26 The counter/timers are mapped into ERF group D. Access is easily performed using the following: LD RP, #0Dh ;Select ERF D for access to bank D ;(working register group 0) ;load CTR0 ;load CTR1 ;CTR2CTR1 LD LD LD R0,#xx 1, #xx R1, 2 LD RP, #0Dh LD working RP, #7Dh ;Select ERF D for access to bank D ; (working register group 0) ;Select expanded register bank D and LD LD 71h, 2 R1, 2 ;register group 7 of bank 0 for access. ;CTRL2register 71h ;CTRL2register 71h Register File The register file (bank 0) consists of 3 I/O port registers, 237 general-purpose registers, 14 control and status registers (R0, R2, R3, R4-R239, and R240-R255, respectively), and two expanded register Banks D (see Table 12) and F. Instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit register address to use the Register Pointer (Figure 14). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Register address E0h-EFh can only be accessed through working registers and indirect addressing modes. PS024006-0605 Functional Description ZGR163L Product Specification 27 R7 R6 R5 R4 R3 R2 R1 R R253 The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF F0 40 3F 30 2F 20 1F 10 0F 00 Specified Working Register Group Register Group 2 The lower nibble of the register file address provided by the instruction points to the specified register. Register Group 1 R15 to R0 Register Group 0 I/O Ports R15 to R4 * R3 to R0 * * RP = 00: Selects Register Bank 0, Working Register Group 0 Figure 14. Register Pointer--Detail Stack The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal stack that resides in the general-purpose registers (R4- R239). SPH (R254) can be used as a general-purpose register. PS024006-0605 Functional Description ZGR163L Product Specification 28 Timers T8_Capture_HI--HI8(0D)0Bh This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 1. Field Bit Position T8_Capture_HI [7:0] Description R/W Captured Data - No Effect T8_Capture_LO--L08(0D)0Ah This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 0. Field Bit Position T8_Capture_L0 [7:0] Description R/W Captured Data - No Effect T16_Capture_HI--HI16(0D)09h This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the MS-Byte of the data. Field Bit Position T16_Capture_HI [7:0] Description R/W Captured Data - No Effect T16_Capture_LO--L016(0D)08h This register holds the captured data from the output of the 16-bit Counter/ Timer16. This register holds the LS-Byte of the data. Field Bit Position T16_Capture_LO [7:0] Description R/W Captured Data - No Effect Counter/Timer2 MS-Byte Hold Register--TC16H(0D)07h PS024006-0605 Field Bit Position T16_Data_HI [7:0] Description R/W Data Functional Description ZGR163L Product Specification 29 Counter/Timer2 LS-Byte Hold Register--TC16L(0D)06h Field Bit Position T16_Data_LO [7:0] Description R/W Data Counter/Timer8 High Hold Register--TC8H0(D)05h Field Bit Position T8_Level_HI [7:0] Description R/W Data Counter/Timer8 Low Hold Register--TC8L(0D)04h Field Bit Position T8_Level_LO [7:0] Description R/W Data CTR0 Counter/Timer8 Control Register--CTR0(0D)00h Table 12 lists and briefly describes the fields for this register. Table 12. CTR0(0D)00h Counter/Timer8 Control Register Field Bit Position Value Description T8_Enable 7------- R/W 0* 1 0 1 Counter Disabled Counter Enabled Stop Counter Enable Counter Single/Modulo-N -6------- R/W 0* 1 Modulo-N Single Pass Time_Out --5------ R/W 0** 1 0 1 No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8 _Clock ---43--- R/W 0 0** 01 10 11 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0** 1 Disable Data Capture Interrupt Enable Data Capture Interrupt PS024006-0605 Functional Description ZGR163L Product Specification 30 Table 12. CTR0(0D)00h Counter/Timer8 Control Register (Continued) Field Bit Position Counter_INT_Mask ------1- P34_Out -------0 Value Description R/W 0** 1 Disable Time-Out Interrupt Enable Time-Out Interrupt R/W 0* 1 P34 as Port Output T8 Output on P34 Note: *Indicates the value at Power-On Reset. **Indicates the value at Per-On Reset. Not reset with a Stop-Mode recovery. T8 Enable This field enables T8 when set (written) to 1. Single/Modulo-N When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (Single-Pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its location. Caution: Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit before using/enabling the counter/timers. The first clock of T8 might not have complete clock width and can occur any time when enabled. Note: Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. T8 Clock This bit defines the frequency of the input signal to T8. PS024006-0605 Functional Description ZGR163L Product Specification 31 Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in Capture Mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. T8 and T16 Common Functions--CTR1(0D)01h This register controls the functions in common with the T8 and T16. Table 13 lists and briefly describes the fields for this register. Table 13. CTR1(0D)01h T8 and T16 Common Functions Field Mode Bit Position 7------- R/W P36_Out/ Capture_Input -6------ R/W Value 0* 1 0* 1 0* 1 T8/T16_Logic/ Edge _Detect --54---- R/W 00** 01 10 11 00** 01 10 11 PS024006-0605 Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Functional Description ZGR163L Product Specification 32 Table 13. CTR1(0D)01h T8 and T16 Common Functions (Continued) Field Transmit_Submode/ Glitch_Filter Bit Position ----32-- Value R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising Edge ------1R/W 0 1 R 0 1 0 1 W Initial_T16_Out/ Falling_Edge -------0 R/W 0 1 R 0 1 0 1 W Description Transmit Mode Normal Operation Ping-Pong Mode T16_Out = 0 T16_Out = 1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle Reserved Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0 Note: *Default at Power-On Reset **Indicates value upon Power-On Reset. Not reset with a Stop Mode recovery. Mode If the result is 0, the counter/timers are in Transmit mode; otherwise, they are in Demodulation Mode. P36_Out/Capture_Input In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/ Timers is from P20 or P31. PS024006-0605 Functional Description ZGR163L Product Specification 33 If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit D2 or use P20 as the input. T8/T16_Logic/Edge_Detect In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "Ping-Pong Mode" operation. When set to 10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. In Demodulation Mode, this field defines the width of the glitch that must be filtered out. Initial_T8_Out/Rising_Edge In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset the mode, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3; D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register--CTR2(0D)02h Table 14 lists and briefly describes the fields for this register. PS024006-0605 Functional Description ZGR163L Product Specification 34 Table 14. CTR2(0D)02h: Counter/Timer16 Control Register Field Bit Position T16_Enable 7------- R W Single/Modulo-N -6------ Value Description 0* 1 0 1 Counter Disabled Counter Enabled Stop Counter Enable Counter R/W 0 1 0 1 Time_Out --5----- Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge R 0** 1 W 0 1 No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 T16 _Clock ---43--- R/W 00** 01 10 11 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0** 1 Disable Data Capture Int. Enable Data Capture Int. Counter_INT_Mask ------1- R/W 0* 1 Disable Timeout Int. Enable Timeout Int. P35_Out -------0 R/W 0* 1 P35 as Port Output T16 Output on P35 Note: *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery. T16_Enable This field enables T16 when set to 1. Single/Modulo-N In Transmit Mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. When set to 1, the counter stops when the terminal count is reached. PS024006-0605 Functional Description ZGR163L Product Specification 35 In Demodulation Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode on page 43. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. Counter_INT_Mask Set this bit to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. CTR3 T8/T16 Control Register--CTR3(0d)03h Table 15 lists and briefly describes the fields for this register. This register allow the T8 and T16 counters to be synchronized. Table 15. CTR3(0D)03h T8/T16 Control Register T16_Enable 7------- R R WW 0* 1 0 1 Counter Disabled Counter Enabled Stop Counter Enable Counter T8 Enable -6------ R/W 0** 1 0 1 Counter Disabled Counter Enabled Stop Counter Enable Counter Sync Mode --5----- R/W 0* 1 Disable Sync Mode Enable Sync Mode Reserved ---43210 R/W 1 x Always reads 11111 No Effect Note: *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery. PS024006-0605 Functional Description ZGR163L Product Specification 36 Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5- D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 15). CTR1 D5,D4 P31 Glitch Filter MUX P20 CTR1 D6 Edge Detector Pos Edge Neg Edge CTR1 D3, D2 Figure 15. Glitch Filter Circuitry T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it is 1, T8_OUT is 0. See Figure 16. PS024006-0605 Functional Description ZGR163L Product Specification 37 T8 (8-Bit) Transmit Mode No T8_Enable Bit Set CTR0, D7 Yes Reset T8_Enable Bit 0 CTR1, D1 Value Load TC8H Set T8_OUT Load TC8L Reset T8_OUT Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled 1 Enable T8 No T8_Timeout Yes Single Pass Single Pass? Modulo-N 1 T8_OUT Value Load TC8L Reset T8_OUT Load TC8H Set T8_OUT Enable T8 No 0 Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled T8_Timeout Yes Figure 16. Transmit Mode Flowchart PS024006-0605 Functional Description ZGR163L Product Specification 38 When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In Single-Pass Mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. From that point, T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One cycle is complete. T8 then loads from TC8H or TC8L according to the T8_OUT level and repeats the cycle. See Figure 17. Z8(R) Data Bus CTR0 D2 Positive Edge IRQ4 Negative Edge HI8 LO8 CTR0 D1 CTR0 D4, D3 SCLK Clock Clock Select TC8H 8-Bit Counter T8 T8_OUT TC8L Z8(R) Data Bus Figure 17. 8-Bit Counter/Timer Circuits The values in TC8H or TC8L can be modified at any time. The new values take effect when they are loaded. Caution: PS024006-0605 To ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed (a non-function occurs). An initial count of 0 causes TC8 to count from 0 to FFh to FEh. Functional Description ZGR163L Product Specification 39 Note: The letter h denotes hexadecimal values. Transition from 0 to FFh is not a timeout condition. Caution: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Second, the status bits must be reset. These commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. See Figure 18 and Figure 19. TC8H Counts Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) T8_OUT Toggles; Timeout Interrupt Figure 18. T8_OUT in Single-Pass Mode T8_OUT Toggles ... T8_OUT TC8L TC8H Counter Enable Command; T8_OUT Switches to Its Initial Value (CTR1 D1) TC8L Timeout Interrupt TC8H TC8L Timeout Interrupt Figure 19. T8_OUT in Modulo-N Mode T8 Demodulation Mode The user must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put into HI8. From that point, one of the PS024006-0605 Functional Description ZGR163L Product Specification 40 edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh (see Figure 21 and Figure 21). T8 (8-Bit) Count Capture No T8 Enable (Set by User) Yes No Edge Present Yes Positive What Kind of Edge Negative T8 HI8 T8 LO8 FFh T8 Figure 20. Demodulation Mode Count Capture Flowchart PS024006-0605 Functional Description ZGR163L Product Specification 41 T8 (8-Bit) Capture Mode No T8 Enable CTR0, D7 Yes FFh TC8 No First Edge Present Yes Enable TC8 Disable TC8 No T8_Enable Bit Set Yes Edge Present No Yes Set Edge Present Status Bit and Trigger Data Capture Int. If Enabled No T8 Timeout Yes Set Timeout Status Bit and Trigger Timeout Int. If Enabled Continue Counting Figure 21. Demodulation Mode Flowchart PS024006-0605 Functional Description ZGR163L Product Specification 42 T16 Transmit Mode In Normal or Ping-Pong mode, the output of T16 when not enabled, is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a status bit (CTR2, D5) is set. See Figure 22. Z8(R) Data Bus CTR2 D2 Positive Edge IRQ3 Negative Edge HI16 LO16 CTR2 D1 CTR2 D4, D3 SCLK Clock Select Clock TC16H 16-Bit Counter T16 T16_OUT TC16L Z8(R) Data Bus Figure 22. 16-Bit Counter/Timer Circuits Note: Global interrupts override this function as described in "Interrupts" on page 46. If T16 is in Single-Pass mode, it is stopped at this point (see Figure 23). If it is in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 24). The values in TC16H and TC16L can be modified at any time. The new values take effect when they are loaded. PS024006-0605 Functional Description ZGR163L Product Specification 43 Caution: Do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a timeout condition. TC16H*256+TC16L Counts "Counter Enable" Command T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt Figure 23. T16_OUT in Single-Pass Mode TC16H*256+TC16L TC16H*256+TC16L ... TC16_OUT TC16H*256+TC16L "Counter Enable" Command, T16_OUT Switches to Its Initial Value (CTR1 D0) T16_OUT Toggles, Timeout Interrupt T16_OUT Toggles, Timeout Interrupt Figure 24. T16_OUT in Modulo-N Mode T16 Demodulation Mode The user must program TC16L and TC16H to FFh. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. If D6 of CTR2 Is 0 When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current count in T16 is complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFh and starts again. This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). PS024006-0605 Functional Description ZGR163L Product Specification 44 If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent edges. This T16 mode generally measures mark time, the length of an active carrier signal burst. If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 must be programmed in Single-Pass mode (CTR0, D6; CTR2, D6), and Ping-Pong mode must be programmed in CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 25. Note: Enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and reset the status flags before instituting this operation. PS024006-0605 Functional Description ZGR163L Product Specification 45 Enable TC8 Timeout Enable Ping-Pong CTR1 D3,D2 TC16 Timeout Figure 25. Ping-Pong Mode Diagram Initiating Ping-Pong Mode First, make sure both counter/timers are not running. Set T8 into Single-Pass mode (CTR0, D6), set T16 into Single-Pass mode (CTR2, D6), and set the PingPong mode (CTR1, D2; D3). These instructions can be in random order. Finally, start Ping-Pong mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 26. P34_Internal MUX P34 CTR0 D0 T8_OUT T16_OUT CTR1, D2 P36_Internal AND/OR/NOR/NAND Logic MUX MUX P36 CTR1 D6 CTR1 D5, D4 P35_Internal MUX CTR1 D3 P35 CTR2 D0 Figure 26. Output Circuit The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. PS024006-0605 Functional Description ZGR163L Product Specification 46 During Ping-Pong Mode The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers reach the terminal count. Interrupts The ZGR163L features six different interrupts (Table 16). The interrupts are maskable and prioritized (Figure 27). The six sources are divided as follows: three sources are claimed by Port 3 lines P33-P31, two by the counter/timers (Table 16) and one for low voltage detection. The Interrupt Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in digital mode, Pin P33 is the source. When in Analog mode the output of the Stop Mode Recovery source logic is used as the source for the interrupt. See Figure 32, Stop Mode Recovery Source, on page 54. PS024006-0605 Functional Description ZGR163L Product Specification 47 P33 Stop Mode Recovery Source 0 P31 IRQ Register D6, D7 D1 of P3M Register P32 Interrupt Edge Select IRQ2 1 IRQ0 Timer 16 IRQ1 IRQ3 Timer 8 IRQ4 Low-Voltage Detection IRQ5 IRQ IMR 6 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 27. Interrupt Block Diagram PS024006-0605 Functional Description ZGR163L Product Specification 48 Table 16. Interrupt Types, Sources, and Vectors Name Source Vector Location Comments IRQ0 P32 0,1 External (P32), Rising, Falling Edge Triggered IRQ1 P33 2,3 External (P33), Falling Edge Triggered IRQ2 P31, TIN 4,5 External (P31), Rising, Falling Edge Triggered IRQ3 T16 6,7 Internal IRQ4 T8 8,9 Internal IRQ5 LVD 10,11 Internal When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle activates when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All ZGR163L interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge triggered. These interrupts are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 17. Table 17. IRQ Register IRQ Interrupt Edge D7 D6 IRQ2 (P31) IRQ0 (P32) 0 0 F F 0 1 F R 1 0 R F 1 1 R/F R/F Note: F = Falling Edge; R = Rising Edge PS024006-0605 Functional Description ZGR163L Product Specification 49 Clock The device's on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 . The on-chip oscillator can be driven with a suitable external clock source. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. C1 C2 XTAL1 XTAL1 XTAL2 XTAL2 Crystal f = 8MHz; C1, C2 = 33Pf Typ # External Clock XTAL1 * Preliminary value including pin parasitics XTAL2 Ceramic Resonator f = 8mHz Figure 28. Oscillator Configuration Power-On Reset A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VDD and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: * * * PS024006-0605 Power Fail to Power OK status, including Waking up from VBO Standby Stop-Mode Recovery (if D5 of SMR = 1) WDT Timeout Functional Description ZGR163L Product Specification 50 The POR timer is 1 ms minimum. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock). Halt Mode This instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit Halt Mode. After the interrupt service routine, the program continues from the instruction after the Halt. Stop Mode This instruction turns off the internal clock and external crystal oscillation, reducing the standby current to 10 A or less. Stop Mode is terminated only by a reset, such as WDT timeout, POR or SMR. This condition causes the processor to restart the application program at address 000Ch. In order to enter Stop (or Halt) mode, first flush the instruction pipeline to avoid suspending execution in midinstruction. Execute an NOP instruction (Opcode = FFh) immediately before the appropriate sleep instruction, as follows: FF 6F NOP STOP ; clear the pipeline ; enter Stop Mode FF 7F NOP HALT ; clear the pipeline ; enter Halt Mode or PS024006-0605 Functional Description ZGR163L Product Specification 51 Port Configuration Register The Port Configuration (PCON) register (Figure 29) configures the comparator output on Port 3. It is located in the expanded register file at Bank F, location 00. PCON (0F) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Reserved (Must be 1) Port 0 0: Open-Drain 1: Push-Pull* Reserved (Must be 1) * Default setting after reset Figure 29. Port Configuration Register (PCON) (Write Only) Comparator Output Port 3 (D0) Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. Port 0 Output Mode (D2) Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. Stop-Mode Recovery Register (SMR) This register selects the clock divide value and determines the mode of Stop Mode Recovery (Figure 30). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level at the XORgate input (Figure 32 on page 54) is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4 of the SMR register specify the source of the Stop-Mode Recovery signal. Bits D0 determines if SCLK/ PS024006-0605 Functional Description ZGR163L Product Specification 52 TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded Register File at address 0Bh. SMR (0F) 0BH D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery * * * Default after Power On Reset or Watch-Dog Reset * * Default setting after Reset and Stop Mode Recovery * * * At the XOR gate input * * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source. Figure 30. Stop Mode Recovery Register SCLK/TCLK Divide-by-16 Select (D0) D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 31). This control selectively reduces device power consumption during normal processor execution (SCLK control) and/or Halt Mode (where TCLK sources interrupt logic). After Stop-Mode Recovery, this bit is set to 0. PS024006-0605 Functional Description ZGR163L Product Specification 53 OSC /2 / 16 SCLK SMR, D0 TCLK Figure 31. SCLK Circuit Stop-Mode Recovery Register 2--SMR2(0F)0DH Table 18 lists and describes the fields for this register. Table 18. SMR2(F)0DH:Stop Mode Recovery Register 2* Field Bit Position Value Description Reserved 7------- 0 Reserved (Must be 0) -6------ 0 1 Low High --5----- 0 Reserved (Must be 0) ---432-- 000 001 010 011 100 101 110 111 A. POR Only B. NAND of P23-P20 C. NAND of P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22-P20 00 Reserved (Must be 0) Recovery Level Reserved Source Reserved ------10 W W Notes: * Port pins configured as outputs are ignored as an SMR recovery source. Indicates the value at Power-On Reset Stop-Mode Recovery Source (D2, D3, and D4) These three bits of the SMR specify the wake-up source of the Stop recovery (Figure 32 and Table 19). PS024006-0605 Functional Description ZGR163L Product Specification 54 VCC SMR D4 D3 D2 0 0 0 SMR D4 D3 D2 0 1 0 VCC P20 SMR2 D4 D3 D2 0 0 0 SMR2 D4 D3 D2 0 0 1 P31 P23 SMR D4 D3 D2 0 1 1 P32 P27 SMR D4 D3 D2 1 0 0 P33 SMR D4 D3 D2 1 0 1 P27 P20 SMR D4 D3 D2 1 1 0 P23 P20 P20 SMR2 D4 D3 D2 0 1 0 SMR D4 D3 D2 1 1 1 P27 SMR D6 To RESET and WDT Circuitry (Active Low) P31 P32 P33 P31 P32 P33 P31 P32 P33 P00 P07 P31 P32 P33 P00 P07 P31 P32 P33 P20 P21 SMR2 D4 D3 D2 0 1 1 SMR2 D4 D3 D2 1 0 0 SMR2 D4 D3 D2 1 0 1 SMR2 D4 D3 D2 1 1 0 SMR2 D4 D3 D2 1 1 1 SMR2 D6 Figure 32. Stop Mode Recovery Source PS024006-0605 Functional Description ZGR163L Product Specification 55 Table 19. Stop Mode Recovery Source SMR:432 Operation D4 D3 D2 Description of Action 0 0 0 POR and/or external reset recovery 0 0 1 Reserved 0 1 0 P31 transition 0 1 1 P32 transition 1 0 0 P33 transition 1 0 1 P27 transition 1 1 0 Logical NOR of P20 through P23 1 1 1 Logical NOR of P20 through P27 Note: Any Port 2 bit defined as an output drives the corresponding input to the default state. This condition allows the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 56 for other recover sources. Stop Mode Recovery Delay Select (D5) This bit, if Low, disables the TPOR delay after Stop Mode Recovery. The default configuration of this bit is 1. If the "fast" wake up is selected, the Stop Mode Recovery source must be kept active for at least 5 TpC. Note: This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay allows the clock source to stabilize before executing instructions. Stop Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z8 GPTM MCU from Stop Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR). PS024006-0605 Functional Description ZGR163L Product Specification 56 Stop Mode Recovery Register 2 (SMR2) This register determines the mode of Stop Mode Recovery for SMR2 (Figure 33). SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low * 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset * * At the XOR gate input Figure 33. Stop Mode Recovery Register 2 ((0F) DH:D2-D4, D6 Write Only) If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop Mode Recovery. Note: Port pins configured as outputs are ignored as an SMR or SMR2 recovery source. For example, if the NAND or P23-P20 is selected as the recovery source and P20 is configured as an output, the remaining SMR pins (P23-P21) form the NAND equation. PS024006-0605 Functional Description ZGR163L Product Specification 57 Watch-Dog Timer Mode Register (WDTMR) The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control a tap circuit that determines the minimum timeout period. Bit 2 determines whether the WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits 4 through 7 are reserved (Figure 34). This register is accessible only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 33). After this point, the register cannot be modified by any means (intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F of the Expanded Register File at address location 0Fh. It is organized as illustrated in Figure 34. WDTMR (0F) 0FH D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. WDT During Halt 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0) * Default setting after reset Figure 34. Watch-Dog Timer Mode Register (Write Only) WDT Time Select (D0, D1) This bit selects the WDT time period. It is configured as indicated in Table 20. PS024006-0605 Functional Description ZGR163L Product Specification 58 Table 20. Watch-Dog Timer Time Select D1 D0 Timeout of Internal RC-Oscillator 0 0 10 ms min. 0 1 20 ms min. 1 0 40 ms min. 1 1 160 ms min. WDTMR During Halt (D2) This bit determines whether or not the WDT is active during Halt Mode. A 1 indicates active during Halt. The default is 1. See Figure 35. 5 Clock Filter *CLR2 RESET 18 Clock RESET Internal RESET Active High WDT XTAL Internal RC Oscillator. VDD VBO + - POR 10 ms 20 ms 40 ms 160 ms CL WDT/POR Counter Chain *CLR Low Operating Voltage Det. WDT From Stop Mode Recovery Source VDD 12-ns Glitch Filter Stop Delay Select (SMR) * CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High input translation. Figure 35. Resets and WDT PS024006-0605 Functional Description ZGR163L Product Specification 59 WDTMR During Stop (D3) This bit determines whether or not the WDT is active during Stop Mode. A 1 indicates active during Stop. The default is 1. ROM Selectable Options There are five ROM Selectable Options to choose from based on ROM code requirements. These options are listed in Table 21. Table 21. ROM Selectable Options Port 00-03 Pull-Ups On/Off Port 04-07 Pull-Ups On/Off Port 20-27 Pull-Up Port 3 Pull-Ups On/Off Port 3 Pull-Ups On/Off Watch-Dog Timer at Power-On Reset On/Off Voltage Brown-Out/Standby An on-chip Voltage Comparator checks that the VDD is at the required level for correct operation of the device. Reset is globally driven when VDD falls below VBO. A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally. Low-Voltage Detection Register--LVD(0D)0CH Note: Voltage detection does not work at Stop mode. It must be disabled during Stop mode in order to reduce current. Field Bit Position Description LVD 765432--- Reserved -----2 R 1 0* HVD flag set HVD flag reset ------1- R 1 0* LVD flag set LVD flag reset -------0 R/W 1 0* Enable VD Disable VD *Default after POR PS024006-0605 Functional Description ZGR163L Product Specification 60 Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both ports 0 and 1 together might trigger the LVD flag. Voltage Detection and Flags The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit 0 of LVD register is set. When Voltage Detection is enabled, the the VCC level is monitored in real time. The flags in the LVD register valid 20uS after Voltage Detection is enabled. The HVD flag (bit 2 of the LVD register) is set only if VCC is lower than the VHVD. When Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only. Note: If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower than the low battery detect threshold, enable interrupts using the Enable Interrupt instruction (EI) prior to enabling the voltage detection. PS024006-0605 Functional Description ZGR163L Product Specification 61 Expanded Register File Control Registers (0D) The expanded register file control registers (0D) are depicted in Figure 36 through Figure 40. CTR0 (0D) 00H D7 D6 D5 D4 D3 D2 D1 D0 0 P34 as Port Output * 1 Timer8 Output 0 Disable T8 Timeout Interrupt** 1 Enable T8 Timeout Interrupt 0 Disable T8 Data Capture Interrupt** 1 Enable T8 Data Capture Interrupt 00 01 10 11 R R W W SCLK on T8** SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Timeout** 1 T8 Counter Timeout Occurred 0 No Effect 1 Reset Flag to 0 0 Modulo-N* 1 Single Pass R R W W 0 T8 Disabled * 1 T8 Enabled 0 Stop T8 1 Enable T8 * Default setting after reset. **Default setting after Reset. Not reset with a Stop Mode recovery. Figure 36. TC8 Control Register ((0D) 00H: Read/Write Except Where Noted) PS024006-0605 Expanded Register File Control Registers (0D) ZGR163L Product Specification 62 CTR1 (0D) 01H D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode* R/W 0 T16_OUT is 0 initially* 1 T16_OUT is 1 initially Capture Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode* R/W 0 T8_OUT is 0 initially* 1 T8_OUT is 1 initially Capture Mode R 0 No Rising Edge Detection R 1 Rising Edge Detection W 0 No Effect W 1 Reset Flag to 0 Transmit Mode* 0 0 Normal Operation* 0 1 Ping-Pong Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 Capture Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 Reserved Transmit Mode/T8/T16 Logic 0 0 AND** 0 1 OR 1 0 NOR 1 1 NAND Capture Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved Transmit Mode 0 P36 as Port Output * 1 P36 as T8/T16_OUT Capture Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input * Default setting after reset. **Default setting after Reset. Not reset with a Stop Mode recovery. Transmit/Capture Mode 0 Transmit Mode * 1 Capture Mode Figure 37. T8 and T16 Common Control Functions ((0D) 01H: Read/Write) PS024006-0605 Expanded Register File Control Registers (0D) ZGR163L Product Specification 63 Notes: Take care in differentiating the Transmit Mode from Capture Mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be performed without disabling the counter/timers. CTR2 (0D) 02H D7 D6 D5 D4 D3 D2 D1 D0 0 P35 is Port Output * 1 P35 is TC16 Output 0 Disable T16 Timeout Interrupt* 1 Enable T16 Timeout Interrupt 0 Disable T16 Data Capture Interrupt** 1 Enable T16 Data Capture Interrupt 0 0 1 1 0 1 0 1 SCLK on T16** SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 R R W W 0 1 0 1 No T16 Timeout** T16 Timeout Occurs No Effect Reset Flag to 0 Transmit Mode 0 Modulo-N for T16* 1 Single Pass for T16 Capture Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge * Default setting after reset. **Default setting after Reset. Not reset with a Stop Mode recovery. R R W W 0 1 0 1 T16 Disabled* T16 Enabled Stop T16 Enable T16 Figure 38. T16 Control Register ((0D) 02H: Read/Write Except Where Noted) PS024006-0605 Expanded Register File Control Registers (0D) ZGR163L Product Specification 64 CTR3 (0D) 03H D7 D6 D5 D4 D3 D2 D1 D0 Reserved No effect when written Always reads 11111 Sync Mode 0* Disable Sync Mode** 1 Enable Sync Mode T8 Enable R 0* T8 Disabled R 1 T8 Enabled W0 Stop T8 W1 Enable T8 T16 Enable R 0* T16 Disabled R 1 T16 Enabled * Default setting after reset. **Default setting after Reset. Not reset with a Stop W 0 Stop T16 W 1 Enable T16 Mode recovery. Figure 39. T8/T16 control Register (0D) 03H: Read/Write (Except Where Noted) Note: If Sync Mode is enabled, the first pulse of T8 (carrier) is always synchronized with T16 (demodulated signal). It can always provide a full carrier pulse. PS024006-0605 Expanded Register File Control Registers (0D) ZGR163L Product Specification 65 LVD (0D) 0CH D7 D6 D5 D4 D3 D2 D1 D0 Voltage Detection 0: Disable * 1: Enable LVD Flag (Read only) 0: LVD flag reset * 1: LVD flag set HVD Flag (Read only) 0: HVD flag reset * 1: HVD flag set Reserved (Must be 0) * Default Figure 40. Voltage Detection Register Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are depicted in Figures 41 through Figure 54. PS024006-0605 Expanded Register File Control Registers (0F) ZGR163L Product Specification 66 PCON (0F) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output * 1 P34, P37 Comparator Output Reserved. (Must be 1) Port 0 0: Open-Drain 1: Push-Pull * Reserved (Must be 1) * Default setting after reset Figure 41. Port Configuration Register (PCON) ((0F)00H: Write Only PS024006-0605 Expanded Register File Control Registers (0F) ZGR163L Product Specification 67 SMR (0F) 0BH D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF * 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * * 001 Reserved 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * * * * Stop Recovery Level * * * 0 Low * * 1 High Stop Flag 0 POR * * * * * 1 Stop Recovery * * * Default setting after Reset * * Set after STOP Mode Recovery * * * At the XOR gate input * * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source. Not reset with a Stop Mode recovery. * * * * * Default setting after Power On Reset. Figure 42. Stop Mode Recovery Register ((0F) 0BH: D6-D0=Write Only, D7=Read Only) PS024006-0605 Expanded Register File Control Registers (0F) ZGR163L Product Specification 68 SMR2 (0F) 0DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR Only * 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level * * 0 Low 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery. * Default setting after reset. Not reset with a Stop Mode recovery. * * At the XOR gate input Figure 43. Stop Mode Recovery Register 2 ((0F) 0DH: D2-D4, D6 Write Only) PS024006-0605 Expanded Register File Control Registers (0F) ZGR163L Product Specification 69 WDTMR (0F) 0FH D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP INT RC OSC 00--10 ms min. 01--20 ms min.* 10--40 ms min. 11--80 ms min. WDT During Halt 0 OFF 1 ON * WDT During Stop 0 OFF 1 ON * Reserved (Must be 0) * Default setting after reset. Not reset with a Stop Mode recovery. Figure 44. Watch-Dog Timer Register ((0F) 0FH: Write Only) Standard Control Registers R246 P2M (F6H) D7 D6 D5 D4 D3 D2 D1 D0 P27-P20 I/O Definition 0 Defines bit as OUTPUT 1 Defines bit as INPUT * * Default setting after reset. Not reset with a Stop Mode recovery. Figure 45. Port 2 Mode Register (F6H: Write Only) PS024006-0605 Standard Control Registers ZGR163L Product Specification 70 R247 P3M (F7H) D7 D6 D5 D4 D3 D2 D1 D0 0: Port 2 Open Drain * 1: Port 2 Push-Pull 0= P31, P32 Digital Mode* 1= P31, P32 Analog Mode Reserved (Must be 0) * Default setting after reset. Not reset with a Stop Mode recovery. Figure 46. Port 3 Mode Register (F7H: Write Only) PS024006-0605 Standard Control Registers ZGR163L Product Specification 71 R248 P01M (F8H) D7 D6 D5 D4 D3 D2 D1 D0 P00-P03 Mode 0: Output 1: Input * Reserved (Must be 0) Reserved (Must be 1) Reserved (Must be 0) P07-P04 Mode 0: Output 1: Input * Reserved (Must be 0) * Default setting after reset; only P00, P01 and P07 are available on 20-pin configurations. Figure 47. Port 0 Register (F8H: Write Only) PS024006-0605 Standard Control Registers ZGR163L Product Specification 72 R249 IPR (F9H) D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4, Priority (Group C) 0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 IRQ0, IRQ2, Priority (Group B) 0: IRQ2 > IRQ0 1: IRQ0 > IRQ2 IRQ3, IRQ5, Priority (Group A) 0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 Reserved; must be 0 Figure 48. Interrupt Priority Register (F9H: Write Only) PS024006-0605 Standard Control Registers ZGR163L Product Specification 73 R250 IRQ (FAH) D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 IRQ5 = LVD Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11 Figure 49. Interrupt Request Register (FAH: Read/Write) R251 IMR (FBH) D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Reserved (Must be 0) 0 Master Interrupt Disable * 1 Master Interrupt Enable * * * Default setting after reset * * Only by using EI, DI instruction; DI is required before changing the IMR register Figure 50. Interrupt Mask Register (FBH: Read/Write) PS024006-0605 Standard Control Registers ZGR163L Product Specification 74 R252 Flags (FCH) D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Tag Zero Flag Carry Flag Figure 51. Flag Register (FCH: Read/Write) R253 RP (FDH) D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Pointer Working Register Pointer Default setting after reset = 0000 0000 Figure 52. Register Pointer (FDH: Read/Write) PS024006-0605 Standard Control Registers ZGR163L Product Specification 75 R254 SPH (FEH) D7 D6 D5 D4 D3 D2 D1 D0 General-Purpose Register Figure 53. Stack Pointer High (FEH: Read/Write) R255 SPL (FFH) D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Low Byte (SP7-SP0) Figure 54. Stack Pointer Low (FFH: Read/Write) Package Information Package information for all device versions of the ZGR163L is depicted in Figures 55 through Figure 60. PS024006-0605 Package Information ZGR163L Product Specification 76 Figure 55. 20-Pin DIP Package Diagram Figure 56. 20-Pin SOIC Package Diagram PS024006-0605 Package Information ZGR163L Product Specification 77 Figure 57. 20-Pin SSOP Package Diagram PS024006-0605 Package Information ZGR163L Product Specification 78 Figure 58. 28-Pin SOIC Package Diagram PS024006-0605 Package Information ZGR163L Product Specification 79 Figure 59. 28-Pin DIP Package Diagram PS024006-0605 Package Information ZGR163L Product Specification 80 D 28 C 15 MILLIMETER SYMBOL H E 1 14 DETAIL A NOM MAX MIN NOM MAX A 1.73 1.86 1.99 0.068 0.073 0.078 A1 0.05 0.13 0.21 0.002 0.005 0.008 A2 1.68 1.73 1.78 0.066 0.068 0.070 B 0.25 0.38 0.010 C 0.09 0.20 0.004 0.006 0.008 D 10.07 10.20 10.33 0.397 0.402 0.407 E 5.20 5.30 5.38 0.205 0.209 0.212 0.65 TYP e 0.015 0.0256 TYP H 7.65 7.80 7.90 0.301 0.307 0.311 L 0.63 0.75 0.95 0.025 0.030 0.037 A1 Q1 INCH MIN A2 e A B SEATING PLANE CONTROLLING DIMENSIONS: MM LEADS ARE COPLANAR WITHIN .004 INCHES. L 0-8 DETAIL 'A' Figure 60. 28-Pin SSOP Package Diagram Note: Please check with ZiLOG(R) on the actual bonding diagram and coordinate for chip-on-board assembly. PS024006-0605 Package Information ZGR163L Product Specification 81 Ordering Information 16KB Standard Temperature: 0 to +70C Part Number Description Part Number Description ZGR163LSH2816C 28-pin SSOP 16K ROM ZGR163LSH2016C 20-pin SSOP 16K ROM ZGR163LSP2816C 28-pin PDIP 16K ROM ZGR163LSP2016C 20-pin PDIP 16K ROM ZGR163LSS2816C 28-pin SOIC 16K ROM ZGR163LSS2016C 20-pin SOIC 16K ROM 16KB Extended Temperature: -40 to +105C Part Number Description Part Number Description ZGR163LEH2816C 28-pin SSOP 16K ROM ZGR163LEH2016C 20-pin SSOP 16K ROM ZGR163LEP2816C 28-pin PDIP 16K ROM ZGR163LEP2016C 20-pin PDIP 16K ROM ZGR163LES2816C 28-pin SOIC 16K ROM ZGR163LES2016C 20-pin SOIC 16K ROM 16KB Automotive Temperature: -40 to +125C Part Number Description Part Number ZGR163LAH2816C 28-pin SSOP 16K ROM ZGR163LAH2016C ZGR163LAP2816C 28-pin PDIP 16K ROM Description 20-pin SSOP 16K ROM ZGR163LAP2016C 20-pin PDIP 16K ROM ZGR163LAS2816C 28-pin SOIC 16K ROM ZGR163LAS2016C 20-pin SOIC 16K ROM Replace C with G for Lead-Free Packaging PS024006-0605 Ordering Information ZGR163L Product Specification 82 8KB Standard Temperature: 0 to +70C Part Number Description Part Number Description ZGR163LSH2808C 28-pin SSOP 8K ROM ZGR163LSH2008C 20-pin SSOP 8K ROM ZGR163LSP2808C 28-pin PDIP 8K ROM ZGR163LSP2008C 20-pin PDIP 8K ROM ZGR163LSS2808C 28-pin SOIC 8K ROM ZGR163LSS2008C 20-pin SOIC 8K ROM Part Number Description ZGR163LEH2808C 28-pin SSOP 8K ROM ZGR163LEH2008C 20-pin SSOP 8K ROM ZGR163LEP2808C 28-pin PDIP 8K ROM ZGR163LEP2008C 20-pin PDIP 8K ROM ZGR163LES2808C 28-pin SOIC 8K ROM ZGR163LES2008C 20-pin SOIC 8K ROM 8KB Extended Temperature: -40 to +105C Part Number Description 8KB Automotive Temperature: -40 to +125C Part Number Description Part Number Description ZGR163LAH2808C 28-pin SSOP 8K ROM ZGR163LAH2008C 20-pin SSOP 8K ROM ZGR163LAP2808C 28-pin PDIP 8K ROM ZGR163LAP2008C 20-pin PDIP 8K ROM ZGR163LAS2808C 28-pin SOIC 8K ROM ZGR163LAS2008C 20-pin SOIC 8K ROM Replace C with G for Lead-Free Packaging PS024006-0605 Ordering Information ZGR163L Product Specification 83 4KB Standard Temperature: 0 to +70C Part Number Description Part Number Description ZGR163LSH2804C 28-pin SSOP 4K ROM ZGR163LSH2004C 20-pin SSOP 4K ROM ZGR163LSP2804C 28-pin PDIP 4K ROM ZGR163LSP2004C 20-pin PDIP 4K ROM ZGR163LSS2804C 28-pin SOIC 4K ROM ZGR163LSS2004C 20-pin SOIC 4K ROM Part Number Description ZGR163LEH2804C 28-pin SSOP 4K ROM ZGR163LEH2004C 20-pin SSOP 4K ROM ZGR163LEP2804C 28-pin PDIP 4K ROM ZGR163LEP2004C 20-pin PDIP 4K ROM ZGR163LES2804C 28-pin SOIC 4K ROM ZGR163LES2004C 20-pin SOIC 4K ROM 4KB Extended Temperature: -40 to +105C Part Number Description 4KB Automotive Temperature: -40 to +125C Part Number Description Part Number Description ZGR163LAH2804C 28-pin SSOP 4K ROM ZGR163LAH2004C 20-pin SSOP 4K ROM ZGR163LAP2804C 28-pin PDIP 4K ROM ZGR163LAP2004C 20-pin PDIP 4K ROM ZGR163LAS2804C 28-pin SOIC 4K ROM ZGR163LAS2004C 20-pin SOIC 4K ROM Replace C with G for Lead-Free Packaging PS024006-0605 Ordering Information ZGR163L Product Specification 84 2KB Standard Temperature: 0 to +70C Part Number Description Part Number Description ZGR163LSH2802C 28-pin SSOP 2K ROM ZGR163LSH2002C 20-pin SSOP 2K ROM ZGR163LSP2802C 28-pin PDIP 2K ROM ZGR163LSP2002C 20-pin PDIP 2K ROM ZGR163LSS2802C 28-pin SOIC 2K ROM ZGR163LSS2002C 20-pin SOIC 2K ROM Part Number Description ZGR163LEH2802C 28-pin SSOP 2K ROM ZGR163LEH2002C 20-pin SSOP 2K ROM ZGR163LEP2802C 28-pin PDIP 2K ROM ZGR163LEP2002C 20-pin PDIP 2K ROM ZGR163LES2802C 28-pin SOIC 2K ROM ZGR163LES2002C 20-pin SOIC 2K ROM 2KB Extended Temperature: -40 to +105C Part Number Description 2KB Automotive Temperature: -40 to +125C Part Number Description Part Number Description ZGR163LAH2802C 28-pin SSOP 2K ROM ZGR163LAH2002C 20-pin SSOP 2K ROM ZGR163LAP2802C 28-pin PDIP 2K ROM ZGR163LAP2002C 20-pin PDIP 2K ROM ZGR163LAS2802C 28-pin SOIC 2K ROM ZGR163LAS2002C 20-pin SOIC 2K ROM Replace C with G for Lead-Free Packaging PS024006-0605 Ordering Information ZGR163L Product Specification 85 1KB Standard Temperature: 0 to +70C Part Number Description Part Number Description ZGR163LSH2801C 28-pin SSOP 1K ROM ZGR163LSH2001C 20-pin SSOP 1K ROM ZGR163LSP2801C 28-pin PDIP 1K ROM ZGR163LSP2001C 20-pin PDIP 1K ROM ZGR163LSS2801C 28-pin SOIC 1K ROM ZGR163LSS2001C 20-pin SOIC 1K ROM Part Number Description ZGR163LEH2801C 28-pin SSOP 1K ROM ZGR163LEH2001C 20-pin SSOP 1K ROM ZGR163LEP2801C 28-pin PDIP 1K ROM ZGR163LEP2001C 20-pin PDIP 1K ROM ZGR163LES2801C 28-pin SOIC 1K ROM ZGR163LES2001C 20-pin SOIC 1K ROM 1KB Extended Temperature: -40 to +105C Part Number Description 1KB Automotive Temperature: -40 to +125C Part Number Description Part Number Description ZGR163LAH2801C 28-pin SSOP 1K ROM ZGR163LAH2001C 20-pin SSOP 1K ROM ZGR163LAP2801C 28-pin PDIP 1K ROM ZGR163LAP2001C 20-pin PDIP 1K ROM ZGR163LAS2801C 28-pin SOIC 1K ROM ZGR163LAS2001C 20-pin SOIC 1K ROM Part Number Description Replace C with G for Lead-Free Packaging Additional Components Part Number Description ZGP323ICE15ZEM Emulator/programmer (For 3.6V Emulation only) ZGP32300100ZPR Programming system (Ethernet) ZGP32300200ZPR Programming system (USB) PS024006-0605 Ordering Information ZGR163L Product Specification 86 For fast results, contact your local ZiLOG sales office for assistance in ordering the part desired. Example ZG R 163 L S P 28 16 C Molding Compound Memory Size Number of Pins Package Type: E = CDIP P = PDIP H = SSOP S = SOIC Temperature: S = Standard E = Extended A = Automotive Voltage: L = 2.0V t0 3.6V Family Designation ROM ZiLOG General-Purpose Family PS024006-0605 Ordering Information ZGR163L Product Specification 87 Index Numerics 16-bit counter/timer circuits 42 20-pin DIP package diagram 76 20-pin SSOP package diagram 77 28-pin DIP package diagram 79 28-pin SOICpackage diagram 78 28-pin SSOP package diagram 80 8-bit counter/timer circuits 38 A absolute maximum ratings 6 AC characteristics 13 timing diagram 13 address spaces, basic 2 architecture 2 expanded register file 24 B basic address spaces 2 block diagram, ZLR16300 functional 3 C capacitance 8 capture_INT_mask 30, 35 characteristics AC 13 DC 8 clock 49 comparator inputs/outputs 21 configuration port 0 16 port 2 17 port 3 18 port 3 counter/timer 20 counter/timer PS024006-0605 16-bit circuits 42 8-bit circuits 38 brown-out voltage/standby 59 clock 49 demodulation mode count capture flowchart 40 demodulation mode flowchart 41 EPROM selectable options 59 glitch filter circuitry 36 halt instruction 50 input circuit 36 interrupt block diagram 47 interrupt types, sources and vectors 48 oscillator configuration 49 output circuit 45 ping-pong mode 44 port configuration register 51 resets and WDT 58 SCLK circuit 53 stop instruction 50 stop mode recovery register 52 stop mode recovery register 2 56 stop mode recovery source 54 T16 demodulation mode 43 T16 transmit mode 42 T16_OUT in modulo-N mode 43 T16_OUT in single-pass mode 43 T8 demodulation mode 39 T8 transmit mode 36 T8_OUT in modulo-N mode 39 T8_OUT in single-pass mode 39 transmit mode flowchart 37 voltage detection and flags 60 watch-dog timer mode register 57 watch-dog timer time select 58 counter/timer functional blocks input circuit 36 T8 transmit mode 36 counter_INT_mask 35 crt3 T8/T16 control register Index ZGR163L Product Specification 88 register 35 CTR(D)01h T8 and T16 common functions 31 CTR1 (0D)01 30 CTR3 T8/T16 control CTR3(0D)03h 35 D DC characteristics 8 demodulation mode count capture flowchart 40 flowchart 41 T16 43 T8 39 description functional 21 general 2 pin 5 E EPROM selectable options 59 expanded register file 22 expanded register file architecture 24 expanded register file control registers 65 flag 74 interrupt mask register 73 interrupt priority register 72 interrupt request register 73 port 0 and 1 mode register 71 port 2 configuration register 69 port 3 mode register 70 port configuration register 69 register pointer 74 stack pointer high register 75 stack pointer low register 75 stop-mode recovery register 67 stop-mode recovery register 2 68 T16 control register 63 T8 and T16 common control functions register 62 TC8 control register 61 watch-dog timer register 69 PS024006-0605 F features standby modes 1 functional description counter/timer functional blocks 36 CTR0(0D)00h register 29 CTR1(0D)01h register 31 CTR2(0D)02h register 33 expanded register file 22 expanded register file architecture 24 HI16(0D)09h register 28 HI8(0D)0Bh register 28 L08(0D)0Ah register 28 L0I6(0D)08h register 28 program memory map 22 RAM 21 register description 59 register file 26 register pointer 25 register pointer detail 27 stack 27 TC16H(0D)07h register 28 TC16L(0D)06h register 29 TC8H(0D)05h register 29 TC8L(0D)04h register 29 TC8L(D)04h register 29 G glitch filter circuitry 36 H halt instruction, counter/timer 50 I input circuit 36 interrupt block diagram, counter/timer 47 interrupt types, sources and vectors 48 Index ZGR163L Product Specification 89 L low-voltage detection register 59 M memory, program 21 modulo-N mode T16_OUT 43 T8_OUT 39 O oscillator configuration 49 output circuit, counter/timer 45 P P34_out 30 P35_out 35 P36_out/demodulator input 32 package information 20-pin DIP package diagram 76 20-pin SSOP package diagram 77 28-pin DIP package diagram 79 28-pin SOIC package diagram 78 28-pin SSOP package diagram 80 pin configuration 20-pin DIP/SOIC/SSOP 5 28-pin DIP/SOIC/SSOP 6 pin functions port 0 (P07 - P00) 15 port 0 configuration 16 port 2 (P27 - P20) 16 port 2 (P37 - P30) 17 port 2 configuration 17 port 3 configuration 18 port 3 counter/timer configuration 20 XTAL1 (time-based input 15 XTAL2 (time-based output) 15 ping-pong mode 44 port 0 configuration 16 pin function 15 PS024006-0605 port 2 configuration 17 pin function 16 port 3 configuration 18 counter/timer configuration 20 port 3 pin function 17 port configuration register 51 power connections 3 power supply 5 program memory 21 map 22 R ratings, absolute maximum 6 register 56 CTR0(0D)00h 29 CTR1 (0D) 01 30 CTR1(0D)01h 31 CTR2(0D)02h 33 flag 74 HI16(0D)09h 28 HI8(0D)0Bh 28 interrupt priority 72 interrupt request 73 interruptmask 73 L016(0D)08h 28 L08(0D)0Ah 28 LVD(D)0Ch 59 pointer 74 port 0 and 1 71 port 2 configuration 69 port 3 mode 70 port configuration 51, 69 stack pointer high 75 stack pointer low 75 stop mode recovery 52 stop mode recovery 2 56 stop-mode recovery 67 stop-mode recovery 2 68 T16 control 63 T8 and T16 common control functions 62 TC16H(0D)07h 28 Index ZGR163L Product Specification 90 TC16L(0D)06h 29 TC8 control 61 TC8H(0D)05h 29 TC8L(0D)04h 29 TC8L(D)04h 29 voltage detection 65 watch-dog timer 69 register description counter/timer2 LS-Byte hold 29 counter/timer2 MS-Byte hold 28 counter/timer8 control 29 counter/timer8 High hold 29 counter/timer8 Low hold 29 CTR2 counter/timer 16 control 33 T16_capture_LO 28 T8 and T16 common functions 31 T8_Capture_HI 28 T8_capture_LO 28 register file 26 expanded 22 register pointer 25 detail 27 resets and WDT 58 S SCLK circuit 53 single/modulo-N 30, 34 single-pass mode T16_OUT 43 T8_OUT 39 stack 27 standard test conditions 7 standby modes 1 stop instruction, counter/timer 50 stop mode recovery 2 register 56 source 54 stop mode recovery 2 56 stop mode recovery register 52 PS024006-0605 T T 16 clock 35 T16 enable 34 T16 initial out/falling edge 33 T16 transmit mode 42 T16_capture_HI 28 T8 and T16 common functions 30 t8 clock 30 T8 enable 30 T8 intiial out/rising edge 33 T8 transmit mode 36 T8/T16_logic/edge_detect 33 T8_Capture_HI 28 test conditions, standard 7 test load diagram 7 time_out 35 timeout 30 timers counter/timer2 LS-byte hold 29 counter/timer2 MS-byte hold 28 counter/timer8 high hold 29 counter/timer8 low hold 29 CTR0 counter/timer8 control 29 T16_Capture_HI 28 T16_Capture_LO 28 T8_Capture_HI 28 T8_Capture_LO 28 timing diagram, AC 13 transmit mode flowchart 37 transmit_submode/glitch filter 33 V VCC 5 voltage brown-out/standby 59 detection and flags 60 voltage detection register 65 Index ZGR163L Product Specification 91 W watch-dog timer mode registerwatch-dog timer mode register 57 time select 58 X XTAL1 5 XTAL1 pin function 15 XTAL2 5 XTAL2 pin function 15 PS024006-0605 Index