ATLS60/225-PQFP225 - Atmel Corporation

1-1

ATL60GA-3.6-03/02

ATL60/ATLS60

Gate Array/Embedded Array

Description.....................................................................................................................1-2

ATL60 and ATLS60 Array Organizations: Tables.......................................................1-2

Design............................................................................................................................1-3

Design Systems Supported ....................................................................................1-3

Design Tools..........................................................................................................1-3

Design Flow...........................................................................................................1-3

Pin Definition Requirements .................................................................................1-3

ATL60 Gate Array Design Flow...........................................................................1-4

Design Options ..............................................................................................................1-4

VHDL/Verilog-HDL .............................................................................................1-4

ASIC Design Translation.......................................................................................1-4

Design Entry ..........................................................................................................1-4

FPGA and PLD Conversions.................................................................................1-4

Macro Cores...................................................................................................................1-5

AVR™ (8-bit RISC) Microcontroller (8515)..........................................................1-5

ARM7TDMI™ Embedded Microcontroller Core ..................................................1-5

OakDSPCore™.......................................................................................................1-5

5.0 Volt DC Characteristics: Table................................................................................1-6

3.3 Volt DC Characteristics: Table................................................................................1-7

2.0 Volt DC Characteristics: Table................................................................................1-7

I/O Buffer DC Characteristics: Table............................................................................1-8

I/O Buffers .............................................................................................................1-8

I/O Options ............................................................................................................1-8

AC Characteristics .........................................................................................................1-9

Source of CMOS Power Dissipation...........................................................................1-10

Po w er Ca l cu lat ion..... ...... ...... ...... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ......1-10

ATL60 Power Estimation Worksheet..........................................................................1-10

Power Estimation Worksheet Examples......................................................................1-11

Timing and Derating Factors.......................................................................................1-17

ATL60 5.0 Volt Derating Factors........................................................................1-17

ATL60 3.3 Volt Derating Factors........................................................................1-17

Power/Ground..............................................................................................................1-18

Power/Ground Rules............................................................................................1-18

Fixed Power/Ground Pads ...................................................................................1-18

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

Description

Atmel's ATL60 Series CMOS Gate Arrays and

Embedded Arrays are fabricated using a 0.6µm drawn

gate , trip le le v el me tal p r oce ss. Ext e nsi ve cell libraries

are available and support the major CAD software too ls.

As with all Atmel ASIC families, customer involvement

and satisfaction is integral to all steps of the d esign flow.

A variety of Design for Testability techniques are

supported by the libraries, and a wide range of

packaging options are available. The ATLS60 version

utilizes a fine pitch staggered row of bond pads to

achieve the smallest die size possible for a given p ad

count. The ATLS60 is only available in a limited

number of PQFP packages.

ATL60 Array Organization

ATLS60 Array Organization

Note: 1. Nominal 2 Input NAND Gate with a Fan Out of 2

Device

Number Raw

Gates Routable

Gates Max Pin

Count M ax I/O

Pins Gate(1)

Speed

ATL60/4 4,000 3,000 44 36 200 ps

ATL6 0/15 15,000 10,000 68 60 200 ps

ATL6 0/25 25,000 16,900 84 76 200 ps

ATL6 0/40 38,000 25,400 100 92 200 ps

ATL6 0/60 58,000 34,600 120 112 200 ps

ATL6 0/85 86,000 51,900 144 136 200 ps

ATL60/110 110,000 65,900 160 152 200 ps

ATL60/150 149,000 89,300 184 176 200 ps

ATL60/200 195,000 116,900 208 200 200 ps

ATL60/235 232,000 139,500 226 218 200 ps

ATL60/300 301,000 181,000 256 248 200 ps

ATL60/435 430,000 260,000 304 296 200 ps

ATL60/550 545,000 288,000 340 332 200 ps

ATL60/700 693,000 363,000 380 372 200 ps

ATL60/870 870,000 456,000 424 416 200 ps

ATL60 /1100 1,119,000 590,000 480 472 200 ps

Device

Number Raw

Gates Routable

Gates Max Pin

Count Max I/O

Pins Gate(1)

Speed

ATLS60/80 12,500 8,000 80 72 200 p s

ATLS60/100 20,400 13,000 100 92 200 ps

ATLS60/120 30,200 17,500 120 112 200 ps

ATLS60/144 44,600 26,000 144 136 200 ps

ATLS60/160 55,300 32,500 160 152 200 ps

ATLS60/208 96,500 57,000 208 200 200 ps

ATLS60/225 113,500 67,500 225 217 200 ps

ATLS60/256 148,200 88,000 256 248 200 ps

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ATL60GA-3.6-03/02

Design

Design Systems Supported

Atmel su pports several major software systems with

complete macro cell libraries, as well as utilities for the

netlist verification and accurate delay simulations.

Cad ence™ Verilog -XL™ is Atmel's golden simulato r.

Mentor™ Q uickS im II™ and Synopsys™ VSS™ are sign-

off level simulators.

The following design systems are supported:

De sign Fl ow

Atmel provides four methods for implementing a gate

ar ray de si gn, whi le maintaining the same basic design

flow for each of them. This flow involves both the

Customer and Atmel at all critical review and

acceptance steps, as can be seen from the chart below.

Database Acceptance occurs when Atmel receives and

accepts the complete design database. The Preliminary

Design Review follows Cadence simulation and

verification by Atmel. This includes functional as well

as timing performance evaluation.

Upon completion of this critical step, Atmel p erforms

physical p lace-and-route. Additional simulations are

per form ed , based on th e ph ysic al de sign , inc luding th e

generation of a back annotation report to provide the

customer with the m ost accurate timing information

available. Final Design Review is the last step of the

design flow prior to generation of masks. After this

acceptance step is completed, masks are generated and

released, and prototype parts, in ceramic packages, are

delivered.

Pin Definition Requirements

The corner pads on each die are reserved and

programmable for Power and Ground only. All other

buffe r pi ns are fully programma ble as Input, Output, Bi-

directional, Clock-into- Array, Power or Groun d.

System Tools

Cadence™ Opus™ - Schematic Capture

Veritime™ - Static Timing

Ve rilog - X L™ - Simulator

High Level Design - Floor Planning

Viewlogic ™ViewDRAW™ - Schematic Capture

ViewSIM™ - Simulator

Motive™- Static Timing

Mentor™ Neted™ - Schematic Capture

QuickSIMII™ - Simulator

Autologic™ - Synthesis

Quick Path™ - Static Timing

Synopsys™VSS™ - Simulator

VHDL Simulation™ - Vital Libraries

Design Compiler™ - Synthesis

Test C o mp ile r™ - Scan Insertion

and ATPG

Veribest™ACEPlus™ - Schematic Capture

Veribest™ - Simulator

Model Tech™VHDL Simulation™ - Vital Libraries

Exemplar™Leonardo™ - Synthesis

Sunrise™TestGen™ - Scan Insertion and ATPG

1016A

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

ATL60 Gate Array Design Flow

Design O p tions

VHDL/Verilog-HDL

Atmel can accept Reg ist er Tran s fer Level (RTL ) design s

for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-

HDL™ format. Atmel fully supports Synopsys for VHDL™

simulation as well as synthesis. VHDL or Verilog-HDL

is Atmel's preferred database format for Gate Array/

Embedded Array design.

ASIC Design Translation

Atmel has successfully translated existing designs from

most major ASIC vendors (LSI Logic™, Motorola™,

SMOS™, Oki™, NEC™, Fujitsu™, AMI™ and others) into

the gate arrays. These designs have been optimized for

speed and gate count and modified to add logic or

memory, or replic ated for a pin-for-pi n compatible , drop-

in replacement.

Design Entry

Design entry is performed by the customer using an Atmel

prov ided macro cell libr ary. A complete netlist and vecto r

set must be provided to Atmel. Upon acceptance of this

data set, Atme l continues with the standard design flow.

FPG A and PLD Conversi ons

Atmel has successfully translated existing FPGA/PLD

designs from most major vendors (Xilinx™, Actel™,

Altera™, AMD™ and Atmel) into the gate arrays. There

are fo ur primary reasons to conve rt from an FPGA /PL D

to a gate array. Conversion of high volume devices for a

single or combined design is cost effective. Performance

can often be optimized for speed or low power

consumption. Several FPGA/PLDs can be combined

onto a single chip to minimize cost while reducing on-

board space requirements. Finally, in situations where an

FPGA/PLD was us ed for fast cycle time prototyping, a

gate array may provide a lower cost answer for long-term

volume production.

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ATL60GA-3.6-03/02

Macro Cores

AVR™ (8-bit RISC) Microcontroller (8515)

The AVR RISC Microcontroller is a true 8-bit RISC

Architecture, ideally suited for embedded control

applications. The AVR is offered as a gate level, soft

macro in the ATL60 family.

The AVR supports a powerful set of 120 instructions. The

AVR pre-fetches an instruction during prior instruction

execution, enabling the execution of one instruction per

clock cy cl e.

The Fast Access RISC register file consists of 32 general

purpose working registers. These 32 registers eliminate

the data transfer delay in the traditional program code

intensive accumulator architectures.

The AVR can incorporate up to 8k x 8 program memory

(ROM) and 64k x 8 data memory (SRAM). Also included

are several optional peripherals: UART, 8-bit timer/

counter, 16 bit timer/counter, external and internal

interrupts and programmable watchdog timer.

ARM7TDMI™

Embedded Microcontroller Core

The ARM7TDMI (Advanced RISC Machines) is a

powerful 32-bit processor offere d as an emb edded cor e in

the ATL60 series arrays.

The ARM7TDMI is a member of the Advanced RISC

Machines (ARM) family of general purpose 32-bit

microprocessors, which offer high performance for very

low power consumption.

The ARM architecture is based on Reduced Instruction

Set Computer (RISC) principles, and the instruction set

and related decode mechanism are much simpler than

those of microprogrammed Complex Instruction Set

Computers. This simplicity results in a high instruction

throughput and impressive real-time interrupt response

from a smal l and cost- effe ctive chip.

Pipelining is employed so that all parts of the processing

and memory systems can operate continuously.

Typically, while one instruction is being executed, its

successor is being decoded, and a third instruction is being

fetched from memory.

The ARM memory interface has been designed to allow

the performance potential to be realized without incurring

high costs in the m emory system. Speed cr itical control

signal s are pipelin ed to allow syste m control functi ons to

be implemented in standard low-power logic, and these

control signals facilitate the exploitation o f th e fast local

access modes offered by industry standard dynamic

SRAMs.

The ARM7TDMI core includes several optional

peripheral macros. The options offered are Real Time

Clock, DMA Controller, USART, External Bus Interface,

Interrupt, Timer and Advanced Power Management and

Controller.

OakDSPCore™

Atmel’s embedded OakDSPCore is a 16-bit, general-

purpose low-power, low-voltage and high-speed Digital

Signal Processor (DSP).

OAK is designed for mid-to-high-end telecommunica-

tions and consumer electronics applications, where low-

power a nd portability are m ajor requirements. Among the

applica tions supported are digi tal cellular tele phones, fas t

modems, advanced facsimile machines and hard disk drives.

OAK is available as a DSP core in Atmel’s Gate Array cell

library, to be utilized as an engine for DSP-based Gate

Array/Embe dded Array. It is specified with several levels

of modularity in SRAM, ROM, I/O blocks, allowing

effi ci en t D SP-bas ed G at e Array /Embed d ed A rray deve l-

opment.

OAK is aimed at achieving the best cost-performance

factor for a given (small) silicon area . As a key element

of a system-on-chip, it takes into account such

requirements as program size, data memory size, glue

logic, power management , etc.

The OAK core consists of three main execution units

operating in parallel: the Computation/B it-Manipulation

Unit (CBU), the Data Addressing Arithmetic Unit

(DAAU) and the Program Control Unit (PCU).

The Core also contains ROM and SRAM addressing units,

and Program Control Logic (PCL). All other peripheral

blocks, which are appl icati on specif ic, ar e defined a s par t

of the user-specific logic, implemented around the DSP

core on the same s ilicon die.

OAK has an enhanced set of DSP and general

microprocessor functions to meet the application

requirements. The OAK programming model and

ins tructio n s et are aime d at straight fo rw ard generation of

effi ci en t an d co mp act co d e.

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

Abso lute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions beyond those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

de vic e reli a bility.

Note:

1. Minimum voltage is -0.6V dc which may undershoot to -2.0V

for pulses of less than 20 ns. Maximum output pin voltage is

VDD + 0.75V dc wh i ch may oversh oot to +7. 0V f or pul ses of less

than 20 ns.

5.0 V ol t DC Char acte ristic s

Applicable over recommended operating range fro m Ta = -55°C to +125°C, VDD = 4.5V to 5.5V (unless otherwise noted).

Note: 1. This is the specification for the P01 Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one

output shorted at a time, for a maximum of one second, is allowed.

Operating Tempe rature .................... -55°C to +125°C

Storage Tempe rature . ............. .........-65°C to +150°C

Voltage on Any P in

wit h Respect to Ground.. ...........-0.6V to VDD+0.75V1

Maximum Operating Voltage...............................6.0V

Symbol Parameter Test Condition Min Typ Max Units

IIH Input Leakage High VIN=VDD, VDD=5.5V 10 µA

IIL Input Leakage Low (no pull-up)

Max R pull-up (U31) VIN=VSS, VDD=5.5V

VIN=VSS, VDD=5.5V -10

-40 -5 µA

IOZ Output Leakage (no pull-up) VIN=VDD or VSS, VDD=5.5V -10 10 µA

IOS Output Short Circuit Current

P01(2mA Buffer)(1) VIN=0, VDD=5V, VOUT=VDD

VIN=VDD=5V, VOUT=VSS

14 mA

VIL TTL Input Low Voltage 0.8 V

VIL CMOS Inp ut Low Voltage 0.3 x VDD V

VIH TTL Input High Voltage 2.0 V

VIH CMOS Input Hi gh Voltage 0.7 x VDD V

VTTTL Sw itch ing Threshold

CMOS Switching Threshold VDD=5.0V, 25°C

VDD=5.0V, 25°C 1.4

2.4 V

VOL Output Low Voltage

Output buffer has

12 stages of drive capability

with 2 m A IOL per stage

IOL=as rated

VDD=4.5V 0.2 0.4 V

VOH Output Hi gh Voltage

Output buffer has

12 stages of drive capability

with -2 mA IOH per stage

IOH=a s rat ed

VDD=4.5V 0.7 x VDD 4.2 V

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ATL60GA-3.6-03/02

3.3 Volt DC Character istics

Applicable over recom mended operating range from Ta = -55°C to +125°C, VDD = 2.7V to 3.6V (unless otherwise noted).

2.0 Volt DC Character istics

Applicable over recommended operating range from Ta = 0°C to +70°C, VDD = 1.8 V to 2.2 V (unless otherwise noted).

Note: 1. This is the specification for the P01 Buffer. Output short circuit current for other outputs will scale accordingly. Not more th an one

output shorted at a time, for a maximum of one second, is allowed.

Symbol Parameter Test Condi tion Min Typ Max Units

IIH Input Leakage High VIN=VDD, VDD=3.6V 5 µA

IIL Input Leakage L ow (no pull-up)

Max R pull-up (U31) VIN=VSS, VDD=3.6V

VIN=VSS, VDD=3.6V -5

-25 -3 µA

IOZ Output Leakage (no pull-u p) VIN=VDD or VSS, VDD=3.6V -5 5 µA

IOS Output Sho rt Circuit Current

P01(1mA Buffer)(1) VDD=3.3V, VOUT=VDD

VDD=3.3V, VOUT=VSS

7mA

VIL CMOS Input Low Voltage 0.3 x VDD V

VIH CMOS Input High Voltage 0.7xVDD V

VTCMOS Switching Threshold VDD=3.0V, 25°C 1.5 V

VOL Output L ow V ol tage

Output buffer has

12 stages of dri ve capabilit y

with 1 mA IOL per stage.

IOL=as rated

VDD=2.7V 0.11 0.4 V

VOH Output High Voltage

Output buffer has

12 stages of dri ve capabilit y

with -1 mA IOH per stage.

IOH=as ra ted

VDD=2.7V 0.7xVDD 2.3 V

Symbol Parameter Test Condition Min Typ Max Units

IIH Input Leakage High VIN=VDD, VDD=2. 2 V 5 µA

IIL Input Leakage Low (no pull-up)

Max R pull-up (U31) VIN=VSS, VDD=2.2V

VIN=VSS, VDD=2.2V -5

-15 -2 µA

µA

IOZ Output Leakage (no pull-up) VIN=VDD or VSS, VDD=2.2V -5 5 µA

IOS Output Short Circuit Current

P01(0.5 mA Buffer)(1) VDD=2.0V, VOUT=VDD

VDD=2.0V, VOUT=VSS

3mA

VIL CMO S Input Low Voltage 0.2 x VDD V

VIH CMOS Input High Voltage 0.8xVDD V

VTCMOS Switching Threshold VDD=3. 0 V, 25°C 0.5 x VDD V

VOL Output Low Voltage

Output buffer has

12 stages of drive capability

with 0.5mA IOL per stage.

IOL=as rated

VDD=1.8 V 0.2 x VDD V

VOH Output High Voltage

Output buffer has

12 stages of drive capability

with -0.5mA IOH per stage.

IOH=as rate d

VDD=1.8 V 0.8xVDD V

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

I/O Buffer DC Characteristics

I/O Buffers

• Programmable output drive

(2 to 24 mA IOL, - 2 to -24 mA IOH for 5.0V

1 to 12 mA I OL, -1 to -12 mA IOH for 3.3V)

The ATL 60 series input/output ring contains the I/O

buffer circuitry capable of sourcing and sinking c ur rents

up to 24 mA, and responds to CMOS or TTL logic

levels. I/O locations on this ring can accommodate bi-

direct i o na l an d Tr i- St at e™ cel l s.

Symbol Parameter Test Condition Min Typ Max Units

CIN Capacitance, Input Buffer (die) 5.0V, 3.3V, 2 .0V 2.4 pF

COUT Capacitance, O utp ut Buffer (die) 5.0 V, 3.3V, 2 .0V 5.6 pF

CI/O Capacitance, B i-Dire ctional 5.0 V, 3.3V, 2 .0V 6.6 pF

Schmitt Trigger

V+ TTL Pos itive Threshold

CMOS Positi ve Th resh o ld 25°C, 5.0V

25°C, 5.0V 1.8

3.0 2.0

3.5 V

V- TTL Negative Threshold

CMOS Negative Threshold 25°C, 5.0V

25°C, 5.0V 0.8

1.5 1.0

2.0 V

∆V TTL Hyst eres is

CMOS Hy steres i s 25°C, 5.0V

25°C, 5.0V 0.8

1.0 V

V+ CMOS Positive Threshold 25°C, 3.3V 1.8 2.3 V

V- CMOS Negative Threshold 25°C, 3.3V 1.0 1.3 V

∆V CMOS Hysteresis 25°C, 3.3V 0.5 V

I/O Options

Input, Output, Bi-directional, Tri-State™ Output , Internal C lock Driver and Oscillator

Output Drive Value Programmable from 2 mA to 24 mA in 2 mA increments

CMOS or TTL Operation

Sch mi tt T r igger (B i-di re ctional , I nput)

Inverting and Non-inverting Input Buffers (Bi-directional, Input)

Pull-Up Resistor - 12K Ω to 372K Ω (Low R values may invalidate VIL specification)

Pull-Down Resistor - 4K Ω to 124K Ω (Low R values may invalidate VIH specification)

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ATL60GA-3.6-03/02

AC Characteristics

Delay vs VCC

Delay vs Temper atu re

Delay vs Fano ut

Output Buffer vs Load

3.0 3.3 3.6 4.5

Volts

Prop Delay (ps)

5.0 5.5

0.1

0.2

0.3

0.4

0.5

0.6

3.3 Volts V

5.0 Volts V

2 input NAND

Temp = 25 C

FO =3

Prop Delay (ns)

3.3 Volts V

5.0 Volts V

2 input NAND

FO =3

Temperature ( C)°

Prop Delay (ps)

-55 25 125

0.1

0.2

0.3

0.4

Prop Delay (ns)

3.3 Volts V

5.0 Volts V

2 input NAND

Temp = 25 C

Fanout

Prop Delay (ns)

24816

0.2

0.4

0.6

0.8

1.2

3.3 Volts V

5.0 Volts V

PO4 - Output Buffer 8 mA

Temp = 25 C

Capacitive Load (pF)

Prop Delay (ns)

10 25 50 100

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

S ource of CM OS Power Diss ipation

There are two primary components in standard CMOS

power consumption.

1) The major portion of the power dissi pation is rel ated

to chargi ng and dischar ging of gate and interconnect

capacitance during switching. It directly varies with

capacitance load, square of supply voltage, and

frequency (P = C x V**2 x F).

2) Quiescent or stand-by power dissipation comes

primarily from two parasitic leakage paths. One is

through the reverse bias P/N junctions inherent in

CMOS and the second is the subthreshold source to

drain current of MOS transistors in the ir off state.

Quiescent Power = 0.025µ

µµ

µ W/Gate (typical)

Atmel provides a methodology for calculating both

components separately. The power factors given in the

following calculations are a ccurate to w ithin 25 percent.

Po wer Calculatio n

Switching power can be divided into sequential cell (FF)

power, combinational cell power, and I/O POWER.

Flip flops and latches have internal clock buffering, and

therefo re dissipa te powe r when a cl ock is ac tive, even if

data is not changing. This is shown below as 0% DC (duty

cycle). All other power numbers assume 100% duty cycle,

that is the cell output switches every time the input

switches.

5 Volt Par am e te rs

3 Volt Par am e te rs

Flip Flop Power Equation:

P (uW) @ 5V = [7.0(1-DC) + (15.7 + .45X/2)*DC] N * Fc(MHz)

P (uW) @ 3.3V = [2.5(1-DC) + (5.5 + 0.20X/2)*DC] N * Fc(MHz)

Where; DC = Dut y C yc le = # cycles d at a ch an g es/ # of

clock cy cl es

Fc = FF Clock freque ncy

X = average output load on FF(logic+wire)in

unit loads

N= number of FFs

Peak c urrent at 5 vo lt is 4N mA. It is re comm ended that

an Gate Array/Em bedded Arr ay have at least 1 power and

ground pin for each amp of peak current.

Gate Power Estimation:

P (uW) @ 5V = (.84 + .45X) * G * DC *Fc(MHz)

P (uW) @ 3.3V = (.46 + 0.20X) * G * DC *Fc(MHz)

Where; G = total gates less FFs

DC = duty cycle (typically .05 to .20)

I/O Power:

P (uW) @ 5V = (16 + 12.5 * P) * N * Fd * DC

P (uW) @ 3.3V = (7 + 5.4 * P) * N * Fd * DC

Where;P = average out put load in PF

N = number of outputs

Fd = Output frequency in MHz

DC = Duty Cycle

ATL60 Power Estimation Worksheet

The fol lowing p ages a re Po wer Estim ation Wo rkshee ts

that can be used to estimate total chip power

consumption. Wo rksh eet Examples have be en provide d

and can be used as reference for chip power calculation.

The directions below explain how to use the worksheets.

1. Fo r e a ch c lo c k dom ain, f ill out a Fli p F lop Powe r

Estimation Worksheet and an associated Gate Power

Workstation.

2. Complete the I/O Power Consumption Workshee t.

3. Sum up the results of all sheets for a whole chip power

estimation.

4. Use the estimated power to calculate the transistor

junct ion temperature. Use the junction t emperature in

simulations.

FF Gates I/O Units

Duty Cycle

100% 7.0

15.7 0.84

16-30 uW/MHz

uW/MHz

Pe ak Current (Ip) 2 .5 mA

Load Factor 0.45 0.45 uW/MHz/Unit

Load

I/O Load Factor 12.5 uW /MHz/Pf

FF Gates I/O Units

Duty Cycle

100% 2.5

5.5

16-30 uW/MHz

uW/MHz

Pe ak Current (Ip) 1 .5 mA

Load Factor 0.20 0.20 uW/MHz/Unit

Load

I/O Load Factor 5.4 uW /MHz/Pf

ATL60GA-3.7-10/98

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ATL60GA-3.6-03/02

Power Estimation Worksheet Examples

Assume the following design:

5 volt VDD ,100K used gates wi th 2 c l oc k d omai n s.

Domain A has 60K gates and 1500 Flip Flops running at

50MHz, w ith a d uty cycle of 0.3 and an average output

load of 3U.L. The data frequency is 25 MHz with a duty

cycle of 0.2 and an avera ge gate loading of 3U.L.

Dom ain B has 40 K gate s an d 1K F lip Flop s runnin g at

12MHz with a duty cycle of 0.4 and an average load of

4U. L. The data freque ncy is 6MH z having a duty cyc le

of 0.4 a nd an average gate loading of 4U.L.

There are 90 Output buffers and 10 Bi-directional

buffer s with a frequency of 20 MHz, a duty cycle of 0.4

and an av erag e cap aci t ive lo ad o f 40pf.

Note that with duty cycle we mean the estimated

pe rce nt age tha t a Fl ip Fl op o r logi c gate tr ansitions

relative to its clock or data frequenc y. For example, if a

Flip Flo p transitions at Flip Flo p clock frequ ency (Fc),

the duty cycle would be 1.0 or 100%. A more typical

value would be 0.3. Likew ise for com binatio nal logic.

Data can transition through logic a t Fd, but in practice

you might only see one transition in 5 cycles, le ading to

a duty cycle of 0.2.

Flip Flop Power Estimation Worksheet Example - Domain A

5 Volt VDD

P= [7 (1-D C )+ (1 5.7 +. 4 5X/ 2)* D C ]N* F c

P= [7(1-0.3)+(15.7+.45*3/2)*0.3]1500*50

Power C onsume d by Flip Flops = 73 6mW

Gate Power Estimation Worksheet Example - Domain A

5 Volt VDD

P = ( .84 +.45 X)*G *DC * Fd

P= (.84+. 45*3)*60,000*0.2*25

Power Consumed by Gates = 657mW

*1 typical value of 3 Unit Loads

Description Variables Values

N umb er of F lip Flop N 1500

Flip Flop Clock Frequency Fc50MHz

Duty Cycle (Flip Flop output transitions/clock cycles) DC 0.3

Average Loading, wire and pin capacitance on Flip Flop X 3

Description Variables Values

N umb er of Gates (not i nc luding F lip Flop) G 60K

D ata Frequency (ty pically 1/2Fc)F

d25MHz

Du ty C ycle (% of Fd that data changes, typically 0.1 - 0.4) DC 0.2

Average Loading, w ire and pin capacitance on gate *1 X 3UL

ATL60 Gate Arrays

1-12

ATL60GA-3.6-03/02

Fli p Flo p P ower E stim a tion W o rksh eet Ex am ple - D o main B

5 Volt VDD

P= [7(1-DC)+(15.7+.45X/2)*DC]N*Fc

P= [7(1-0.4)+(15.7+.45*4/2)*0.4]1000*12

Power Consumed by Flip Flops = 130mW

Gate Po we r Estim a tio n W ork sh eet E xa m ple - D omain B

5 Volt VDD

P= (.84+.45X)*G*DC*Fd

P= (.84+.45*4)*40,000*0.4*6

Power Consumed by Gates = 253mW

*1 Typic al Value of 3 Unit Loads

Description Variables Values

Number of Flip Flop N 1000

Flip Flop Clock Frequenc y Fc12MHz

Duty Cycle (Flip Flop output transitions/clock cycles) DC 0.4

Ave ra ge Loading, wire and pin capacitance on Flip Flop X 4

Description Variables Values

Number of Gates ( not including Flip Flop) G 40K

Data Frequenc y (typical ly 1/2Fc)F

d6MHz

Duty Cycle (% of Fd that data changes, typically 0.1 - 0.4) DC 0.4

Ave ra ge Loading, wire and pin capacitance on gate *1 X 4UL

1-13

ATL60GA-3.6-03/02

I/O Power Estimation Work sheet Example

5 Volt VDD

P= (16+12.5P)*N*Fd*DC

P= (16+12.5*40)*90*20*0.4

To ta l Pow er Cons u m ed by I/O = 372mW

Estimated Chip Power

Domain A

Flip Fl o p Pow er 736mW

Gate Power 657mW

Domain B

Flip Fl o p Pow er 130mW

Gate Power 253mW

I/O Power 372mW

___________________________

Total 2.15Watt

Description Variables Values

N umb er of Outputs/Bidis or T ri State Buffers N 90

D ata Frequency Fd20MHz

Duty Cycle (% of Fd that dat a changes, typically 0.2 - 0.5) DC 0.4

Average Capacitive Loading (pf) P 40

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

ATL60 Flip Flop Power Estimation Worksheet

5 Volt VDD

P=[7(1-DC)+(15.7+0.45X/2)*DC]N*Fc

Power Consumed by Flip Flops = _______ mW

3 Volt VDD

P=[2.5(1-DC)+(5.5+0.20X/2)*DC]N*Fc

Power Consumed by Flip Flops = _______ mW

Description Variables Values

Number of Flip Flop N

Flip Flop Clock Frequenc y Fc

Duty Cycle (Flip Flop output transitions/clock cycles) DC

Ave rage loading, wire and p in capacitance on Flip Flop X

1-15

ATL60GA-3.6-03/02

AT L6 0 Com b in ati on al Gate Pow er Est im ation Worksheet

5 Volt VDD

P=(.84+0.45X)*G*DC*Fd

Process Consume by Gates I/O = _______ mW

3 Volt VDD

P=(.46+0.20X)*G*DC*Fd

Power Consumed by Ga tes I/O = _______ mW

*1 typical value of 3 Unit Loads

Description Variables Values

N umb er of G at e (not including Flip Flop) G

D ata Frequency (ty pically 1/2 Fc)F

Duty Cycle (% of Fd t hat data changes, typically 0.1 - 0.4) DC

Average loading, wire and pin capacitance on gate *1 X

ATL60 Gate Arrays

1-16

ATL60GA-3.6-03/02

ATL60 I/O Power Estimation Worksheet

5 Volt VDD

P=(16+12.5*P)*N*Fd*DC

Total Power Consumed by I/O = _______ mW

3 Volt VDD

P=(7+5.4*P)*N*Fd*DC

Total Power Consumed by I/O = _______ mW

Description Variables Values

Number of Outputs/Bidis and Tri State Buffers N

Data F requency Fd

Duty Cycle (% of Fd that data changes, typically 0.2 - 0.5) DC

Ave rage Capacitive Loading (pf ) P

1-17

ATL60GA-3.6-03/02

Timing and Derating Factors

Cell tim ing is g enera ted from co mprehen sive transist or

lev el circ uit s imu latio n o ver va riat ions in te mpe ratu re,

voltage, loading and process va riations. The Cell Library

section includes pin-to-pin timing.

Delays are represented as mx+b form, where b is the

intrinsic delay through the cell (ze ro loa d), x is the out-

put load and m is the load factor. All delays are

expresse d in nanoseconds. Lo ad factors are i n nanosec-

onds per picofara d for output buff ers and in nanoseco nds

per u nit lo ad for all inte rnal c ells. A un it loa d is o ne N

channel and one P chan ne l tr an sistor gate. The Cell

Library section contains m and b numbers for each input

to output path, for output rising and output falling, under

nominal conditions.

For sequential logic, set up and hold times used, are the

worst case values for a military environment. In set up

measurements, timing is measured from the rising or

falling edge of the data pin (50% of VDD) to th e ri si ng

edge of the clock (50% of VDD). Hold measurements are

taken from the rising edge of the clock to the rising or

falling edge of the data pin. If set up or hold times are

negative, the value is set to zero.

Simulation libraries contain individual derating for each

cell, providing the most accurate delay numbers

possible. The tables below show the total derating

factors for military, industrial and commercial

environments.

AT L6 0 5.0 V olt Dera tin g Fa ctor s

Pro cess Derat ing Fa cto rs

Combined Derating Factors - Voltage, Temperature, and Process

AT L6 0 3.3 V olt Dera tin g Fa ctor s

Pro cess Derat ing Fa cto rs

Combined Derating Factors - Voltage, Temperature, and Process

Best Case Worst Case

0.748 1.265

Conditions Best Case Worst Case

Military (4.5 Volts to 5.5 Volts)

(-55°C to 125°C) 0.550 1.600

Industrial 0.60 1.45

Commercial 0.67 1.40

Best Case Worst Case

0.748 1.265

Conditions Best Case Worst Case

Military (2.7 Volts to 3.9Volts)

(-55°C to 125°C) 0.55 1.75

Industrial 0.61 1.53

Commercial 0.67 1.49

ATL60 Gate Arrays

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ATL60GA-3.6-03/02

Power/Ground

Simultaneous switching of outputs can result in large

transient currents. Since the board, package, and chip

ground wiring has a finite impedance, this current

produces a transient increase in the l ocal ground voltage,

known as gro und bo un ce. If a buffe r site conta ining an

input buffer experiences sufficient ground bounce, the

input data may be erroneously detected by the buffer.

Ground bounce may also adversely affect the speed

performance of both input and output buffers.

Several steps can be taken to help alleviate ground

bounce problems. Use only minimum drive buffers

nec essary to ac hieve requir ed o utput switc hing speed s.

Atmel allows output drive on a single pin to be

prog rammed in 2 mA increments from 2-24 mA. Adding

extra power and ground pins will lessen ground bounce.

Power and ground distribution is provided by dedi cated

pins in each corner of the die, plus additional power and

grou nd pins tha t can be placed at any pad locati on on any

side. The dedicated corner pins supply power and

grou nd to both the I/O ring and the inte rnal array. Corne r

pin s ca n be eit he r p o w er o r gr ound. For c us tom package

designs, these pins connect to low inductance and low

resistance power and ground paths to the external

package pins.

As a maximum, one power and one ground pin together

can handle up to 80 mA o f simultaneous switching

output current. For example, ten 8 mA buffers would

require a minimum of one power and one ground pin.

Power and ground pins can supply both input and output

buffers, or separate input and output buffers c an be

specified. Generally, simultaneously switching inputs

and output s should be grouped sepa rately wit h addit ional

supply pins between the groups.

Choice of input buffers also impacts the number of

power and ground pins required. A TTL buffer with a

switching point of 0.8 to 2.0V is more susceptible to

ground bounce noise th an a CM OS buffer. Unless other

requirement s dictate TTL level inputs, a C MOS buffer

swit ching at 2.5V will offer more noise imm unity. For

excessively noisy environments, a Schmitt Trigger input

is avail ab l e.

Rigorous solution of the ground bounce problem requires

simulation of the board, package and chip together, with

accurate models of the inductance, resistance and capaci-

tance o f the powe r distributio n and b uffer l oads. Atmel

will prov ide t ran si stor leve l s imul ati on re su lts f or spe ci fic

ap plicati ons as r e quired.

Power/Ground Rules Fixed Power/Ground Pads

80 mA of simultaneous switching current between

power or ground pins is the maximum allowed

Group i nputs together an d out puts t ogethe r, wi t h

supp ly pins bet w een groups

Group bi -direc tional buffers w ith a comm on

Tri-State™ con t rol

The corner pins (8) of all die are fixed as power or

ground.

All other pins are fully programmable