5962-9078502MLA - ANALOG DEVICES

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

Update drawing to current requirements. Editorial changes throughout. - drw 04-12-15 Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS REV A A A A A A A A A A A A

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12

PMIC N/A PREPARED BY

Dan Wonnell

DEFENSE SUPPLY CENTER COLUMBUS

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Raymond Monnin

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

APPROVED BY

Raymond Monnin

MICROCIRCUIT, DIGITAL-LINEAR, DUAL, 12-BIT

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

99-05-27

D/A CONVERTERS, MONOLITHIC SILICON

AMSC N/A

REVISION LEVEL

A SIZE

A CAGE CODE

67268

5962-90785

SHEET

1 OF

DSCC FORM 2233

APR 97 5962-E052-05

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1. SCOPE

1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)

and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or

Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

1.2 PIN. The PIN is as shown in the following example:

5962 - 90785 01 M L A

Federal

stock class

designator

RHA

designator

(see 1.2.1)

Device

type

(see 1.2.2)

Device

class

designator

Case

outline

(see 1.2.4)

Lead

finish

(see 1.2.5)

\ / (see 1.2.3)

Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF- 38535 specified RHA levels and are

marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A

specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

1.2.2 Device types. The device types identify the circuit function as follows:

Device type Generic number Circuit function

01 AD7247A Dual, CMOS, 12-bit D/A converters

02 AD7237A Dual, CMOS, 12-bit D/A converters

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as

follows:

Device class Device requirements documentation

M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-

JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A

Q or V Certification and qualification to MIL-PRF-38535

1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

L GDIP3-T 24 or CDIP4-T24 24 Dual-in-line

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,

appendix A for device class M.

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1.3 Absolute maximum ratings.

DD to GND (device type 01) ................................................................... -0.3 V to +17 V dc

DD to AGND, DGND (device type 02) .................................................... -0.3 V to +17 V dc

DD to VSS................................................................................................ -0.3 V to +34 V dc

AGND to DGND (device type 02)............................................................ -0.3 V, VDD +0.3V

OUTA, VOUTB to AGND 1/....................................................................... VSS - 0.3 V to VDD + 0.3 V

REF OUT to AGND 1/ ........................................................................... 0 V to VDD

REF IN to AGND ..................................................................................... -0.3 V to VDD + 0.3 V

Digital inputs to DGND............................................................................. -0.3 V to VDD + 0.3 V

Storage temperature range...................................................................... -65°C 10 +150°C

Lead temperature (soldering, 10 sec.)..................................................... +300°C

Power dissipation to +75°C...................................................................... 1000 mW, derate above +75°C by 10 mW/°C

Thermal resistance, junction-to-ambient (θJA).......................................... 120°C/W

Thermal resistance, junction-to-case (θJC)............................................... 35°C/W

1.4 Recommended operating conditions.

Ambient operating temperature range (TA).............................................. -55°C to +125°C

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or

from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

________

1/ The outputs may be shorted to voltages in this range provided the power dissipation of the pack age is not exceeded.

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3. REQUIREMENT S

3.1 Item requirements. T he individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth tables. The truth tables shall be as specified on figure 2.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

ambient operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. T he electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for

device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 56 (see MIL-PRF-38535, appendix A).

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TABLE I. Electrical performance characteristics.

Test

Symbol

Conditions 1/

-55°C ≤ TA ≤+125°C

unless otherwise specified

Group A

subgroups

Device

type

Limits Unit

Min Max

Resolution RES 1, 2, 3 All 12 Bits

Relative accuracy RA 2/ 1, 2, 3 All -0.5 +0.5 LSB

Differential non-linearity DNL Must be monotonic 2/ 1, 2, 3 All -0.9 +0.9 LSB

Unipolar offset error UNI DAC latch contents all 0’s 3/ 1, 2, 3 All -4.0 +4.0 LSB

Bipolar zero error BZE

VDD = 11.4 V, VSS = -11.4 V

and range = ±5 V

VSS = -15 V DAC latch

contents 1000 0000 0000

1, 2, 3 All -6.0 +6.0 LSB

Full scale error AE 4/ 1, 2, 3 All -6.0 +6.0 LSB

Reference output REFOUT 5/ 1, 2, 3 All 4.95 5.05 V

Reference temperature

coefficient REF TC 6/ 1, 2, 3 All -25 +25 PPM/°C

Reference load change ∆REF ∆REF OUT vs ∆I reference

load current change

(0 - 100 mA) 1, 2, 3 All -1.0 mV

Reference input range REF IN 7/ 1, 2, 3 All 4.75 5.25 V

Reference input current IIN REF IN = 5.0 V 1, 2, 3 All -5.0 +5.0 µA

Digital input current IINH V

IN = VDD 1, 2, 3 All -10 + 10 µA

(control inputs) IINL V

IN = 0 -150

Digital input current

(data inputs) IIN V

IN = 0 V to VDD 1, 2, 3 All -10 +10 µA

Digital input high voltage VINH 1, 2, 3 All 2.4 V

Digital input low voltage VINL 1, 2, 3 All 0.8 V

Input capacitance CIN see 4.4.1c 4 All 8 pF

Output range resistors RR 1, 2, 3 All 15 30 kΩ

Output voltage ranges VOUT V

SS = 0 V (pin strappable) 1, 2, 3 All +5 V

+10

SS = -15 V (pin strappable) -5 +5

Power supply current IDD Outputs unloaded 1, 2, 3 All 15 mA

ISS Outputs unloaded

(dual supplies) +5

Functional tests FT see 4.4.1d 7, 8 All

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - continued.

Test

Symbol

Conditions 1/

-55°C ≤ TA ≤+125°C

unless otherwise specified

Group A

subgroups

Device

type

Limits Unit

Min Max

CS to WR setup time t1 see figure 3 8 / 9, 10, 11 All 0 ns

CS to WR hold time t2 see figure 3 9, 10, 11 All 0 ns

WR pulse width t3 see figure 3 9, 10, 11 All 100 ns

Data valid to write setup

time t4 see figure 3 9, 10, 11 All 80 ns

Data valid to write setup

time t5 see figure 3 9, 10, 11 All 10 ns

Address to WR setup time t6 see figure 3 9, 10, 11 02 0 ns

Address to WR hold time t7 see figure 3 9, 10, 11 02 0 ns

LDAC pulse width t8 see figure 3 9, 10, 11 02 100 ns

1/ VDD = +12 V ±5% or +15 V ±15%, VSS = 0 V or -12 V ±5% or -15 V ±5%, GND = 0 V, RL = 2 kΩ, CL = 100 pF. Parts are

guaranteed over this supply range. Individual tests are performed using known worst case supply conditions.

2/ VDD = +11.4 V, VSS = -11.4 V and Range = ±5 V; VDD = +14.25 V, VSS = -14.25 V and range = +10 V; VDD = +11.4 V,

SS = 0 V and range = +5 V.

3/ VDD = +14.25 V, VSS = -14.25 V and Range = ±10 V; VDD = +15.75 V, VSS = 0 V and range = +10 V; VDD = +11.4 V,

SS = 0 V and range = +5 V; VDD = + 11.4 V, VSS = -11.4 V and Range = ±5 V

4/ Measured with respect to REF IN and includes unipolar/ bipolar of fset error. VDD = +11. 4 V, VSS = -11.4 V and

Range =

±5 V; VDD = +14.25 V, VSS = -14.25 V and range = +10 V; VDD = +15. 75 V, VSS = 0 V and range = +10 V;

DD = +11.4 V, VSS = 0 V and range = +5 V.

5/ Reference output voltage shall not change more than 0.39% f rom its original value, over the operating life of the device.

6/ If not tested, shall be guaranteed t o the limits specified in table I.

7/ This is a recommended input range. Testing is done with nominal value of 5.0 V.

8/ All input signals are specified with tR = tF = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

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Device type 01 02

Case outline L

Terminal

number Terminal symbol

1 REF OUT REF INA

2 ROFSB REF OUT

3 VOUTB REF INB

4 DB11 ROFSB

5 DB10 VOUTB

6 GND AGND

7 DB9 DB7

8 DB8 DB6

9 DB7 DB5

10 DB6 DB4

11 DB5 DB3

12 DB4 GND

13 DB3 DB2

14 DB2 DB1

15 DB1 DB0

16 DB0 A0

17 CSB A1

18 CSA CS

19 WR WR

20 VDD LDAC

21 VOUTA V

22 VSS V

OUTA

23 ROFSA V

24 REF IN ROFSA

FIGURE 1. Terminal connections.

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Device type 01

CSA CSB WR Function

X X 1 No data transfer

1 1 X No data transfer

0 1 0 DAC A latch transparent

1 0 0 DAC B latch transparent

0 0 0 Both DAC latches transparent

X = Don’t care

Device type 02

CS WR A1 A0

LDAC Function

1 X X X 1 No data transfer

X 1 X X 1 No data transfer

0 0 0 0 1 DAC A LS input latch transparent

0 0 0 1 1 DAC A MS input latch transparent

0 0 1 0 1 DAC B LS input latch transparent

0 0 1 1 1 DAC B MS input latch transparent

1 1 X X 0

DAC A and DAC B latches updated

simultaneously from the respective

input latches

X = Don’t care

FIGURE 2. Tr uth tables.

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Device type 01

Device type 02

FIGURE 3. Timing waveforms.

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4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

a. Burn-in test, method 1015 of MIL-STD-883.

(1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision

level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015.

(2) TA = +125°C, minimum.

b. Interim and final electrical test paramet ers shall be as specified in table II herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under

document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015 of MIL-STD-883.

b. Interim and final electrical test paramet ers shall be as specified in table II herein.

c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in

MIL-PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection . Technology conformance inspection for classes Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed

for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspect i ons

(see 4.4.1 through 4.4.4).

4.4.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.

c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which

may affect input capacitance.

d. For device class M, subgroups 7 and 8 tests shall be sufficient t o verify the truth table. For device classes Q and V,

subgroups 7 and 8 shall include verifying the functionality of the device.

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TABLE II. Electrical test requirements.

Test requirements

Subgroups

(in accordance with

MIL-STD-883,

method 5005, table I)

Subgroups

(in accordance with

MIL-PRF-38535, table III)

Device

class M Device

class Q Device

class V

Interim electrical

parameters (see 4.2) 1 1 1

Final electrical

parameters (see 4.2) 1, 2, 3, 1/

9, 10, 11 1, 2, 3, 1/

9, 10, 11

Group A test

requirements (see 4.4) 1, 2, 3, 4, 7,

8, 9, 10, 11 1, 2, 3, 4, 7,

8, 9, 10, 11

Group C end-point electrical

parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3

Group D end-point electrical

parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3

Group E end-point electrical

parameters (see 4.4) - - - - - - - - - - - -

1/ PDA applies to subgroup 1.

4.4. 2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.

4.4. 2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-ST D-883:

a. Test condition A, B, C or D . The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of

MIL-STD-883.

b. TA = +125°C, minimum.

c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.4. 2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and t est temperature,

or approved alternatives shall be as specified in the device manuf acturer's QM plan in accordance with MIL-PRF-38535. The

test circuit shall be maintained under document revision level c ontrol by the device manufacturer's TRB in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or prepar ing activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specif ied in method 1005 of MIL-ST D-

883.

4.4. 3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.

4.4. 4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured

(see 3.5 herein).

a. End-point electrical parameters shall be as specified in table II herein.

b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as

specified in MIL-PRF-38535 for the RHA level being t ested. For device class M, the devices shall be subjected to

radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device

classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,

after exposure, to the subgroups specified in t able II herein.

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5. PACKAGING

5.1 Packaging requirement s. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes

Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOT ES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor

prepared specification or drawing.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed changes to existing SMD' s will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system

application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users

and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic

devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.

6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone

(614) 692-0547.

6.5 Abbreviat ions, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in

MIL-PRF-38535 and MIL-HDBK-1331.

6.6 Sources of supply.

6.6. 1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.

The vendors listed in QML-38535 have submitted a cert ificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to

this drawing.

6.6. 2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.

The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been

submitted to and accepted by DSCC-VA.

STANDARD MICROCIRCUIT DRAWING BULLETI N

DATE: 04-12-15

Approved sources of supply for SMD 5962-90785 are listed below for immediate acquisition information only and shall

be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised

to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate

of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next

dated revision of MIL-HDBK-103 and QML-38535. DSCC mainta ins an online database of all current sources of

supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-9078501MLA 24355 AD7247ATQ/883B

5962-9078502MLA 24355 AD7247ATQ/883B

1/ The lead finish shown for each PIN representing

a hermetic package is the most readily available

from the manufacturer listed for that part. If the

desired lead finish is not listed contact the vendor

to determine its availability.

2/ Caution. Do not use this number for item

acquisition. Items acquired to this number may not

satisfy the performance requirements of this drawing.

Vendor CAGE Vendor name

number and address

24355 Analog Devices

Rt 1 Industrial Park

PO Box 9106

Norwood, MA 02062

Point of contact:

Raheen Business Park

Limerick, Ireland

The information contained herein is disseminat ed for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.