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Features
•Supports Various Atmel Devices: 16V8, 20V8, 22V10, 750, 750B, F1500A, 2500B,
F1508AS, F750C, F1504AS
•Full CUPL Hardware Description Language Using “C”-like Syntax
•Design Entry Includes: Boolean Equations, State Machines, and Truth Tables
•Macros Allow Library Development, and Macro Reusability
•Five-level Logic Minimization Algorithm
•Functional Unit Delay Behavioral Simulator
•Menu Driven Operation
Description
Atmel-W inCUPL is an entr y leve l PLD des ign syst em. It offe rs full de sign en try, sim u-
lation, and JEDEC file generation of Atmel PLDs. Atmel-WinCUPL offers the basic
features of Logical Devices ’ WinCUPL PLD d esign enviro nment. It is well suited for
small PLD design and verification. The package is specifically designed to support
development with Atmel Programmable Logic Devices. Atmel-WinCUPL suppor ts:
16V8, 20V 8, 22 V1 0, 75 0, 7 50B , 75 0C, 1 500, 250 0B, 1508, 1504 d ev ic es. S uppo rt for
other manufacturer’s PLDs can be added directly from Logical Devices.
Atme l-WinC UPL suppo rts mult iple de sign ent ry meth ods. St ate mac hine, trut h tables
and high level B oolean e quation c an be u sed. Atmel -WinCUPL also acc epts inp uts
from schematic entry tools and other HDLs.
Multiple logic minimization algorithm are available. Different algorithms will provide dif-
ferent results for each design. Therefore, a user benefits from the availability of
multiple algorithms.
A unit de lay simul ator allows qui ck de sig n ve rific ation . Si mulat ion is the sim ples t way
of checking a design’s functionality. An integrated simulator allows quick design
iteration.
Once a design is completed, Atmel-WinCUPL generates standard JEDEC files.
Device programming is done with these files.
System Requirements
•486/Pentium-based PC
•8 MB Memory
•10 MB Hard Disk Space
•Windows NT/95/98
Atmel-WinCUPL
Design Tool
for Atmel
Programmable
Logic Devices
ATDS1000PC
Rev. 0434D–08/99
ATDS1000PC