© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 5
1Publication Order Number:
NB4N121K/D
NB4N121K
3.3V Differential In 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
•Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
•340 ps Typical Rise and Fall Times
•800 ps Typical Propagation Delay
•Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
•<1 ps RMS Additive Clock jitter
•Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
•Differential HCSL Output Level (700 mV Peak−to−Peak)
•Pb−Free Packages are Available
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
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NB4N
121K
AWLYYWWG
1
52
Figure 1. Pin Configuration (Top View)
Q0
Q0
Q1
Q1
Q19
Q19
Q20
Q20
CLK
CLK
VCC
GND RREF IREF
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
VTCLK
VTCLK
152
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Figure 2. Pinout Configuration (Top View)
VCC
Q0
Q1
Q1
Q2
Q2
Q3
Q4
Q4
IREF VCC
Q6
Q3
Q5
Q5
GND
Q20
Q8
Q9
Q11
Q11
Q17
Q14
Q13
Q14
Q13
Q16
1
2
3
4
5
6
7
8
9
10
11
12
13
VTCLK
CLK
CLK
VTCLK
VCC
Q20
Q19
Q19
Q18
Q18
14
15
16
17
18
19
20
21
22
23
24
25
26
Q17
Q16
Q15
Q15
Q12
Q12
VCC
39
38
37
36
35
34
33
32
31
30
29
28
27
Q10
Q10
Q9
Q8
Q7
Q7
Q6
52
51
50
49
48
47
46
45
44
43
42
41
40
Q0
Exposed Pad (EP)
NB4N121K
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 IREF Output Output current programming pin to select load drive. For 1X
configuration, connect IREF to GND, or for 2X configuration, connect
IREF to VCC (See Figure 9).
2 GND −Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
3, 6 VTCLK,
VTCLK
−Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to self−oscillation.
4 CLK LVPECL Input CLOCK Input (TRUE)
5 CLK LVPECL Input CLOCK Input (INVERT)
7, 26, 39, 52 VCC −Positive Supply pins. VCC pins must be externally connected to a power
supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
Q[20−0] HCSL Output Output (INVERT)
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Q[20−0] HCSL Output Output (TRUE)
Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heat−sinking conduit for
proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
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Table 2. ATTRIBUTES
Characteristic Value
Input Default State Resistors None
ESD Protection Human Body Model
Machine Model
>2 kV
400 V
Moisture Sensitivity (Note 2) QFN−52 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 622
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS (Note 3)
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC Positive Power Supply GND = 0 V 4.6 V
VIPositive Input GND = 0 V GND − 0.3 v VI v VCC V
VINPP Differential Input Voltage |CLK − CLKb| VCC V
IOUT Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range QFN−52 −40 to +70 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm
500 lfpm
QFN−52
QFN−52
25
19.6
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 4) QFN−52 21 °C/W
Tsol Wave Solder Pb−Free 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +70°C Note 5)
Symbol Characteristic Min Typ Max Unit
IGND GND Supply Current (All Outputs Loaded) 70 98 120 mA
ICC Power Supply Current (All Outputs Loaded) 1X
2X
420
780
mA
IIH Input HIGH Current CLKx, CLKx 2.0 150 mA
IIL Input LOW Current CLKx, CLKx −150 −2.0 mA
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 5 and 7)
Vth Input Threshold Reference Voltage Range (Note 6) 1050 VCC − 150 mV
VIH Single−Ended Input HIGH Voltage Vth + 150 VCC mV
VIL Single−Ended Input LOW Voltage GND Vth − 150 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8)
VIHD Differential Input HIGH Voltage 1200 VCC mV
VILD Differential Input LOW Voltage GND VCC − 75 mV
VID Differential Input Voltage (VIHD − VILD) 75 2400 mV
VCMR Input Common Mode Range 1163 VCC − 75
HCSL OUTPUTS (Figure 4)
VOH Output HIGH Voltage 600 740 900 mV
VOL Output LOW Voltage −150 0 150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with VCC. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded
25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC.
6. Vth is applied to the complementary input when operating in single ended mode.
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Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; −40°C to +70°C (Note 7)
Symbol Characteristic Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPmin) fin = 133 MHz
fin = 166 MHz
fin = 200 MHz
725
725
725
900
900
900
mV
tPLH,
tPHL
Propagation Delay to (See Figure 3) CLK/CLK to Qx/Qx 550 800 950 ps
DtPLH,
DtPHL
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8)
(See Figure 3)
100 ps
tSKEW Duty Cycle Skew (Note 9)
Within−Device Skew, 1X Mode Only (Note 10)
Within−Device Skew, 2X Mode (Note 10)
Device−to−Device Skew (Note 10)
20
50
80
150
ps
ps
ps
ps
tJITTER RMS Random Clock Jitter (Note 11) fin =133 MHz
fin = 166 MHz
fin = 200 MHz
1 ps
Vcross Absolute Crossing Magnitude Voltage 250 550 mV
DVcross Variation in Magnitude of Vcross 150 mV
tr, tfAbsolute Magnitude in Output Risetime and Falltime Qx, Qx
(From 175 mV to 525 mV)
175 340 700 ps
Dtr, DtfVariation in Magnitude of Risetime and Falltime (Single−Ended) Qx, Qx
(See Figure 4)
1X
2X
125
150
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded 50 W
to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X
configuration, connect IREF to VCC. Typical gain is 20 dB.
8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+.
10.Skew is measured between outputs under identical transition @ 133 MHz.
11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz
Figure 3. AC Reference Measurement
CLK
CLK
Q
Q
tPLH tPHL
VINPP = VIH(CLK) − VIL(CLK)
= VIH(CLK) − VIL(CLK)
VOUTPP = VOH(Q) − VOL(Q)
= VOH(Q) − VOL(Q)
DtPLH DtPHL
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Figure 4. HCSL Output Parameter Characteristics
525 mV
DVCROSS
VCROSS
175 mV
trtf
CLK
Vth
CLK
Vth
Figure 5. Differential Input Driven
Single−Ended (Vth = VREFAC)
CLK
CLK
Figure 6. Differential Inputs Driven
Differentially
VIHmax
VILmax
VIH
Vth
VIL
VIHmin
VILmin
VCC
Vthmax
Vthmin
GND
Vth
VIHDmax
VILDmax
VIHDmin
VILDmin
VIHDtyp
VILDtyp
VID = VIHD − VILD
VCMR
VCC
VCMmax
VCMmin
GND
Figure 7. Vth Diagram Figure 8. VCMR Diagram
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Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation
CLx for Test Only (Representing Receiver Input Loading); Not Added to Application
CL3D
2 pF
CL4D
2 pF
A. For 1X configuration, connect IREF pin
to GND or for 2X configuration, connect
IREF pin to VCC. To adjust load drive for
1X configuration, use RREF from 0 W to
1 kW, to adjust 2X load, use 20 kW to
50 kW.
B. RL1, RL2: 50 W for 1X Load
25 W for 2X Load
C. RS1, RS2: 0 W for Test and
Evaluation. Select to Minimizing Ringing.
D. CL1, CL2, CL3, CL4: Receiver Input
Simulation Load Capacitance Only
CL1D
2 pF
CL2D
2 pF
Z0 = 50 W
Z0 = 50 W
2X Load Option
1X Load
Receiver 2
Receiver
RS1C
RS2C
HCSL
Driver
RREFA
RL1B
50
RL2B
50
Qx
Qx
50 W*
VTCLK = VTCLK = VCC − 2.0 V
LVPECL
Driver
Z0 = 50 W
Z0 = 50 W
VCC = 3.3 V VCC = 3.3 V
GND GND
50 W*
VTCLK
VTCLK
D
D
Figure 10. LVPECL Interface
*RTIN, Internal Input Termination Resistor
50 W*
VTCLK = VTCLK
LVDS
Driver
Z0 = 50 W
Z0 = 50 W
VCC = 3.3 V VCC = 3.3 V
GND GND
50 W*
VTCLK
VTCLK
D
D
Figure 11. LVDS Interface
*RTIN, Internal Input Termination Resistor
NB4N121K NB4N121K
NB4N121K
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8
50 W*
VTCLK = VTCLK = VCC
CML
Driver
Z0 = 50 W
Z0 = 50 W
VCC VCC
GND GND
50 W*
VTCLK
VTCLK
D
D
Figure 12. Standard 50 W Load CML Interface
*RTIN, Internal Input Termination Resistor
NB4N121K
VCC 50 W*
VTCLK = OPEN
LVCMOS/
LVTTL
Driver
Z0 = 50 W
VCC VCC
GND GND
50 W*
VTCLK
VTCLK
D
D
*RTIN, Internal Input Termination Resistor
NB4N121K
Figure 13. LVCMOS/LVTTL Interface
D = Vth
Vth
VTCLK = OPEN
VDR
INTQ
VCC
INTQb
Q
Qb
Figure 14. HCSL Output Structure
ORDERING INFORMATION
Device Package Shipping†
NB4N121KMNG QFN−52
(Pb−Free)
260 Units / Tray
NB4N121KMNR2G QFN−52
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
PACKAGE DIMENSIONS
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
QFN52 8x8, 0.5P
CASE 485M−01
ISSUE C
C0.15
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.08
A1 A3
A
D2
L
NOTE 3
C0.15
2X
2X
SEATING PLANE
C0.10
A2
C
E2
52 X
e
1
13
14 26
27
39
4052
b
52 X
A0.10 BC
0.05 C
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A2 0.60 0.80
A3 0.20 REF
b0.18 0.30
D8.00 BSC
D2 6.50 6.80
E8.00 BSC
E2 6.50 6.80
e0.50 BSC
K0.20 ---
REF
K
52 X
L0.30 0.50
PIN ONE
REFERENCE
SOLDERING FOOTPRINT*
DIMENSIONS: MILLIMETERS
8.30
6.75
6.75
0.50
0.62
0.30
52X
52X
PITCH
8.30
PKG
OUTLINE
RECOMMENDED
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NB4N121K/D
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