TOSHIBA TMP87CH74A/M74A CMOS 8-Bit Microcontroller TMP87CH74AF, TMP87CM74AF The 87CH74A/CM74<A are the high speed and high performance 8-bit single chip microcomputers. These MCU contain 8-bit A/D conversion inputs and a VFT (Vacuum Fluorescent Tube) driver on a chip. Part No. ROM RAM Package OTP MCU TMP87CH74AF 16 K x 8-bit 512 x 8-bit ~------7 === ---f------------ P-QFP80-1420-0.80B TMP87PM74F TMP87CM74AF 32 K x 8-bit 1 Kx8-bit Features 8-bit single chip microcomputer TLCS-870 Series P-QFP80-1420-0.80B @ Instruction execution time: 0.5 4s (at 8 MHz), 122 es (at 32.768 kHz) @ 412 basic instructions Multiplication and Division (8 bits x 8 bits , 16 bits + 8 bits) @ Bit manipulations (Set/Clear/Complement/Load/Store/Test/Exclusive OR) @ 16-bit data operations 0 ee oo, 1-byte jump/subroutine-call (Short relative jump/ Vector call) 15 interrupt sources (External: 6, Internal: 9) All sources have independent latches each, TMP87CH74AF and nested interrupt control is available. TMP87CM74AF : . : : TMP87PM74F @ 3 edge-selectable external interrupts with noise reject @ High-speed task switching by register bank changeover #11 Input/Output ports (71 pins) High current output: 16 pins (typ. 20 mA) @ Two 16-bit Timer/Counters @ Timer, Eventcounter, programmable pulse generator output, Pulse width measurement, External trigger timer, Window modes. 000707EBP1 @ For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a sate design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 3-74-1 2000-12-15TOSHIBA TMP87CH74A/M74A @ Two 8-bit Timer/Counters @ Timer, Event counter, Capture (Pulse width/duty measurement), PWM output, Programmable divider output modes @ Time Base Timer (Interrupt frequency: 1 Hz to 16384 kHz) @ Divider output function (frequency: 1kHz to 8 kHz) @ Watchdog Timer Interrupt source/reset output (programmable) @8-bit Serial Interface With 8 bytes transmit/receive data buffer @ Internal/external serial clock, and 4/8-bit mode @Serial bus Interface @ |2C-bus, 8-bit SIO modes @8-bit successive approximate type A/D converter with sample and hold @ 12 analog inputs Conversion time: 23 s at 8 MHz @ Vacuum Fluorescent Tube Driver (automatic display) @ Programmable grid scan @ High breakdown voltage ports (max. 40 V x 37 bits) @ Dual clock operation @ Single/Dual-clock mode (option) @ Five Power saving operating modes @ STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/High-impedance. @ SLOW mode: Low power consumption operation using low-frequency clock (32.768 kHz). @ |IDLE1 mode: CPU stops, and Peripherals operate using high-frequency clock. Release by interrupts. IDLE2 mode: CPU stops, and Peripherals operate using high-and low-frequency clock. Release by interrupts. @ SLEEP mode: CPU stops, and Peripherals operate using low-frequency clock. Release by interrupts. @Wide operating voltage: 2.7 to 5.5 V at 32.768 kHz, 4.5 to 5.5 V at 8 MHz/ 32.768 kHz @Emulation Pod: =BM87CM75F0A 3-74-2 2000-12-15TMP87CH74A/M74A P-QFP80-1420-0.80B Pin Assignments (Top View) TOSHIBA MAT SOAn eee ree errr ern weoHY TMA HK OPC 222222222222 tuytidtddddddddd da AtTHMman - onweHITMN HK ON Addtnuwn Bester r i gta >PRPPaAoooooonaoaaaaoaa (OA) 09d => Led (0OSs vas) (LA) L9d > we Od (01S/ 195) (ZA) Z9d wee Lid (EDL, 7LN1) (EA) 9d 91d (LNI) (vA) 79d wee SGld (ELNIZ LDL) (SA) $9d we vid WWd/Odds731) (9A) 99d = 1d (OAQ) (ZA) 29d mee Zld (dds 291) (@A) O4d wee bid (LLINI) (6A) Ld = Old (QLNI) (OLA) Z4d wee OZd (GINIs dO1S) (LLA) 4d = 1S3al (Z LA) wid ae 1Zd (NILX) (ELA) Sd Zed (LNOLX) (w LA) 94d we 155454 (GLA) d 9s 6 NIX (QLA) 08d s 8 Lnox (ZLA) L@d 8s Z SSA (@ LA) 78d 6S 9 0d (6 LA) 8d 09 5 90d (OZA) ved 19 tv $0d (LZA) S8d 79 vOd (ZZA) 98d 9 z 0d (EZA) 8d 9 O | Z0d (10S) RERRSRRRBSAREYSS RRR etree reoeeeve ANNAANSaHAAMaAae ~<A P>r>ree>eeerSoorsre we eecrcecc rc e2ze2e22 |p 2000-12-15 3-74-3TOSHIBA Block Diagram VDD Power Supply { VSS VFT Power VKK Supply Reset I/O RESET Test Pin TEST Resonator XIN Connectiong (XOUT Pins TMP87CH74A/M74A /O Ports A P77 P87 P97 PDO Y to to to to PD4 P70 P7 System Controller Standby Controller Timing Generator High u Clock Low Generator frequ P80 VFT driver circuit (automatic display) Stack Pointer Data Memory Register banks Interrupt Controller Time Base 16-bit 8-bit Timer/Counters Timer/Counters Timer TC TC2 TC3 TC4 Watchdog Timer Program Counter Program Memory(ROM) Serial Interfaces $lO1 AID Converter P22 VAREF P47 (AIN7) P53 (AIN13) P17 PO? P32 to VASS to to to to to P20 PAO (AINO) P50 (AIN10) P10 POO P30 XQ / vO Nv Ports /O Ports 2000-12-15 3-74-4TOSHIBA TMP87CH74A/M74A Pin Function When used as a VFT driver output, the latch must be cleared to 0. Pin Name Input / Output Function P07 to PO3 vo Two 8-bit programmable weet nee eee eee ee tena eeeeneeeecenee da ceeeeeeeeteeneetaneneeenens input/output ports (tri-state). SlOlenisldatnOuteut P02 SOND cccssaeefronO OutPUD | Each bit ofthese portscanbe |... ve srtsnnsovnithvsveststnntststvetstnteee P01 (S11) 1/0 (Input) individually configured as an input or | $101 serial data Input cececeeeteceueeeeeeesnansesesaasaas[eceeccceseeteeeesaasanenenaes an output under software control. Freer errr reer ener ee ee eee eeeee ae eeeesaaaeaeeeneenae POO (SCK1) 0 (0) When used as a SIO input/output, an | S101 serial clock input/output P17 (INTAITC3) timer/counter input, the latch must be | Bernal interrupt input or ao Ti 1 ceceeteeeccceeetaeetesseeeeeeeeaes set to0. When used as a PPG Timer/Counter 3 input eee P16 (INT2) I/O (Input) output or divider output, the latch External interrupt input 2 cecceeeeeccaeeteeeeeeneseeeeeeaes must be set to 1. vee eeeate tent yeceeceeeertespeeedereegaceecreeenseesieeesireeeeeenrees PisdNTarrey rere ner pat 30 BDO/PWIV' Timer counter 4 input or 8-bit programmable P14 (1C4/PDO/PWM) IO (1/0) divider output or 8-bit PWM output P13 (DVO) I/O (Output) Divider output P12 (TC2/PPG) 0 (/0) Timer counter 2 input or Programmable pulse wetter eee et teeta eene eerie nea eteeeeeeeennea eee generator OUTPUT cc cccccececeseeseenes P11 (INT1) External interrupt input 1 wee eeaeeeeccaeeeeeeeeaeeeeueeeneaee VO (Input) Cen e ne e e cena eens eens ene e eee e enn ee ee P10 (INTO) External interrupt input 0 P22 (XTOUT) 0 (Output) 3-bit input/output port with latch. Resonator connecting pins (32.768 kHz). weet e teense ere eeeete Dera eee eee e een tea sree eeaes When used as input port, or external | For inputting external clock, XTIN is used and P21 (XTIN) interrupt input, STOP mode release] XTOUT is opened. wee eee eee VO (Input) signal input the latch must be set to External interrupt input or $TOP mode TOUTE CFA A pt input 5 or STOP mode P20 (INTS/STOP) 1". release signal input __ 3-bit programmable input/output . . P32 (SCKO) VO (1/0) ports (Sink open drain). $100 serial clock input/output weet eerie deere ne nee ne eenn nena eee Each bit of these ports can be Poe eee individually configured as aninputor | |2cb ial data input/output or $100 serial P31 (SDA/SOO0) 70 (/O/Outpud) | an output under software control. ate cutoxt mpuwounpa eececacaceecaeaeececeeeeeececenesee feseeeecenseseesaeneeeeeeees When used asa I2C input/output, the |o9 ooo eee latch must be set to 1. : : . l2 | clock t/output or $100 I P30 (SCL/SIO) V0 (VO/Input) Cbus serial clock input/output or seria data Input 8-bit programmable input/output ports (tri-state). P47 (AIN7) Each bit of these ports can be VO (Input) individually configured as an inputor | A/D converter analog inputs to P40 (AINO) an output under software control. When used as a analog input, the PACR must be set to 0. 4-bit programmable input/output ports (tri-state). P53 (AIN13) Each bit of these ports can be 0 (Input) individually configured as an input or | A/D converter analog inputs to P50 (AIN10) an output under software control. When used as a analog input, the PSCR must be set to 0. P67 (V7) to P60 (V0) Four 8-bit high brackdown voltage Trererereseesenegecennnee eset output ports with the latch. . P77 (V15) to P70 (V8) When used as a VFT driver output, the| VFT driver outputs eee /O (Output) latch must be cleared to 0. P87 (V23) to P80 (V16) P97 (V31) to P90 (V24) 5-bit high breakdown voltage output PD4 (V36) toPDO (V32)} VO(Output) | Ports with the latch. 3-74-5 2000-12-15TOSHIBA TMP87CH74A/M74A Pin Name Input / Output Function XIN, XOUT Input, Output Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. oo Reset signal input or watchdog timer output/address-trap-reset output/system- RESET vO clock-reset outputted. TEST Input Test pin for out-going test. Be tied to low. VDD, V55 +5V, 0V (GND) VKK Power Supply VFT driver power supply VAREF, VASS Analog reference voltage inputs (High, Low) 3-74-6 2000-12-15TOSHIBA TMP87CH74A/M74A Operational Description 1. 1.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer. This section provides a description of the CPU core, the program memory (ROM), the data memory (RAM), and the reset circuit. Memory Address Map The TLCS-870 Series is capable of addressing 64 Kbytes of memory. Figure 1-1 shows the memory address maps of the 87CH74A/M74A. In the TLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped |/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the first 128 bytes of the RAM address space. ser [ DBR ROM 0000, 003F 0040 OOBF a0co 043F oF80 OFFF | : ~~ we 8000 FFOO FFBF FFCO FFDF FFEO FFFF ~ ~ 64 bytes 128 bytes 896 bytes 128 bytes 32512 bytes t 87CM74A 0000, 003F 64 bytes 0040 OORF 128 bytes ooco pum ~ ~~ ~ 384 bytes 023F OF80 128 bytes OFFF 000 | 16128 bytes 32 bytes 87CH74A Register banks (8 registers x 16 banks) Note : ROM; Read Only Memory includes : Program memory RAM; Random Access Memory includes : Data memory Stack General-purpose register banks SFR; Special Function Register includes : DBR; Vector table for vector call instructions (16 vectors) Vector table for interrupts/ reset (16 vectors) HO ports Peripheral control registers Peripheral status registers System control registers interrupt control registers Program Status Word Data Buffer Register includes : S10 data buffer VFT display data buffer Entry area for page call instructions Figure 1-1. Memory Address Maps 3-74-7 2000-12-15TOSHIBA TMP87CH74A/M74A Electrical Characteristics Absolute Maximum Ratings (Vs =O ) Parameter Symbol Pins Ratings Unit Supply Voltage Vop -0.3 to 6.5 Vv Input Voltage VIN -0.3 to Vpp + 0.3 Vv Output Voltage Vout: |P2, P3, P4, P5, XOUT, RESET -0.3 to Vpp + 0.3 V Vout3 | Source open drain ports Vpp 40 to Vpp + 0.3 lout: | P15 to P17, P3, P4, P5 3.2 Output Current (Per 1 pin) lourz _| PO, Pio to Pia. Pe 30 mA lourz | P8, P9, PD -12 louta | P6, P7 -25 Slout: | P15 to P17, P3, Pa, P5 60 Output Current (Total) = loutz | PO, P10 to P14, P2 160 mA Slout3 | P6, P7, P8, P9,PD - 200 Power Dissipation [Topr = 25C] PD Note 2 1200 mW Soldering Temperature (time) Tsld 260 (10s) Storage Temperature Tstg -55to 125 aa Operating Temperature Topr - 30 to 70 C Note 1: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Note 2: Power Dissipation (PD) ; For PD, it is necessary to decrease 14.3 mw/C. Recommended Operating Conditions | (Vs3=0V,Topr= - 30 to 70C) Parameter Symbol Pins Conditions Min Max Unit NORMAL 1, 2 mades fc=8 MHz 45 IDLE1, 2 modes Supply Voltage Vopb fs= SLOW mode 27 5.5 Vv 32.768 kHz | si EEP mode STOP mode 2.0 Output Voltage Vout3_ | Source open drain ports Vop - 38 Vop Vv Vv Except hysteresis input Vpp x 0.70 1H1 p Y p Vpp24.5V DD Input High Voltage Vin2 Hysteresis input Vpp x 0.75 Vpp Vv Vin3 Vpp <4.5V Vpp x 0.90 Vv Except hysteresis input Vpp x 0.30 IL1 p p Vpp24.5V DD Input Low Voltage Vit2 Hysteresis input 0 Vpp x 0.25 Vv Vis Vpp <4.5V Vpp x 0.10 Vpp =4.5V to5.5V 8.0 fe XIN, XOUT 0.4 MHz Clock Frequency Vpp=2.7V to5.5V 4.2 fs XTIN, XTOUT 30.0 34.0 kHz Note 1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note 2: Clock frequency fc: Supply voltage range is specified in NORMAL 1/2 mode and IDLE 1/2 mode. 3-74-129 2000-12-15TOSHIBA TMP87CH74A/M74A How to calculate power consumption. With the TMP87CH74A/M74<A, a pull-down resistor (Rk = 80 kQ typ.) can be built into a VFT driver using mask option. The share of VFT driver loss (VFT driver output loss + pull-down resistor (Rk) loss) in power consumption Pmax is high. When using a fluorescent display tube with a large number of segments, the maximum power consumption Pd must not be exceeded. power consumption Pmax = operating power consumption + normal output portloss + VFT driver loss Where, operating power consumption: VDD x IDD LED output loss > lot3x VoL VFT driver loss : VFT driver output loss + pull-down resistor (Rk) loss Example: When Ta = 10 to 50c (When using a fluorescent display tube with a grid scan type which can use two or more grid outputs.) and a fluorescent display tube with segment output = 3 mA, digit output = 15mA, Vxx = -25 Vis used. Operating conditions: VDD =5 V + 10 %, fc = 8 MHz, VFT dimmer time (DIM) = (14/16) x tseg, Digit outputs = two pin Power consumption Pmax = (1) + (2) + (3) Where, (1) Operating power consumption: Vpp Xlpp = 5.5 Vx 14mA=77 mW (2) LED output > 10mAx 1.0Vx4=40 mW (when using four LED) (3) VFT driver loss : segment pin = 3mAx2V xnumber of segments X = 6mWx X digit pin = 15 mA x 2 V x 14/16 (DIM) x number of digits Y =52.5 mw Rk loss = (5.5 + 25 V)2/50 kQ x (number of segments X + number of digits Y) = 18.605 mW x (X + 2) Therefore, Pmax = 77 mW+40 mW+6 mWxX+52.5 mW+18.605 mWx (X+42)=206.71 mW + 24.605X... Maximum power consumption Pd when Ta = 50C is determined by the following equation: PD = 1200 mW-(14.3 x 25) = 842.5 mW The number of segments X which can be lit is: PD > Pmax 842.5 mW > 206.71 + 24.605 X 25.8 >X Thus, a fluorescent display tube with less than 25 segments can be used. If a fluorescent display tube with 25 segments or more is used, either a pull-down resistor must be attached externally , or the number of segments to be lit must be kept to less than 25 by software. 3-74-130 2000-12-15TOSHIBA TMP87CH74A/M74A D.C. Characteristics (Vss=OV, Topr= 30 to 70C) Parameter Symbol Pins Conditions Min | Typ. | Max | Unit Hysteresis Voltage Vus | Hysteresis input - 0.9 - Vv lint | TEST Open drain ports, linz : Vpp =5.5V - - +2 Tri-state ports DD= - Input Current Vin = 5.5 V/OV uA ling | RESET, STOP lina PD ports (Nate3) - - 80 Input Resistance Rin2 | RESET 100 | 220 | 450 | kQ Pull-down Resistance Rk Source open drain ports Vpp=5.5V, Vx = -30V 50 80 110 | kQ ILo1 Sink open drain ports Vpop=5.5V, VouT= 5.5 V - - 2 Output Leakage Source open drain ports and _ _ Current lLo2 | tri-state ports Vop =5.5V, Vout= -32V - - -2 | vA ILo3 | Tri-state ports Vpp=5.5V, VouT=5.5V/0V - - +2 Von2 | Tri-state ports Von =4.5V, lon = -0.7mA 4.1 - - Output High Voltage P oP on Vv Vou3 | P8, P9, PD Vpp =4.5V, loy= -8mA 24 | - - Output Low Voltage VoL Except XOUT, PO, P10 to P14, P2 Vpp =4.5V, lol = 1.6mA - - 0.4 Vv Output Low Current lot3_| PO, P10 to P14, P2 Vop = 4.5 V, VoL= 1.0V - 20 - | mA Output High Current lon | P6, P7 Vop =4.5V, Von =2.4V - |-20] - | ma Supply Current in Von=5.5V NORMAL 1, 2 modes fee MHz ~ 10) 14 A m Supply Current in fs = 32.768 kHz _ 6 9 IDLE 1, 2 mades Vin = 5.3 W/0.2V Supply Current in SLOW mode lbp Vpp=3.0V - | 30 | 60 S ve ; fs = 32.768 kHz vA upply Current in Vin=2.8V/0.2V _ SLEEP mode IN 15 30 Supply Current in Vpp=5.5V STOP mode Vin=5.3V/0.2V | 05 | 10 | HA Note 1: Typical values show those at Topr=25C, Vpp =5 V. Note 2: input Current ling iz; The current through resistor is not included, when the input resistor (pull-up/pull-down) is contained. Note 3: input Current ling; The current when the pull-down register (Rk) is not connected by the mask aption. A/D Conversion Characteristics (Vsg = OV, Vpp =4.5 to 6.0 V, Topr= 30 to 70C) Parameter Symbol Conditions Min Typ. Max Unit VAREF Vpp 1.5 Vpp Analog Reference Voltage Varer- Vass=2.5V Vv Vass Vss Analog Input Voltage VAIN Vass _ VAREF Vv Analog Supply Current IREF Varer=5.5V, Vass =0.0V 0.5 1.0 mA Nonlinearity Error _ _ +1 Zero Point Error Vpp =5.0V, Vss = 0.0 V +1 Varer= 5.000 V LSB Full Scale Error Vass = 0.000 V = +1 Total Error _ _ +2 Note: Total errors includes all errors, except quantization error. 3-74-131 2000-12-15TOSHIBA TMP87CH74A/M74A A.C. Characteristics (Vss=O0V, Vpp =4.5to5.5V, Topr= 30 to 70C) Parameter Symbol Conditions Min Typ. Max Unit In NORMAL1, 2 modes 0.5 - 10 In IDLE 1, 2 modes Machine Cycle Time tey us In SLOW mode 117.6 - 133.3 In SLEEP mode High Level Clock Pulse Width twcu _| For external clock operation 7 : fe=8MH 50 - - ns Low Level Clock Pulse Width two. | &XINinput), fe = z High Level Clock Pulse Width twsH__| For external clock operation 147 ; Low Level Clock Pulse Width tws. | OX TIN input), fs = 32.768 kHz , x Recommended Oscillating Conditions (Vsg = OV, Vpp=4.5 to 5.5 V, Topr= 30 to 70C) XIN (1) High-frequency Oscillation (2) Low-frequency Oscillation Oscillation Recommended Constant Parameter Oscillator Recommended Oscillator Frequency Cy Co 8 MHz KYOCERA KBR8.0M Ceramic Resonator KYOCERA KBR4.0MS 30pF 30pF 4MHz High-frequency MURATA CSA 4.00MG Oscillation 8 MHz TOYOCOM 210B 8.0000 Crystal Oscillator 20pF 20pF 4MHz TOYOCOM 204B 4.0000 Low-frequency ae Crystal Oscillator 32.768 KHz NDK MX-38T 15pF 15pF Oscillation XTIN XTOUT Note: An electrical shield by metal shield plate on the surface of IC package should be recommendable in order to prevent the device from the high electric fieldstress applied from CRT (Cathode Ray Tube) for continuous reliable operation. 3-74-132 2000-12-15