32K x 8 Static RAM
CY62256V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-050 57 Rev. *B Revised May 16, 2002
Features
• Low voltage range:
—CY62256V (2.7V–3.6V)
—CY62256V25 (2.3V–2.7V)
•Low active power and standby power
•Easy memory expansion with CE and OE features
•TTL-compatibl e inputs and outpu ts
•Automatic power -do wn wh en dese lec t ed
•CMOS for optimum speed/power
Functional Description
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memor y ex pa ns ion is p rov ided by an acti ve LOW chip enable
(CE) and active LOW output enable (OE) and three-state
drivers. These devices have an automatic power-down
feature, reducing the power consumption by over 99% when
desele ct ed. The CY 6225 6V fami ly is avail able i n the st andard
450-mil-wide (300-mil body width) SOIC, TSOP, and reverse
TSOP packages.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the de vic e and enab lin g the ou tputs, CE and OE activ e LO W,
while WE remains inacti ve or HIGH. Un der th ese co nditi ons,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENS E AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
512 × 512
ARRA
Y
I/O7
I/O6
I/O5
I/O4
A10
A
13
A
11
A
12
A
A
14
A
1
0
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
I/O3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
I/O3
TSOP I
Top View
(not to scale)
TSOP I
Top View
(not to scale)
Reverse Pinout
Logic Block Diagram Pin Configurations
CY62256V
Document #: 38-05057 Rev. *B Page 2 of 11
Maximum Ratings
(Abov e wh ic h th e useful life may be impa ired . Fo r us er gui de-
lines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1] .......................................−0.5V to VCC + 0.5V
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Output Current into Outpu ts (LO W)............... ...... ..... ...20 mA
Static Discharge Voltage......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.3V to 3.6V
Industrial −40°C to +85°C 2.3V to 3.6V
Product Portfolio
Product VCC Range (V) Speed Power Dissipat ion
Operating, ICC (mA) Standby, ISB2 (µA)
Min. Typ.[2] Max. (ns) Typ.[2] Max. Typ.[2] Max.
CY62256V 2.7 3.0 3.6 70 11 30 0.1 5
CY62256V25 2.3 2.5 2.7 100 9 15 0.1 4
Electri cal Characteristics Ov er the Operating Rang e
Parameter Description Test Conditions CY62256V-70 UnitMin. Typ.[2] Max.
VOH Output HIGH Voltage IOH = −1.0 mA Vcc=
2.7V 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA Vcc=
2.7V 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.3V V
VIL Input Leakage Voltage −0.5 0.8 V
IIX Input Leaka ge Cu rren t GND < VIN < VCC −1+1 µA
IOZ Output Leakage Current GND < VIN < VCC, Output Disabled −1+1 µA
ICC VCC Operating Supply
Current VCC = 3. 6V, IOUT = 0 mA,
f = fMAX = 1/tRC Com’l11 30 mA
ISB1 Automatic CE Power-down
Current— TTL Inputs VCC = 3 .6V, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX Com’l100 300 µA
ISB2 Automatic CE Power-down
Current— CMOS Input s VCC = 3.6V , CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Com’l0.1 5µA
Ind’l10 µA
Electri cal Characteristics Ov er the Operating Rang e
Parameter Description Test Conditions CY62256V25-100 UnitMin. Typ.[2] Max.
VOH Output HIGH Voltage IOH = −0.1 mA Vcc=
2.3V 2 V
VOL Output LOW Voltage IOL = 0.1 mA Vcc=
2.3V 0.4 V
VIH Input HIGH Voltage 1.7 Vcc +
0.3V V
VIL Input LOW Voltage −0.3 0.7 V
IIX Input Leakage Current GND < VIN < VCC −1+1 µA
IOZ Output Leakage Current GND < VIN < VCC, O utput Di sabled −1+1 µA
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C, and tAA = 70 ns.
CY62256V
Document #: 38-05057 Rev. *B Page 3 of 11
ICC VCC Operating Supply
Current VCC = 2.7V , IOUT = 0 mA,
f = fMAX = 1/tRC Com’l14 23 mA
ISB1 Automatic CE Power-down
Current— TTL Inputs VCC = 2.7V, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX Com’l75 225 µA
ISB2 Automatic CE Power-down
Current
— CMOS Inputs
VCC = 2.7V, CE > VCC − 0.3V
VIN > VCC – 0.3V or VIN < 0.3V, f
= 0
Com’l0.1 4µA
Ind’l 8 µA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.0V 6pF
COUT Output Capacitance 8pF
AC Test Loads and Waveforms
Parameter 3.3V 2.5V Units
R1 1.100 16.60 K Ohms
R2 1.500 15.40 K Ohms
RTH 0.645 8.00 K Ohms
VTH 1.750 1.20 Volts
Data Retention Characteristics (Over the O perating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC fo r Data Rete ntio n 1.4 V
ICCDR Data Retention Current VCC = 1 .6V, CE > VCC – 0.3V,
VIN > V CC – 0.3V or VIN < 0.3V Com’l0.13µA
Ind’l6µA
tCDR[3] Chip Deselect to Data
Retention Time 0ns
tR[3] Operation Recovery Time tRC ns
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
4. No input may exceed VCC + 0.3V.
Electri cal Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions CY62256V25-100 UnitMin. Typ.[2] Max.
VCC
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT Vth
Equivalent to: THÉ VENINEQUIVALENT
ALL INPUT PULSES
R1
Rth
CY62256V
Document #: 38-05057 Rev. *B Page 4 of 11
Data Retention Waveform
1.8V1.8V
tCDR
VDR >1.4V
DATA RETENTION MODE
tR
CE
VCC
Switching Characteristics Over the Operating Range[5]
Parameter Description CY62256V-70 CY62256V25-100 UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 70 100 ns
tAA Address to Data Valid 70 100 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 70 100 ns
tDOE OE LOW to Data Valid 35 75 ns
tLZOE OE LOW to Low-Z[6] 5 5 ns
tHZOE OE HIGH to High-Z[6, 7] 25 50 ns
tLZCE CE LOW to Low-Z[6] 10 10 ns
tHZCE CE HIGH to High-Z[6, 7] 25 50 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 70 100 ns
Write Cycle[8, 9]
tWC Write Cycle Time 70 100 ns
tSCE CE LOW to Write End 60 90 ns
tAW Address Set-up to Write End 60 90 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 50 80 ns
tSD Data Set-up to Write End 30 60 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[6, 7] 25 50 ns
tLZWE WE HIGH to Low-Z[6] 10 10 ns
Notes:
5. Test con di tio ns as sum e sign al tran siti on time of 5 ns or less tim ing r efer enc e le vels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOL/IOH and 100-pF load capa citance .
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is le ss th an t LZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified wi th CL = 5 pF as in ( b) of AC Test Loads. Transition is measured ± 200 m V fro m steady- state volt age.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal s must b e LOW to in itiate a wr ite and either signal can terminate
a write by going HI GH. The data input set -up and hold timing sho uld be reference d to the rising edge of the si gnal that termin ates the writ e.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW ) is t he sum of tHZWE and tSD.
CY62256V
Document #: 38-05057 Rev. *B Page 5 of 11
Switching Waveforms
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
Read Cycle No. 1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
[10, 11]
Read Cycle No. 2
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
[11, 12]
Write Cycle No.1 (WE Controlled)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATAINVALID
[8, 13, 14]
NOTE 15
CY62256V
Document #: 38-05057 Rev. *B Page 6 of 11
Notes:
12. Address valid prior to or coincident with CE transition LOW .
13. Data I/O is high impedance if OE = VIH.
14. If CE goes HI GH simu ltaneo usly w ith W E HIG H, the o utput remains i n a h igh-imped ance sta te.
15. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
Write Cycle No. 2 (CEControlled) tWC
tAW
tSA tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
DATAINVALID
[8, 13, 14]
Write Cycle No. 3 (WEControlled, OELOW)
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
tHZWE
DATAINVALID
[9, 14]
NOTE 15
WE
CE
CY62256V
Document #: 38-05057 Rev. *B Page 7 of 11
Typical DC and AC Characteristics
1.6
1.8
1.0
0.6
0.4
0.2
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED t
AA
-14
-12
-10
-8
-6
-4
0.0 1.0 1.5 22.5
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.8
1.5
1.0
0.5
1.65 2.1 2.6 3.1 3.6
NORMALIZED t
SUPPL Y VOLTAGE (V )
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
6
4
2
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
OUTP UT VO LT AGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I
CC
NORMALIZED I
CC
TA = 25°C
0.6
0.0
0
AA
2.5
2.0
TA= 25°C
1.4
−55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
AMBIEN T TE MPERA TURE (°C)
1.0
0.5
0.0
-0.5
ISB
3.0
STANDBY
I
SB2
µ
A
VCC = 3.0V
VCC = 2.5V
V
cc
= 2.5V
V
cc
= 3.3V
1.6
1.8
2.0
2.4
2.8
3.2
3.6
1.4
1.2
VCC = 3.0V
VCC = 2.5V
0.5
8
10
12
14
TA = 25°C
TA = 25°C
VCC = 2.5V
VCC = 2.5 V
CY62256V
Document #: 38-05057 Rev. *B Page 8 of 11
Typical DC and AC Characteristics (continued)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DEL T A t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30
NORMALIZED I
CC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 1000 0.50
TA = 25°C
VIN = 0.5V
1
VCC = 3.0V
TA = 25°C
VCC = 3V
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High-Z Deselect/Power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High-Z Deselect, Output Disabled Active (ICC)
Order in g In fo rmat io n
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
70 CY62256VLL-70SNC SN28 28-lead (300-mil Narrow Body) SOIC Commercial
CY62256VLL-70ZC Z28 28-lead Thin Small Outline Package Commercial
CY62256VLL-70ZI Industrial
CY62256 VLL -70SNI SN28 28-lead (300-mil Narrow Body) SOIC Industrial
CY62256VLL-70ZRI ZR28 28-lead Reverse Thin Small Outline Package
100 CY62256V25LL-100ZC Z28 28-lead Thin Small Outline Package Commercial
CY62256V
Document #: 38-05057 Rev. *B Page 9 of 11
Package Diagrams
51-85092-*B
28-lead (300-mil) SNC (Narrow Body) SN28
28-lead Thin Small Outline Package Type 1 (8 × 13.4 mm) Z28
51-85071-*G
CY62256V
Document #: 38-05057 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
All product and company names mentioned in this document are the trademarks of their respective holders.
51-85074-*F
28-lead Reverse Type 1 Thin Small Outline Package (8 × 13.4 m m) ZR28
CY62256V
Document #: 38-05057 Rev. *B Page 11 of 11
Document Title: CY62256V 32K x 8 Static RAM
Document Number: 38-05057
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 107248 09/10/01 SZV Change from Spec number: 38-00519 to 38-05057.
*A 111445 11/01/01 MGN Remove obsolete parts. Change to standard format.
*B 115229 05/23/02 GBI Changed SN package diagram.
