VP5225 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex's well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. te Low threshold (-2.4V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Applications Medical Ultrasound imaging Non-destructive evaluation Solid state relays Telecom switches Logic level interfaces - ideal for TTL and CMOS Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. le bs o Ordering Information Device Package Option 3-Lead TO-252 (D-PAK) VP5225 BVDSS/BVDGS RDS(ON) ID(ON) (V) (max) () -250 3.0 -2.5 VP5225K4 Pin Configuration Absolute Maximum Ratings Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage 20V O Parameter Operating and storage temperature Soldering temperature* -55OC to +150OC 300OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. (min) (A) DRAIN SOURCE GATE 3-Lead TO-252 (D-PAK) (K4) Product Marking YYWW VP5225 LLLLLLL YY = Year Sealed WW = Week Sealed L = Lot Number 3-Lead TO-252 (D-PAK) (K4) VP5225 Thermal Characteristics ID Power Dissipation ID jc Package (continuous) (mA) (pulsed) (A) @TA = 25OC (W) ( C/W) 3-LeadTO-252 (D-PAK) 645 3.0 2.5 6.25 O ( C/W) IDR (mA) IDRM 50 645 3.0 O ja (A) Notes: ID (continuous) is limited by max rated Tj of 150OC. Mounted on FR4 board, 25mm x 25mm x 1.57mm Electrical Characteristics (T = 25 C unless otherwise specified) A O Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -250 - - V VGS = 0V, ID = -250A VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA Change in VGS(th) with temperature - - 4.5 IGSS Gate body leakage - - -100 nA VGS = 20V, VDS = 0V - - -10 A IDSS Zero gate voltage drain current VGS = 0V, VDS = Max Rating - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125C ID(ON) On-state drain current -2.5 - - A VGS = -10V, VDS = -25V - - 5.0 - - 3.0 - - 1.7 500 - - RDS(ON) Change in RDS(ON) with temperature bs ol RDS(ON) Static drain-to-source on-state resistance GFS Forward transductance CISS Input capacitance - - 400 COSS Common source output capacitance - - 150 CRSS Reverse transfer capacitance - - 50 td(ON) Turn-on delay time - - 20 Rise time - - 30 Turn-off delay time - - 60 Fall time - - 30 Diode forward voltage drop - - Reverse recovery time - 300 tr td(OFF) tf VSD trr mV/ C VGS = VDS, ID= -1.0mA O et VGS(th) Conditions e Sym %/ C O VGS = -4.5V, ID = -250mA VGS = -10V, ID = -1.0A VGS = -10V, ID = -1.0A mmho VDS = -25V, ID = -200mA pF VGS = 0V, VDS = -25V, f = 1.0MHz ns VDD = -25V, ID = -500mA, RGEN = 25 -1.8 V VGS = 0V, ISD = -500mA - ns VGS = 0V, ISD = -500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulsed test: 300s pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. O Switching Waveforms and Test Circuit 0V PULSE GENERATOR 10% INPUT -10V td(ON) RGEN 90% t(OFF) t(ON) td(OFF) tr D.U.T. tF 0V OUTPUT VDD Output INPUT 90% 10% 90% RL 10% VDD 2 VP5225 3-Lead TO-252 D-PAK Package Outline (K4) E1 A E c2 b3 4 H et e 1 L3 D1 D 1 3 ol Detail B 2 b2 Gauge Plane bs A1 L2 L5 b e Front View Side View L4 Rear View Seating Plane L L1 Detail B O Notes: 1. 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed. Symbol A A1 b b2 b3 c2 D D1 E E1 MIN Dimension NOM (inches) MAX .086 - .025 .030 .195 .018 .235 .205 .250 .170 - - - - - - .240 - - - .094 .005 .035 .045 .215 .035 .245 - .265 - e .090 BSC H L .370 .055 .410 L1 L2 L3 .035 .108 .020 .060 REF BSC .070 .050 L4 L5 1 - .045 0O 0O - - - - .040 .060 10O 15O JEDEC Registration TO-252, Variation AA, Issue E, June 2004. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-VP5225 NR053008 3