1
UT54ACS164245SEI
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver
Datasheet
June 21, 2007
www.aeroflex.com/16BitLogic
FEATURES
• Flexible voltage operation
- 5V bus to 3.3V bus; 5V bus to 5V bus
- 3.3V bus to 5V bus; 3.3V bus to 3.3V bus
• Cold sparing
- 1MΩ minimum input impedance power-off
• Warm sparing
- Guaranteed output tri-state while one power supply is "off"
and the other is "on"
- 1MΩ minimum input impedance power-off
• 0.6μm Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
• High speed, low power consumption
• Schmitt trigger inputs to filter noisy signals
• Available QML Q or V processes
• Standard Microcircuit Drawing 5962-98580
- Device Types 06 and 07
• Package:
- 48-lead flatpack, 25 mi l pi tch (.390 x .640 )
DESCRIPTION
The 16-bit wide UT54ACS164245SEI MultiPurpose transceiv-
er is built using Aeroflex’s Commercial RadHardTM epitaxial
CMOS technology. This high speed, low pow er
UT54ACS164245SEI transceiver is designed to perform mul-
tiple functions including: asynchronous two-way communica-
tion, schmitt input buffering, voltage translation, cold and warm
sparing. With either or both VDD1 and VDD2 are equal to zero
volts, the UT54ACS164245SEI outputs and inputs present a
minimum impedance of 1MΩ making it ideal for "cold spare"
applications. Balanced outputs and low "on" output impedance
make the UT54ACS164245SEI well suited for driving high ca-
pacitance loads and low impedance backplanes. The
UT54ACS164245SEI enables system designers to interface 3.3
volt CMOS compatible components with 5 volt CMOS compo-
nents. For voltage translation, the A port interfaces with the 3.3
volt bus; the B port interfaces with the 5 volt bus. The direction
control (DIRx) controls th e direction of data flow. The output
enable (OEx) overrides the direction control and disables both
ports. These signals can be driven from either port A or B.
The direction and output enable controls operate these devices
as either two independent 8-bit transceivers or one 16-bit trans-
ceiver.
LOGIC SYMBOL
(48)
OE1
G2
(47)
1A1
(46)
1A2 (44)
(2) 1B1
(5)
(3) 1B2
1A3 (43)
1A4 (41)
1A5 (40)
1A6
1B3
(9) 1B6
(8) 1B5
(6) 1B4
(38)
1A7 (37)
1A8 (12) 1B8
(11) 1B7
(1)
DIR1 1EN1 (BA)
1EN2 (AB)
11 12
(25)
OE2G1 (24) DIR2
21 22
(36)
2A1 2B1
(13)
(35)
2A2 (33)
2A3 (32)
2A4 (30)
2A5 (29)
2A6 (27)
2A7 (26)
2A8
(16) 2B2
2B3
(20) 2B6
(19) 2B5
(17) 2B4
(23) 2B8
(22) 2B7
(14)
2EN1 (BA)
2EN2 (AB)
2
PIN DESCRIPTION
FUNCTION TABLE
PINOUTS
Pin Names Description
OExOutput Enable Input (Active Low)
DIRx Direction Control Inputs
xAx Side A Inputs or 3-State Outputs (3.3V Port)
xBx Side B Inputs or 3-State Outputs (5V Port)
ENABLE
OExDIRECTION
DIRx OPERATION
L L B Data To A Bus
L H A Data To B Bus
H X Isolation
1
2
3
4
5
7
6
48
47
46
45
44
42
43
DIR1
1B1
1B2
VSS
1B3
1B4
VDD1
OE1
1A1
1A2
VSS
1A3
VDD2
841
1B5 1A5
1A4
940
1B6 1A6
10 39
VSS VSS
48-Lead Flatpack
Top View
1B7
1B8
2B1
2B2
VSS
2B3
2B4
VDD1
2B5
2B6
11
12
13
14
15
17
16
18
19
20
VSS
2B7
2B8
DIR2
21
22
23
24
38
37
36
35
34
32
33
1A7
1A8
2A1
2A2
VSS
2A4
31 VDD2
2A3
30 2A5
29 2A6
28 VSS
27 2A7
26 2A8
25 OE2
3
IO GUIDELINES
All inputs are 5 volt tolerant. When VDD2 is at 3.3 volts, either
3.3 or 5 volt CMOS logic levels can be applied to all control in-
puts. It is recommended that all unused inputs be tied to VSS
through a 1KΩ resistor. Input signal transitions should be driven
to the UT54ACS164245SEI wit h a rise and fall time that is
<100ms.
POWER TABLE
POWER APPLICATION GUIDELINES
For proper operation, connect power to all VDD pins and ground
all VSS pins (i.e., no floating VDD or VSS input pins). By virtue
of the UT54ACS164245SEI warm spare feature, power supplies
VDD1 and VDD2 may be appli ed to the device in any order. To
ensure the device is in cold spare mode, both supplies, VDD1 and
VDD2 must be equal to VSS +/- 0.3V. Warm spare operation is
in effect when one power supply is >1V and the other power
supply is equal to VSS +/- 0.3V. If VDD1 has a power on ramp
longer than 1 second, then VDD2 should be powered on first to
ensure proper control of DIRx and OEx. During normal opera-
tion of the part, after power-up, ensure VDD1>VDD2.
By definition, warm sparing occurs when half of the chip re-
ceives its normal VDD supply value while the VDD supplying the
other half of the chip is set to 0.0V. When the chip is "warm
spared", the side that has VDD set to a normal operational value
is "actively" tri-stated because the chip’s internal OE signal is
forced low. The side of the chip that has VDD set to 0.0V is "pas-
sively" tri-stated by the cold spare circuitry. In order to mini-
mize transients and current consumption, the user is encouraged
to first apply a high level to the OEx pins and then power down
the appropriate supply.
Port B Port A OPERATION
5 Volts 3.3 Volts Voltage Translator
5 Volts 5 Volts Non Translating
3.3 Volts 3.3 Volts Non Translating
VSS VSS Cold Spare
VSS 3.3V or 5V Port A Warm Spare
3.3V or 5V VSS Port B Warm Spare
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LOGIC DIAGRAM
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
DIR1 (1)
(47)
(48)
(2)
(46)
(3)
(44)
(5)
(43)
(6)
(41)
(8)
(40)
(9)
(38)
(11)
(37)
(12)
1B1
1B2
1B3
1B6
1B5
1B4
1B8
1B7
OE1
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
DIR2 (24)
(36)
(25)
(13)
(35)
(14)
(33)
(16)
(32)
(17)
(30)
(19)
(29)
(20)
(27)
(22)
(26)
(23)
2B1
2B2
2B3
2B6
2B5
2B4
2B8
2B7
OE2
3.3V PORT
5 V PORT
3.3V PORT
5 V PORT
5
RADIATION HARDNESS SPECIFICATIONS 1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other cond itions b eyond limits indicated in the operational sections is no t recommended. Exposu re to absolute maximum r ating cond itions for extended
periods may affect device reliability and performance.
2. For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating VDD + 0.3V.
DUAL SUPPLY OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E5 rad(Si)
SEL Immune >114 MeV-cm2/mg
Neutron Fluence21.0E14 n/cm2
SYMBOL PARAMETER LIMIT (Mil only) UNITS
VI/O (Port B)2Voltage any pin during operation -.3 to VDD1 +.3 V
VI/O (Port A)2Voltage any pin during operation -.3 to VDD2 +.3 V
VDD1 Supply voltage -0.3 to 6.0 V
VDD2 Supply voltage -0.3 to 6.0 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD1 Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V
VDD2 Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V
VIN (Port B) Input voltage any pin 0 to VDD1 V
VIN (Port A) Input voltage any pin 0 to VDD2 V
TCTemperature range -55 to + 125 °C
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DC ELECTRICAL CHARACTERISTICS 1
(Tc = -55°C to +125°C for "C" screening and -4 0°C to +125°C for "W" screening)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VT+Schmitt Trigger, positive going threshold2 VDD from 3.0 to 5.5 .7VDD V
VT-Schmitt T rigger, negative going threshold2VDD from 3.0 to 5.5 .3VDD V
VH1 Schmitt Trigger range of hysteresis VDD from 4.5 to 5.5 0.6 V
VH2 Schmitt Trigger range of hysteresis VDD from 3.0 to 3.6 0.4 V
IIN Input leakage current VDD from 3.6 to 5.5
VIN = VDD or VSS
-1 3μA
IOZ Three-state output leakage current VDD from 3.6 to 5.5
VIN = VDD or VSS
-1 3μA
ICS Cold sparing leakage current3VIN = 5.5
VDD = VSS
-1 5μA
IWS Warm sparing input leakage current (any
pin)3VIN = 5.5V
VDD1 = VSS & VDD2 = 3.0V to 5.5V
or
VDD1 = 3.0V to 5.5V & VDD2 = VSS
-1 5μA
IOS1 Short-circuit output current 6, 10 VO = VDD or VSS
VDD from 4.5 to 5.5
-200 200 mA
IOS2 Short-circuit output current 6, 10 VO = VDD or VSS
VDD from 3.0 to 3.6
-100 100 mA
VOL1 Low-level output voltage4IOL= 8mA
IOL= 100μA
VDD = 4.5
0.4
0.2
V
VOL2 Low-level output voltage4IOL= 8mA
IOL= 100μA
VDD = 3.0
0.5
0.2
V
VOH1 High-level output voltage4IOH= -8mA
IOH= -100μA
VDD = 4.5
VDD - 0.7
VDD - 0.2
V
VOH2 High-level output voltage4IOH= -8mA
IOH= -100μA
VDD = 3.0
VDD - 0.9
VDD - 0.2
V
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Notes:
1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. This parameter is unaffected by the state of OEx or DIRx.
4. Per MIL-PRF-38535 , for current den sity ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
5. Guaranteed by characterization.
6. Not more than one output may be shorted at a time for maximum duration of one second.
7. Power does not include power contribution of any CMOS output sink current.
8. Power dissipation specified per switching output.
9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
10. Supplied as a design limit, but not guaranteed or tested.
.
Ptotal1 Power dissipation 5,7, 8 CL = 50pF
VDD from 4.5 to 5.5
2.0 mW/
MHz
Ptotal2 Power dissipation 5, 7, 8 CL = 50pF
VDD from 3.00 to 3.6
1.5 mW/
MHz
IDDQ Standby Supply Current VDD1 or VDD2
Pre-Rad 25oC
Pre-Rad -55oC to +125oC
Post-Rad 25oC
VIN = VDD or VSS
VDD = 5.5
OE = VDD
OE = VDD
OE = VDD
60
100
100
μA
μA
μA
CIN Input capacitance 9ƒ = 1MHz @ 0V
VDD from 3.0 to 5.5
15 pF
COUT Output capacitance9ƒ = 1MHz @ 0V
VDD from 3.0 to 5.5
15 pF
8
AC ELECTRICAL CHARACTERISTICS1 (Port B = 5 Volt, Port A = 3.3 Volt)
(VDD1 = 5V ±10%; VDD2 = 3.3V ± 0.3V) (Tc = -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)
Notes:
1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low.
SYMBOL PARAMETER MIN MAX UNIT
UT54ACS164245SEI
tPLH Propagation delay Data to Bus 3.5 11 ns
tPHL Propagation delay Data to Bus 3.5 11 ns
tPZL Output enable time OEx to Bus 2.5 16 ns
tPZH Output enable time OEx to Bus 2.5 16 ns
tPLZ Output disable time OEx to Bus high impedance 2.5 16 ns
tPHZ Output disable time OEx to Bus high impedance 2.5 16 ns
tPZL2Output enable time DIRx to Bus 118 ns
tPZH2Output enable time DIRx to Bus 118 ns
tPLZ2Output disable time DIRx to Bus high im pedance 120 ns
tPHZ2Output disable time DIRx to Bus high impedance 120 ns
tSKEW3Skew between outputs - 600 ps
tDSKEW4Differential skew between outputs -1.5 ns
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tPLZ
tPZH
tPZL
tPHL
tPHZ
Propagation Delay
Input
Output
VDD
VDD/2
0V
tPLH
VOH
VOL
VDD/2
Control Input
5V Output
Normally Low
Enable Disable Times
5V Output
Normally High
VDD
VDD/2
0V
VDD/2
VDD/2
.8VDD
.2VDD
VDD/2+0.2
VDD/2-0.2 .2VDD + .2V
.8VDD - .2V
tPLZ
tPZH
tPZL
tPHZ
3.3V Output
Normally Low
3.3V Output
Normally High
VDD/2
VDD/2
.7VDD
.2VDD
VDD/2+0.2
VDD/2-0.2 .2VDD + .2V
.7VDD - .2V
10
AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 5 Volt Operation)
(VDD1 = 5V ± 10%; VDD2 = 5.0V ± 10%) (Tc = -55°C to +125°C for "C" screening and -40°C to +125°C fo r "W" screening)
Notes:
1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low.
SYMBOL PARAMETER MIN MAX UNIT
UT54ACS164245SEI
tPLH Propagation delay Data to Bus 3.5 9 ns
tPHL Propagation delay Data to Bus 3.5 9 ns
tPZL Output enable time OEx to Bus 3 9 ns
tPZH Output enable time OEx to Bus 3 9 ns
tPLZ Output disable time OEx to Bus high impedance 3 9 ns
tPHZ Output disable time OEx to Bus high impedance 3 9 ns
tPZL2Output enable time DIRx to Bus 112 ns
tPZH2Output enable time DIRx to Bus 112 ns
tPLZ2Output disable time DIRx to Bus high im pedance 115 ns
tPHZ2Output disable time DIRx to Bus high impedance 115 ns
tSKEW3Skew between outputs - 600 ps
tDSKEW4Differential skew between outputs -1.5 ns
11
tPLZ
tPZH
tPZL
tPHZ
Control Input
5V Output
Normally Low
Enable Disable Times
5V Output
Normally High
VDD
VDD/2
0V
VDD/2
VDD/2
.8VDD
.2VDD
VDD/2+0.2
VDD/2-0.2 .2VDD + .2V
.8VDD - .2V
tPHL
Propagation Delay
Input
Output
VDD
VDD/2
0V
tPLH
VOH
VOL
VDD/2
tPLZ
tPZH
tPZL
tPHL
tPHZ
Propagation Delay
Input
Output
VDD
VDD/2
0V
tPLH
VOH
VOL
VDD/2
Control Input
3.3V Output
Normally Low
Enable Disable Times
3.3V Output
Normally High
VDD
VDD/2
0V
VDD/2
VDD/2
.7VDD
.2VDD
VDD/2+0.2
VDD/2-0.2 .2VDD + .2V
.7VDD - .2V
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AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 3.3 Volt Operation)
(VDD1 = 3.3V + 0.3V; VDD2 = 3.3V + 0.3V) (Tc = -55°C to +125°C for "C" screening and -40°C to +125°C for "W" screening)
Notes:
1. All specifications vali d fo r radia tion do se ≤ 1E5 rad(Si) per MIL-STD-883, Me thod 1019.
2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested.
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to- l ow vs. low-to-high and low-to- high vs high-to low.
SYMBOL PARAMETER MIN MAX UNIT
UT54ACS164245SEI
tPLH Propagation delay Data to Bus 3.5 11 ns
tPHL Propagation delay Data to Bus 3.5 11 ns
tPZL Output enable time OEx to Bus 2.5 16 ns
tPZH Output enable time OEx to Bus 2.5 16 ns
tPLZ Output disable time OEx to Bus high impedance 2.5 16 ns
tPHZ Output disable time OEx to Bus high impedance 2.5 16 ns
tPZL2Output enable time DIRx to Bus 1 18 ns
tPZH2Output enable time DIRx to Bus 1 18 ns
tPLZ2Output disable time DIRx to Bus high impedance 1 20 ns
tPHZ2Output disable time DIRx to Bus high impedance 1 20 ns
tSKEW3Skew between outputs 600 ps
tDSKEW4Differential skew between outputs 1.5 ns
13
PACKAGE
14
ORDERING INFORMATION
UT54ACS164245SEI: SMD
Lead Finish:
(C) = Gold
Case Outline:
(X) = 48 lead BB FP (Gold only)
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(06) = 16-bit MultiPurpose Transceiver with warm and cold sparing (Full Mil-Te mp)
(07) = 16-bit MultiPurpose Transceiver with warm and cold sparing (Extended Industrial Temp)
Drawing Number: 98580
Total Dose: (Note 1)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
5962 R 98580 ** * * *
Notes:
1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
15
UT54ACS164245SEI
UT54 *** ****** -* * *
Lead Finish:
(C) = Gold
Screening:
(C) = Mil Temp (-55oC to +125oC)
(P) = Prototype (Room temp Only)
(W) = Extended Industrial Temp (-40oC to +125oC)
Package Type:
(U) = 48-lead BB FP (Gold only)
Part Number:
(164245SEI) = 16-bit MultiPurpose Transceiver with warm and cold sparing
I/O Type:
(ACS)= CMOS compatible I/O Level
Aeroflex Core Part Number
Notes:
1. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation neither
tested nor guaranteed.
2. Extended Industrial Temperature Range Flow per Aeroflex Manufacturing Flows Document. Devices are tested at -40oC, room temp, and +125oC.
Radiation is neither tested nor guaranteed
16
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changes to any products and services herein at any time
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel