SRDA05-4.TET - Semtech - Datasheet.Live

PROTECTION PRODUCTS

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PROTECTION PRODUCTS - RailClamp®®

®®

SRDA05-4 and SRDA12-4

RailClamp®®

®®

Low Capacitance TVS Diode Array

Description Features

Circuit Diagram Schematic and PIN Configuration

Revision 8/21/07

RailClamps are surge rated diode arrays designed to

protect high speed data interfaces. The SRDA series

has been specifically designed to protect sensitive

components which are connected to data and trans-

mission lines from overvoltage caused by electrostatic

discharge (ESD), electrical fast transients (EFT), and

lightning.

The unique design incorporates surge rated, low

capacitance steering diodes and a TVS diode in a

single package. During transient conditions, the

steering diodes direct the transient current to ground

via the internal low voltage TVS. The TVS diode clamps

the transient voltage to a safe level. The low capaci-

tance array configuration allows the user to protect up

to four high-speed data lines. The SRDA05-4 may be

used to protect lines operating up to 5 volts while the

SRDA12-4 may be used on lines operating up to 12

volts.

These devices are in a 8-pin SOIC package. They are

available with a SnPb or RoHS/WEEE compliant matte

tin lead finish. The high surge capability (Ipp=25A,

tp=8/20μs) means it can be used in high threat

environments in applications such as CO/CPE equip-

ment, telecommunication lines, and video lines.

Applications

Mechanical Characteristics

USB Power and Data Line Protection

T1/E1 secondary IC Side Protection

T3/E3 secondary IC Side Protection

HDSL, SDSL secondary IC Side Protection

Video Line Protection

Microcontroller Input Protection

Base stations

I2C Bus Protection

Transient protection for high-speed data lines to

IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)

IEC 61000-4-4 (EFT) 40A (5/50ns)

IEC 61000-4-5 (Lightning) 24A (8/20μs)

Array of surge rated diodes with internal TVS diode

Protects four I/O lines

Low capacitance (<15pF) for high-speed interfaces

Low operating and clamping voltages

Solid-state technology

JEDEC SOIC-8 package

Lead Finish: SnPb or Matte Sn

Molding compound flammability rating: UL 94V-0

Marking : Part number, date code, logo

Packaging : Tape and Reel per EIA 481

I/O 3

I/O 4

REF 2

I/O 1

I/O 2

REF 1

S0-8 (Top View)

REF1

I/O 1 I/O 2 I/O 3 I/O 4

REF2

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

4-50ADRS

retemaraPlobmySsnoitidnoCmuminiMlacipyTmumixaMstinU

egatloVffO-dnatSesreveRV

MWR

egatloVnwodkaerBesreveRV

Am1=6 V

tnerruCegakaeLesreveRI

MWR

C°52=T,V5=01Aμ

egatloVgnipmalCV

t,A1=

sμ02/8=8.9V

egatloVgnipmalCV

t,A01=

sμ02/8=21V

egatloVgnipmalCV

t,A52=

sμ02/8=02V

tnerruCesluPkaePI

sμ02/8=52A

ecnaticapaCnoitcnuJC

dnasnipO/IneewteB

dnuorG

zHM1=f,V0=

851Fp

snipO/IneewteB

zHM1=f,V0=

4Fp

Absolute Maximum Rating

gnitaRlobmySeulaVstinU

t(rewoPesluPkaeP

)sμ02/8=P

005sttaW

I(egatloVdrawroFkaeP

t,A1=

)sμ02/8=V

5.1V

erutarepmeTgniredloSdaeLT

).ces01(062C°

erutarepmeTgnitarepOT

521+ot55-C°

erutarepmeTegarotST

GTS

051+ot55-C°

Electrical Characteristics (T=25oC)

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

4-21ADRS

retemaraPlobmySsnoitidnoCmuminiMlacipyTmumixaMstinU

egatloVffO-dnatSesreveRV

MWR

21V

egatloVnwodkaerBesreveRV

Am1=3.31V

tnerruCegakaeLesreveRI

MWR

C°52=T,V21=1Aμ

egatloVgnipmalCV

t,A1=

sμ02/8=71V

egatloVgnipmalCV

t,A01=

sμ02/8=02V

egatloVgnipmalCV

t,A02=

sμ02/8=52V

tnerruCesluPkaePI

sμ02/8=02A

ecnaticapaCnoitcnuJC

dnasnipO/IneewteB

dnuorG

zHM1=f,V0=

851Fp

snipO/IneewteB

zHM1=f,V0=

4Fp

Electrical Characteristics (continued)

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Typical Characteristics

Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve

0.01

0.1

0.1 1 10 100 1000

Pulse Duratio n - tp (µs)

Peak Pulse Pow er - Ppk (kW)

100

110

0 25 50 75 100 125 150

Ambien t Temperatur e - TA (oC)

% of Rated Power or I

Clamping Voltage vs. Peak Pulse Current

100

110

0 5 10 15 20 25 30

Tim e (µs)

Per cent of I PP

e-t

td = IPP/2

Waveform

Para me te rs:

tr = 8µ s

td = 2 0µs

Pulse Waveform

0 5 10 15 20 25 30

Peak Pu l se Current - IPP (A)

Clamping Voltage - VC (V)

SRDA05-4

SRDA3.3-4

Waveform

Parameters:

tr = 8µs

td = 20µs

SRDA12-4

Variation of Capacitance vs. Reverse Voltage Forward Voltage vs. Forward Current

0 5 10 15 20 25 30 35 40 45 50

Forward Current - IF (A)

For war d Vo l tage - VF (V)

Waveform

Parameters:

tr = 8μs

td = 20μs

0.88

0.9

0.92

0.94

0.96

0.98

1.02

1.04

00.511.522.533.5

Reverse Voltage - VR (V)

Cj ( V R) / Cj (VR =0 )

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Device Connection Options for Protection of Four

High-Speed Lines

The SRDA TVS is designed to protect four data lines

from transient overvoltages by clamping them to a

fixed reference. When the voltage on the protected

line exceeds the reference voltage (plus diode VF) the

steering diodes are forward biased, conducting the

transient current away from the sensitive circuitry.

Data lines are connected at pins 1, 4, 6 and 7. The

negative reference is connected at pins 5 and 8.

These pins should be connected directly to a ground

plane on the board for best results. The path length is

kept as short as possible to minimize parasitic induc-

tance.

The positive reference is connected at pins 2 and 3.

The options for connecting the positive reference are

as follows:

1. To protect data lines and the power line, connect

pins 2 & 3 directly to the positive supply rail (VCC).

In this configuration the data lines are referenced

to the supply voltage. The internal TVS diode

prevents over-voltage on the supply rail.

2. The SRDA can be isolated from the power supply by

adding a series resistor between pins 2 and 3 and

VCC. A value of 10kΩ is recommended. The

internal TVS and steering diodes remain biased,

providing the advantage of lower capacitance.

3. In applications where no positive supply reference

is available, or complete supply isolation is desired,

the internal TVS may be used as the reference. In

this case, pins 2 and 3 are not connected. The

steering diodes will begin to conduct when the

voltage on the protected line exceeds the working

voltage of the TVS (plus one diode drop).

Data Line and Power Supply Protection Using Vcc as

reference

Data Line Protection with Bias and Power Supply

Isolation Resistor

Data Line Protection Using Internal TVS Diode as

Reference

ESD Protection With RailClamps

RailClamps are optimized for ESD protection using the

rail-to-rail topology. Along with good board layout,

these devices virtually eliminate the disadvantages of

using discrete components to implement this topology.

Consider the situation shown in Figure 1 where dis-

crete diodes or diode arrays are configured for rail-to-

rail protection on a high speed line. During positive

duration ESD events, the top diode will be forward

biased when the voltage on the protected line exceeds

the reference voltage plus the V

drop of the diode.

For negative events, the bottom diode will be biased

Applications Information

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

PIN Descriptions

Figure 1 - “Rail-To-Rail” Protection Topology

(First Approximation)

Figure 2 - The Effects of Parasitic Inductance When

Using Discrete Components to Implement Rail-To-Rail

Protection

Figure 3 - Rail-To-Rail Protection Using

RailClamp TVS Arrays

Applications Information (continued)

when the voltage exceeds the V

of the diode. At first

approximation, the clamping voltage due to the charac-

teristics of the protection diodes is given by:

= V

+ V

(for positive duration pulses)

= -V

(for negative duration pulses)

However, for fast rise time transient events, the

effects of parasitic inductance must also be consid-

ered as shown in Figure 2. Therefore, the actual

clamping voltage seen by the protected circuit will be:

= V

+ V

+ L

ESD

/dt (for positive duration pulses)

= -V

- L

ESD

/dt (for negative duration pulses)

ESD current reaches a peak amplitude of 30A in 1ns

for a level 4 ESD contact discharge per IEC 61000-4-2.

Therefore, the voltage overshoot due to 1nH of series

inductance is:

V = L

ESD

/dt = 1X10-9 (30 / 1X10-9) = 30V

Example:

Consider a V

= 5V, a typical V

of 30V (at 30A) for the

steering diode and a series trace inductance of 10nH.

The clamping voltage seen by the protected IC for a

positive 8kV (30A) ESD pulse will be:

= 5V + 30V + (10nH X 30V/nH) = 335V

This does not take into account that the ESD current is

directed into the supply rail, potentially damaging any

components that are attached to that rail. Also note

the high V

of the discrete diode. It is not uncommon

for the V

of discrete diodes to exceed the damage

threshold of the protected IC. This is due to the

relatively small junction area of typical discrete compo-

nents. It is also possible that the power dissipation

capability of the discrete diode will be exceeded, thus

destroying the device.

The RailClamp is designed to overcome the inherent

disadvantages of using discrete signal diodes for ESD

suppression. The RailClamp’s integrated TVS diode

helps to mitigate the effects of parasitic inductance in

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Applications Information (continued)

the power supply connection. During an ESD event,

the current will be directed through the integrated TVS

diode to ground. The total clamping voltage seen by

the protected IC due to this path will be:

= V

F(RailClamp)

+ V

TVS

This is given in the data sheet as the rated clamping

voltage of the device. For an SRDA05-4 the typical

clamping voltage is <16V at I

=30A. The diodes

internal to the RailClamp are low capacitance, fast

switching devices that are rated to handle high tran-

sient currents and maintain excellent forward voltage

characteristics.

Using the RailClamp does not negate the need for good

board layout. All other inductive paths must be consid-

ered. The connection between the positive supply and

the SRDA and from the ground plane to the SRDA

must be kept as short as possible. The path between

the SRDA and the protected line must also be mini-

mized. The protected lines should be routed directly to

the SRDA. Placement of the SRDA on the PC board is

also critical for effective ESD protection. The device

should be placed as close as possible to the input

connector. The reason for this is twofold. First,

inductance resists change in current flow. If a signifi-

cant inductance exists between the connector and the

TVS, the ESD current will be directed elsewhere (lower

resistance path) in the system. Second, the effects of

radiated emissions and transient coupling can cause

upset to other areas of the board even if there is no

direct path to the connector. By placing the TVS close

to the connector it will divert the ESD current immedi-

ately and absorb the ESD energy before it can be

coupled into nearby traces.

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

T1/E1 Interface Protection

Universal Serial Bus ESD Protection

Typical Applications

SRDA05-4

LC01-6

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Applications Information - Spice Model

SRDA05-4 & SRDA12-4 Spice Model

sretemaraPecipS4-21ADRS&4-50ADRS

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)SVT(3D

4-21ADRS

)SVT(3D

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VBtloV08604207.651

JVtloV26.046.065.87.

SRmhO081.0551.065.004.0

VBIpmA3-E0.13-E0.13-E0.13-E0.1

OJCdaraF21-E

2.521-E2.621-E70321-E17

TTces9-E145.29.-E145.29-E145.29-E145.2

M--850.0850.0742.0642.0

N--1.11.11.11.1

GEVe11.111.111.111.1

Pin 1

Pin 3

Pin 8

0.6 nH

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Land Pattern - SO-8

Outline Drawing - SO-8

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2X N/2 TIPS

SEATING

aaa C

E/2

bbb C A-B D

ccc C e/2

A2 SEE DETAIL A

SIDE VIEW

DETAIL A

(L1) 01

0.25

GAGE

PLANE

3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

OR GATE BURRS.

-B-

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

DATUMS AND TO BE DETERMINED AT DATUM PLANE

NOTES:

2. -A- -H-

REFERENCE JEDEC STD MS-012, VARIATION AA.

.050 BSC

.236 BSC

.010

.150

.189 .154

.193

.012 -

0.25

1.27 BSC

6.00 BSC

3.90

4.90

.157

.197 3.80

4.80

.020 0.31

4.00

5.00

0.51

(.041)

.004

.008

.028

0°

.016

.007

.049

.004

.053

8° 0°

0.20

0.10

-8°

0.40

0.17

1.25

0.10

.041

.010

.069

.065

.010 1.35

(1.04)

0.72

1.04

0.25

-1.75

1.65

0.25

.010 .020 0.50

bbb

aaa

ccc

DIM MIN

MILLIMETERS

NOM

DIMENSIONS

INCHES

MIN MAX MAXNOM

(.205) (5.20)

.118 1.27

.050 0.60.024 2.20.087 7.40.291

INCHES

DIMENSIONS

DIM

MILLIMETERS

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

NOTES:

REFERENCE IPC-SM-782A, RLP NO. 300A.

PROTECTION PRODUCTS

SRDA05-4 and SRDA12-4

Contact Information

Semtech Corporation

Protection Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805)498-2111 FAX (805)498-3804

Ordering Information

Note: Lead-free devices are RoHS/WEEE Compliant

SC YYWW

SRDA05-4

PHIL

Marking Diagram

Note:

YYWW = Date Code

Tape and Reel Specification

Device Orientation in Tape

epaT

htdiW )xaM(,BD1DE F

)XAM( P0P2P)XAM(TW

mm21mm2.8 mm1.0+5.1

mm0.0-

mm5.101.±057.1

50.0±5.5

mm mm5.4 1.0±0.4

1.0±0.4

50.0±0.2

mm mm4.0

mm0.21

3.0±

0A0B0K

mm02.0-/+05.6mm02.0-/+04.5mm01.0-/+00.2

Pin 1 Location

User Direction of feed

rebmuNtraPhsiniFdaeL repytQ

leeR eziSleeR

BT.4-50ADRSbPnS005hcnI7

TBT.4-50ADRSnSettaM005hcnI7

BT.4-21ADRSbPnS005hcnI7

TBT.4-21ADRSnSettaM005hcnI7

SC YYWW

SRDA12-4

PHIL

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Semtech:

SRDA05-4.TET SRDA12-4.TBT SRDA05-4.TBT