74LVC1G53 2-channel analog multiplexer/demultiplexer Rev. 05 -- 11 June 2008 Product data sheet 1. General description The 74LVC1G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device. The 74LVC1G53 provides one analog multiplexer/demultiplexer with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features n Wide supply voltage range from 1.65 V to 5.5 V n Very low ON resistance: u 7.5 (typical) at VCC = 2.7 V u 6.5 (typical) at VCC = 3.3 V u 6 (typical) at VCC = 5 V n Switch current capability of 32 mA n High noise immunity n CMOS low-power consumption n TTL interface compatibility at 3.3 V n Latch-up performance meets requirements of JESD 78 Class I n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Control inputs accepts voltages up to 5 V n Multiple package options n Specified from -40 C to +85 C and from -40 C to +125 C 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC1G53DP -40 C to +125 C TSSOP8 74LVC1G53DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC1G53GT -40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 74LVC1G53GD -40 C to +125 C XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 74LVC1G53GM -40 C to +125 C XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 4. Marking Table 2. Marking codes Type number Marking code 74LVC1G53DC V53 74LVC1G53DP V53 74LVC1G53GT V53 74LVC1G53GD V53 74LVC1G53GM V53 5. Functional diagram Y1 S Y0 Z E 001aah795 Fig 1. Logic symbol 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 2 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Y0 S Z Y1 E Fig 2. 001aad387 Logic diagram 6. Pinning information 6.1 Pinning 74LVC1G53 Z 1 8 VCC E 2 7 Y0 GND 3 6 Y1 GND 4 5 S 74LVC1G53 Z 1 8 VCC E 2 7 Y0 GND 3 6 Y1 GND 4 5 S 001aad389 Transparent top view 001aad388 Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 4. Pin configuration SOT833-1 (XSON8) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 3 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 74LVC1G53 1 8 VCC E 2 7 Y0 GND 3 6 Y1 GND 4 5 S Y1 S 8 1 7 Z 2 6 E 3 5 GND GND Z Y0 4 74LVC1G53 VCC terminal 1 index area 001aai249 Transparent top view Transparent top view Fig 5. 001aag459 Pin configuration SOT996-2 (XSON8U) Fig 6. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Symbol Pin description Pin Description SOT505-2, SOT765-1, SOT996-2 and SOT833-1 SOT902-1 Z 1 7 common output or input E 2 6 enable input (active LOW) GND 3 5 ground (0 V) GND 4 4 ground (0 V) S 5 3 select input Y1 6 2 independent input or output Y0 7 1 independent input or output VCC 8 8 supply voltage 7. Functional description Table 4. Function table[1] Input Channel on S E L L Y0 to Z or Z to Y0 H L Y1 to Z or Z to Y1 X H Z (switch off) [1] H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 4 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] VI input voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V ISK switch clamping current VI < -0.5 V or VI > VCC + 0.5 V VSW switch voltage enable and disable mode VSW > -0.5 V or VSW < VCC + 0.5 V [2] Min Max Unit -0.5 +6.5 V -0.5 +6.5 V -50 - mA - 50 mA -0.5 VCC + 0.5 V ISW switch current - 50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 C - 250 mW total power dissipation Ptot Tamb = -40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. [3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature t/V input transition rise and fall rate Conditions Min Max Unit 1.65 5.5 V 0 5.5 V 0 VCC V enable and disable mode [1] -40 +125 C VCC = 1.65 V to 2.7 V [2] - 20 ns/V VCC = 2.7 V to 5.5 V [2] - 10 ns/V [1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit for the voltage drop across the switch. [2] Applies to control signal levels. 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 5 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = -40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage Tamb = -40 C to +125 C Unit Max Min Max 0.65 x VCC - - 0.65 x VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3 V to 3.6 V 2.0 - - 2.0 - V 0.7 x VCC - - 0.7 x VCC - V VCC = 1.65 V to 1.95 V VCC = 4.5 V to 5.5 V VIL Typ[1] VCC = 1.65 V to 1.95 V - - 0.35 x VCC - 0.35 x VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 3 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 x VCC - 0.3 x VCC V - 0.1 2 - 10 A II input leakage current pin S and pin E; VI = 5.5 V or GND; VCC = 0 V to 5.5 V [2] IS(OFF) OFF-state leakage current VI = VIH or VIL; VCC = 5.5 V; see Figure 7 [2] - 0.1 5 - 20 A IS(ON) ON-state leakage current VI = VIH or VIL; VCC = 5.5 V; see Figure 8 [2] - 0.1 5 - 20 A ICC supply current VI = 5.5 V or GND; VSW = GND or VCC; IO = 0 A; VCC = 1.65 V to 5.5 V [2] - 0.1 10 - 40 A ICC additional pin S and pin E; supply current VI = VCC - 0.6 V; IO = 0 A; VSW = GND or VCC; VCC = 5.5 V [2] - 5 500 - 5000 A CI input capacitance - 2.5 - - - pF CS(OFF) OFF-state capacitance - 6.0 - - - pF CS(ON) ON-state capacitance - 18 - - - pF [1] Typical values are measured at Tamb = 25 C. [2] These typical values are measured at VCC = 3.3 V. 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 6 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.1 Test circuits VCC S VIL or VIH Y0 Z Y1 1 switch switch S E 1 VIL VIH 2 VIH VIH IS 2 E GND VIH VI VO 001aad390 VI = VCC or GND; VO = GND or VCC. Fig 7. Test circuit for measuring OFF-state leakage current VCC S VIL or VIH IS Z Y0 1 Y1 2 switch S E 1 VIL VIL 2 VIH VIL switch E GND VIL VO VI 001aad391 VI = VCC or GND and VO = open circuit. Fig 8. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(peak) Parameter -40 C to +85 C Conditions -40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 34.0 130 - 195 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 12.0 30 - 45 ISW = 12 mA; VCC = 2.7 V - 10.4 25 - 38 ISW = 24 mA; VCC = 3 V to 3.6 V - 7.8 20 - 30 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 6.2 15 - 23 ON resistance (peak) VI = GND to VCC; see Figure 9 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 7 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 8. ON resistance ...continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(rail) Parameter -40 C to +85 C Conditions ON resistance (rail) -40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 8.2 18 - 27 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24 ISW = 12 mA; VCC = 2.7 V - 6.9 14 - 21 ISW = 24 mA; VCC = 3 V to 3.6 V - 6.5 12 - 18 ISW = 32 mA; VCC = 4.5 V to 5.5 V - 5.8 10 - 15 ISW = 4 mA; VCC = 1.65 V to 1.95 V - 10.4 30 - 45 ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.6 20 - 30 ISW = 12 mA; VCC = 2.7 V - 7.0 18 - 27 ISW = 24 mA; VCC = 3 V to 3.6 V - 6.1 15 - 23 - 4.9 10 - 15 - 26.0 - - - VI = GND; see Figure 9 VI = VCC; see Figure 9 ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) [2] VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - ISW = 12 mA; VCC = 2.7 V - 3.5 - - - ISW = 24 mA; VCC = 3 V to 3.6 V - 2.0 - - - ISW = 32 mA; VCC = 4.5 V to 5.5 V - 1.5 - - - [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. 10.3 ON resistance test circuit and graphs VSW VCC VIL or VIH S Y0 1 Z Y1 2 switch S E 1 VIL VIL 2 VIH VIL switch E GND VIL ISW VI 001aad392 RON = VSW / ISW. Fig 9. Test circuit for measuring ON resistance 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 8 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer mna673 40 RON () 30 (1) 20 (2) (3) 10 (4) (5) 0 0 1 2 3 4 5 VI (V) (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 C 001aaa712 55 RON () 001aaa708 15 RON () 45 13 35 11 (4) (3) (2) (1) (1) (2) 25 9 (3) (4) 15 7 5 5 0 0.4 0.8 1.2 1.6 2.0 0 0.5 VI (V) 1.5 2.0 2.5 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = -40 C. (4) Tamb = -40 C. Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V 74LVC1G53_5 Product data sheet 1.0 (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 9 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 001aaa709 13 001aaa710 10 RON () RON () 11 8 (1) (1) 9 (2) (2) 6 (3) (3) 7 (4) (4) 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 0 1 2 3 4 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = -40 C. (4) Tamb = -40 C. Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V 001aaa711 7 RON () 6 5 (1) (2) (3) 4 (4) 3 0 1 2 3 4 5 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C. Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 10 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter -40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V - - 2 - 2.5 ns VCC = 2.3 V to 2.7 V - - 1.2 - 1.5 ns VCC = 2.7 V - - 1.0 - 1.25 ns VCC = 3.0 V to 3.6 V - - 0.8 - 1.0 ns VCC = 4.5 V to 5.5 V - - 0.6 - 0.8 ns VCC = 1.65 V to 1.95 V 2.6 6.7 10.3 2.6 12.9 ns VCC = 2.3 V to 2.7 V 1.9 4.1 6.4 1.9 8.0 ns VCC = 2.7 V 1.9 4.0 5.5 1.8 7.0 ns VCC = 3.0 V to 3.6 V 1.8 3.4 5.0 1.8 6.3 ns 1.3 2.6 3.8 1.3 4.8 ns VCC = 1.65 V to 1.95 V 1.9 4.0 7.3 1.9 9.2 ns VCC = 2.3 V to 2.7 V 1.4 2.5 4.4 1.4 5.5 ns VCC = 2.7 V 1.1 2.6 3.9 1.1 4.9 ns VCC = 3.0 V to 3.6 V 1.2 2.2 3.8 1.2 4.8 ns VCC = 4.5 V to 5.5 V 1.0 1.7 2.6 1.0 3.3 ns VCC = 1.65 V to 1.95 V 2.1 6.8 10.0 2.1 12.5 ns VCC = 2.3 V to 2.7 V 1.4 3.7 6.1 1.4 7.7 ns VCC = 2.7 V 1.4 4.9 6.2 1.4 7.8 ns VCC = 3.0 V to 3.6 V 1.1 4.0 5.4 1.1 6.8 ns 1.0 2.9 3.8 1.0 4.8 ns VCC = 1.65 V to 1.95 V 2.3 5.6 8.6 2.3 11.0 ns VCC = 2.3 V to 2.7 V 1.2 3.2 4.8 1.2 6.0 ns VCC = 2.7 V 1.4 4.0 5.2 1.4 6.5 ns VCC = 3.0 V to 3.6 V 2.0 3.7 5.0 2.0 6.3 ns VCC = 4.5 V to 5.5 V 1.3 2.9 3.8 1.3 4.8 ns propagation delay Z to Yn or Yn to Z; see Figure 16 tpd enable time ten S to Z or Yn; see Figure 17 [2][3] [4] VCC = 4.5 V to 5.5 V E to Z or Yn; see Figure 17 disable time tdis S to Z or Yn; see Figure 17 [4] [5] VCC = 4.5 V to 5.5 V E to Z or Yn; see Figure 17 [1] -40 C to +125 C Unit Typ[1] [5] Typical values are measured at Tamb = 25 C and nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPLZ and tPHZ. 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 11 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits VI Yn or Z input VM VM GND tPLH tPHL VOH Z or Yn output VM VM VOL 001aac361 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Input (Yn or Z) to output (Z or Yn) propagation delays VI S, E input VM GND tPLZ Z, Yn output LOW to OFF OFF to LOW VCC Z, Yn VM VX VOL output HIGH to OFF OFF to HIGH tPZL tPHZ VOH tPZH VY VM GND switch enabled switch disabled switch enabled 001aad393 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 17. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH - 0.3 V 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 12 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance (should be equal to output impedance Zo of the pulse generator). CL = Load capacitance (including jig and probe capacitance). RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 18. Load circuit for switching times Table 11. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open GND 2VCC 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open GND 2VCC 2.7 V VCC 2.5 ns 50 pF 500 open GND 2VCC 3 V to 3.6 V VCC 2.5 ns 50 pF 500 open GND 2VCC 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2VCC 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions THD total harmonic distortion fi = 600 Hz to 20 kHz; RL = 600 ; CL = 50 pF; VI = 0.5 V (p-p); see Figure 19 f(-3dB) Min Typ Max Unit VCC = 1.65 V - 0.260 - % VCC = 2.3 V - 0.078 - % VCC = 3.0 V - 0.078 - % VCC = 4.5 V - 0.078 - % -3 dB frequency response RL = 50 ; CL = 5 pF; see Figure 20 VCC = 1.65 V - 200 - MHz VCC = 2.3 V - 300 - MHz VCC = 3.0 V - 300 - MHz VCC = 4.5 V - 300 - MHz 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 13 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Parameter Conditions iso isolation (OFF-state) RL = 50 ; CL = 5 pF; fi = 10 MHz; see Figure 21 Qinj Min Typ Max Unit VCC = 1.65 V - -42 - dB VCC = 2.3 V - -42 - dB VCC = 3.0 V - -40 - dB VCC = 4.5 V - -40 - dB VCC = 1.8 V - 3.3 - pC VCC = 2.5 V - 4.1 - pC VCC = 3.3 V - 5.0 - pC VCC = 4.5 V - 6.4 - pC VCC = 5.5 V - 7.5 - pC CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 22 charge injection 11.3 Test circuits 0.5VCC VCC S VIL or VIH 0.1 F Z Y0 1 Y1 2 switch S E 1 VIL VIL 2 VIH VIL RL 10 F switch E VIL CL 600 fi D GND 001aad394 Fig 19. Test circuit for measuring total harmonic distortion 0.5VCC VCC S VIL or VIH 0.1 F Z Y0 1 Y1 2 RL switch S E 1 VIL VIL 2 VIH VIL switch E VIL fi CL 50 dB GND 001aad395 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB. Fig 20. Test circuit for measuring the frequency response when switch is in ON-state 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 14 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 0.5VCC 0.5VCC VCC RL S VIL or VIH 0.1 F switch S E 1 VIH VIH 2 VIL VIH RL Z Y0 1 Y1 2 switch E VIH dB CL 50 fi GND 001aad396 Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) VCC S Y0 1 Z Y1 2 switch E Rgen VIL VI G VO RL CL Vgen GND 001aad398 a. Test circuit logic (S) off input on VO off VO 001aac478 b. Input and output pulse definitions Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 22. Test circuit for measuring charge injection 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 15 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 23. Package outline SOT505-2 (TSSOP8) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 16 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 24. Package outline SOT765-1 (VSSOP8) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 17 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4x (2) L L1 e 8 7 6 e1 5 e1 e1 8x A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 25. Package outline SOT833-1 (XSON8) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 18 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 26. Package outline SOT996-2 (XSON8U) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 19 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C v M C A B w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 27. Package outline SOT902-1 (XQFN8U) 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 20 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model CDM Charged Device Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G53_5 20080611 Product data sheet - 74LVC1G53_4 Modifications: * Added type number 74LVC1G53GD (XSON8U / SOT996-2 package) 74LVC1G53_4 20080303 Product data sheet - 74LVC1G53_3 74LVC1G53_3 20070829 Product data sheet - 74LVC1G53_2 74LVC1G53_2 20060410 Product data sheet - 74LVC1G53_1 74LVC1G53_1 20060110 Product data sheet - - 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 21 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC1G53_5 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 05 -- 11 June 2008 22 of 23 74LVC1G53 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms and test circuits . . . . . . . . . . . . . . 12 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 June 2008 Document identifier: 74LVC1G53_5