Semiconductor Components Industries, LLC, 2002
October, 2002 – Rev. 1 1Publication Order Number:
NTLMS4506N/D
NTLMS4506N
Advance Information
Power MOSFET
30 A, 30 V N–Channel SO–8 Leadless
The SO–8LL (Leadless) package uses the power QFN package
technology. It’s footprint matches that of the standard SO–8 single die
device. This Leadless SO–8 package provides low parasitic
inductance compared to the standard SO–8 package allowing for
higher frequency operation.
Features
•Planar HD3E Process for Fast Switching Performance
•Body Diode for Low trr and Qrr, Optimized for Synchronous
Operation
•Low RDSon to Minimize Conduction Loss
•Low Ciss to Minimize Driver Loss
•Optimized Qdg X RSDon (FOM) for Shootthrough Protection
•Low Gate Charge
•Surface Mount
Product Summary
Symbol Value
VDS 30 V
RDSon @ 10 V 3.5 m
Qg33 nC
ID30 A
Qgd 10 nC
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
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Device Package Shipping
ORDERING INFORMATION
NTLMS4506N SO–8 Leadless 2500 Tape &
Reel
SO–8 Leadless
CASE 751S
PIN ASSIGNMENT
PIN
1FUNCTION
S – SOURCE
MARKING
DIAGRAM
xxxxx = Specific Device Code
Y = Year
WW = Work Week
2 G – GATE
3 D – DRAIN
xxxxx
WWY
D
S
G
1[S]
2[G]
3[D]
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2
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter Symbol Value Units
Drain–to–Source Voltage VDSS 30 Vdc
Gate–to–Source Voltage Continuous VGS ±20 Vdc
Drain Current Continuous @ TA = 25°C (Note 1)
Continuous @ TA = 25°C (Note 2)
Single Pulse (tp = 10 s) (Note 4)
ID
IDM
IDM
20
30
84
A
A
A
Maximum Power Dissipation (Steady State) @ TA = 25°C (Note 1)
Single Pulse (tp = 10 Secs) TA = 25°C (Note 2) PD
PD2.5
6.0 W
W
Operating and Storage Temperature TJ and Tstg –55 to 150 °C
Single Pulse Drain–to Source Avalanche Energy Starting TJ = 25°C EAS 220 mJ
Thermal Resistance Junction–to–Ambient (Note 1)
Junction–to–Ambient (Note 2)
Junction–to–Ambient (Note 3)
RJA
RJA
RJA
50
20
100
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8” from Case for 10 Secs TL260 °C
1. When surface mounted to an FR4 board using 1” pad size, (Cu Area 1.127 in2).
2. 1” pad (Cu Area 0.911 in2), t < 10sec.
3. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2).
4. Chip current capability limited by package.
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3
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Characteristics Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Note 5)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(br)DSS 30
–33
25 –
–Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 24 Vdc, VGS = 0 Vdc)
(VDS = 24Vdc, VGS = 0 Vdc, TJ = 150 °C)
IDSS –
––
–1.0
10
Adc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS – – ±100 nAdc
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage (Note 5)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th) 1.0
–1.5
–3.8 2.0
–Vdc
mV/°C
Static Drain–to–Source On–Resistance (Note 5)
VGS = 10 Vdc, ID = 30 Adc
VGS = 4.5 Vdc, ID = 15 Adc
RDS(on) –
–3.5
4.8 4.4
5.8
m
Forward Transconductance (Note 5) (VDS = 10 Vdc, ID = 10 Adc) gFS – 90 – Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 30 Vdc, VGS = 0 V, f = 1 MHz) Ciss – 4900 5150 pF
Output Capacitance Coss – 1275 1352
Transfer Capacitance Crss – 380 400
SWITCHING CHARACTERISTICS (Note 6)
Turn–On Delay Time (Ven = 10 Vdc, VDD = 15 Vdc, ID = 30 Adc,
R25)
td(on) – 30 36 ns
Rise Time RG = 2.5 )tr– 15 19
Turn–Off Delay Time td(off) – 110 132
Fall Time tf – 35 42
Gate Charge (VGS = 4.5 Vdc, ID = 30 Adc,
V10 V ) (Note 5)
QT(g) – 33 36 nC
VDS = 10 Vdc) (Note 5) Q1(gs) – 18 –
Q2(gd) – 10 –
Qsw – TBD –
Qoss – TBD –
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Volta
g
e (I
S
= 15 A
dc
, V
GS
= 0 V
dc
) (Note 5) V
S
DV
dc
Forward
On Voltage
(IS
=
15
Ad
c,
VGS
=
0
Vd
c
)
(Note
5)
(IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
– 0.70
07
1.2
Vd
c
(Sdc,GS dc,J)
– 0.7 –
Reverse Recovery Time (IS = 15 Adc, VGS = 0 Vdc, VDD = 24 V
dI /dt 100 A/s) (Note 5)
trr – 37 54 ns
dIS/dt = 100 A/s) (Note 5) ta– 20 –
tb– 18 –
Reverse Recovery Stored Charge QRR – 0.026 – C
5. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
6. Switching characteristics are independent of operating junction temperatures.
NTLMS4506N
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4
PACKAGE DIMENSIONS
SO–8 Leadless
CASE 751S–02
ISSUE A
Ç
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Ç
H
0.20 K
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
DIM MIN MAX
MILLIMETERS
A1.750 1.950
A1 0.254 REF
B0.900 1.100
D6.000 BSC
D1 3.046 3.246
D3
0.154 0.354
E
1.246 1.446
E1
5.000 BSC
F2.940 3.140
G0.400 0.600
J1 0.680 0.880
J2 0.250 0.450
J3 0.154 0.354
E
A
A1
D
D2
D3
B
E1
J
0.08 K
0.08 K
K
PIN #1 I.D.
D2
J3
J3
D1
F
J1
J2
J2
G
D2
4.392 4.592
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NTLMS4506N/D
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