LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 LM34919C-Q1 Ultra Small 50V, 600 mA Constant On-Time Buck Switching Regulator Check for Samples: LM34919C-Q1 FEATURES APPLICATIONS * * * * * * * * * * * * 1 2 * * * * * * * * * AEC-Q100 qualified (Tj = -40C to 125C) Maximum Switching Frequency: 2.6 MHz Input Voltage Range: 4.5 V to 50 V Integrated N-Channel buck switch Integrated Start-Up Regulator No Loop Compensation Required Ultra-Fast Transient Response Operating Frequency Remains Constant with Load Current and Input Voltage Adjustable Output Voltage Power Good Output Enable Input Valley Current Limit at 0.64 A Typical Precision Internal Voltage Reference Low IQ Shutdown (<10 A) Highly Efficient Operation Thermal Shutdown 12-Bump 2 mm x 2 mm DSBGA and 12-pin 4 mm x 4 mm WSON Packages Automotive Safety and Infotainment High Efficiency Point-of-Load (POL) Regulator Telecommunication Buck Regulator Secondary Side Post Regulator DESCRIPTION The LM34919C Step Down Switching Regulator features all of the functions needed to implement a low-cost, efficient, buck bias regulator capable of supplying 0.6 A to the load. This buck regulator contains an N-Channel Buck Switch and is available in DSBGA and WSON packages. The constant ontime feedback regulation scheme requires no loop compensation, results in fast load transient response, and simplifies circuit implementation. The operating frequency remains constant with line and load variations due to the inverse relationship between the input voltage and the on-time. The valley current limit results in a smooth transition from constant voltage to constant current mode when current limit is detected, reducing the frequency and output voltage, without the use of foldback. Additional features include: Power Good, enable, VCC undervoltage lockout, thermal shutdown, gate drive undervoltage lockout, and maximum duty cycle limiter. 4.5V - 50V Input VIN C1 VCC C3 C5 REN RON LM34919C BST RON VOUT C4 EN L1 RPGD PGD VOUT SW PGD D1 R1 SS R3 ISEN C2 C6 FB RTN SGND R2 Figure 1. Basic Step Down Regulator 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2013, Texas Instruments Incorporated LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) VALUE UNIT VIN, EN , RON to RTN 65 V BST to RTN 79 V -1.5 to 65 V +0.3 V BST to VCC 65 V BST to SW 14 V VCC to RTN 14 V PGD 14 V SW to RTN (Steady State) SW to VIN SGND to RTN -0.3 to 0.3 V SS to RTN -0.3 to 4 V FB to RTN -0.3 to 7 V -65 to 150 C 2 kV 150 C Storage Temperature Range ESD Rating HBM Junction Temperature (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the devices at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (1) VALUE VIN Junction Temperature (1) 2 UNIT 4.5 to 50 V -40 to 125 C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device is intended to be fully functional. For verified specifications and test conditions, see Electrical Characteristics. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 Electrical Characteristics Unless otherwise specified, these specifications apply for -40C TJ +125C, VIN = 12 V, RON = 100 k. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ Max Units 2.1 3.0 V 10 50 A 1 8 A 7 7.6 V EN Power Up Feature (EN Pin) EN EN Threshold EN rising EN Disable Threshold EN falling ISD EN Input Current EN = VIN = 12 V VIN Shutdown Current EN = 0 V 0.5 1.3 V Start-Up Regulator, VCC VCCReg VCC Regulated Output VIN = 12 V 6.1 VIN =4.5 V, ICC = 3 mA UVLOVCC 4.43 V VIN - VCC Dropout Voltage ICC = 0 mA, Non-Switching VCC = UVLOVCC + 250 mV 20 mV VCC Output Impedance 0 mA ICC 5 mA, VIN = 4.5 V 16 0 mA ICC 5 mA, VIN = 8 V 8 VCC Current Limit VCC = 0 V VCC Under-Voltage Lockout Threshold Measured at VCC VCC Increasing 3.4 3.75 4.1 VCC Decreasing 3.25 3.6 3.95 27 UVLOVCC Hysteresis, at VCC IQ mA 150 mV VCC Under-Voltage Lock-Out Threshold Measured at VIN VIN Increasing, ICC = 3 mA VCC Under-Voltage Lock-Out Threshold Measured at VIN VIN Decreasing, ICC = 3 mA UVLOVCC Filter Delay 100 mV Overdrive IIN Operating Current Non-Switching, FB = 3 V, SW = Open 2.2 3.8 Buck Switch Rds(on) (DSBGA) ITEST = 200 mA 0.35 0.9 Buck Switch Rds(on) (WSON-12) ITEST = 200 mA 0.45 1 Gate Drive UVLO VBST - VSW Increasing 2.95 3.60 3.90 V 4.50 V 3.80 4.25 3 s mA Switch Characteristics Rds(on) UVLOGD 2.40 VBST - VSW Decreasing 2.82 UVLOGD Hysteresis V 130 mV 2.52 V 10.5 A Soft-start Pin VSS Pull-Up Voltage Internal Current Source VSS = 1V Threshold Current out of ISEN Current Limit ILIM 0.52 0.64 0.76 A Resistance from ISEN to SGND 190 m Response Time 50 ns On Timer tON - 1 On-Time VIN = 12 V, RON = 100 k 300 tON - 2 On-Time VIN = 24 V, RON = 100 k 175 tON - 3 On-Time VIN = 4.5 V, RON = 100 k 760 ns Off Timer tOFF Minimum Off-time 100 120 150 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 ns 3 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, these specifications apply for -40C TJ +125C, VIN = 12 V, RON = 100 k. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ Max 2.47 2.52 2.57 Units Regulation and Over-Voltage Comparators (FB Pin) VREF FB Regulation Threshold SS pin = Steady State V FB Over-Voltage Threshold 3.0 FB Bias Current FB = 3 V 1 nA Power Good Feature (PGD Pin) PGDUV PGDOV Td, PGD IPGD PGD UV Threshold Rising, With Respect to VREF FB Increasing PGD UV Threshold Falling FB Decreasing PGD OV Threshold Rising FB Increasing PGD OV Threshold Falling FB Decreasing PGD Delay Falling Edge PGD Pulldown Vin = 4.5 V, FB = 3 V, Vpg = 0.1 V 87 92 90 97 % 120 110 10 1 us mA Thermal Shutdown TSD Thermal Shutdown Temperature 175 Thermal Shutdown Hysteresis 20 Junction to Ambient 0 LFPM Air Flow (DSBGA Packages) 61 For WSON Package (Exposed Pad) 50 C Thermal Resistance JA 4 C/W Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 PIN DESCRIPTIONS D1 D2 D3 C1 C2 C3 B1 B2 B3 A1 A2 A3 Figure 2. DSBGA Package Bump View BST SW VIN VCC EN ISEN SS PGD SGND FB RTN RON Figure 3. DSBGA Package Top View VIN 1 12 SW ISEN 2 11 BST 3 WSON-12 SGND 4 Exposed Pad RTN EN 10 VCC 9 PGD 5 8 SS RON 6 7 FB Figure 4. WSON Top View Pin Descriptions PIN NUMBER PIN NUMBER (WSON-12) NAME A1 6 RON On-time control and shutdown An external resistor from VIN to this pin sets the buck switch on-time. A2 5 RTN Circuit Ground Ground for all internal circuitry other than the current limit detection. A3 7 FB Feedback input from the regulated output Internally connected to the regulation and overvoltage comparators. The regulation level is 2.52 V (typ.). B1 4 SGND Sense Ground Re-circulating current flows into this pin to the current sense resistor. DESCRIPTION APPLICATION INFORMATION Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 5 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com Pin Descriptions (continued) PIN NUMBER PIN NUMBER (WSON-12) NAME B2 9 PGD B3 8 SS C1 2 ISEN C2 3 EN C3 10 D1 APPLICATION INFORMATION Power Good Open drain. Logic output indicates when the voltage at the FB pin has increased above 92% of the internal reference. The falling threshold for PGD is 90% of the internal reference. An external pull-up resistor connecting PGD pin to a voltage less than 14 V is required. Soft-start An internal current source charges an external capacitor to 2.52 V, providing the soft-start function. Current sense The re-circulating current flows through the internal sense resistor and out of this pin to the freewheeling diode. Valley current limit is nominally set at 0.64 A. Enable Pin Pull low to disable the part for low shutdown current. Shutdown threshold is 1.3 V (typ). VCC Output from the startup regulator Nominally regulated at 7.0 V. An external voltage (7 V - 14 V) can be applied to this pin to reduce internal dissipation. An internal diode connects VCC to VIN. 1 VIN Input supply voltage Nominal input range is 4.5 V to 50 V. D2 12 SW Switching Node Internally connected to the buck switch source. Connects to the inductor, free-wheeling diode, and bootstrap capacitor. D3 11 BST Boost pin for bootstrap capacitor Connect a 0.022 F capacitor from SW to this pin. The capacitor is charged from VCC via an internal diode during each off-time. EP (WSON Only) 6 DESCRIPTION Exposed pad should be connected to RTN pin and system ground for proper cooling. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 4.5V to 50V Input LM34919C 7V SERIES REGULATOR VIN VCC C5 VCC UVLO C1 GND C3 RON ON TIMER RON START RON 2.1V EN FINISH OFF TIMER START FINISH BST Gate Drive SD UVLO 2.52V 10.5 A VIN C4 LOGIC SS C6 LEVEL SHIFT Driver FB L1 SW THERMAL SHUTDOWN REGULATION COMPARATOR CURRENT LIMIT COMPARATOR 0.92VREF D1 R1 + - 64 mV + UNDER-VOLTAGE COMPARATOR RSENSE 100 m R3 ISEN R2 C2 SGND GND 1.2VREF RTN RPGD Power Good VOUT PGD OVER-VOLTAGE COMPARATOR Figure 5. Functional Block Diagram Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 7 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com Typical Performance Characteristics Efficiency at 2.1 MHz, VOUT = 3.3 V Efficiency at 250 kHz, VOUT = 3.3 V 90 95 EFFICIENCY (%) EFFICIENCY (%) 90 80 70 Vin = 6V Vin = 9V Vin = 12V Vin = 18V 60 0.2 0.3 0.4 0.5 85 80 75 70 0.6 LOAD CURRENT (A) Vin = 4.5V Vin = 6V Vin = 9V Vin = 12V Vin = 18V Vin = 24V 0.2 0.3 0.4 0.5 0.6 LOAD CURRENT (A) C002 Efficiency at 2.1 MHz, VOUT = 5 V C002 VCC vs. VIN 95 10 85 VCC (V) EFFICIENCY (%) 8 6 4 75 Vin = 9V Vin = 12V Vin = 18V Vin = 24V 65 0.2 0.3 0.4 0.5 2 0 0.6 LOAD CURRENT (A) 0 5 10 15 20 25 30 35 40 45 INPUT VOLTAGE (V) C003 VCC vs. ICC 50 C004 ICC vs. Externally Applied VCC 10 8 Vin = 4.5V 7 Vin = 12V 8 5 ICC (mA) VCC (V) 6 4 3 2 4 2 1 Vcc Externally Loaded Fsw = 2 MHz Fsw = 2 MHz 0 0 0 5 10 15 ICC (mA) 8 6 20 25 30 7 C005 Submit Documentation Feedback 8 9 10 11 APPLIED VCC (V) 12 13 14 C006 Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 Typical Performance Characteristics (continued) ON-TIME vs. VIN and RON Voltage at the RON Pin Ron = 100k Ron = 61.9k Ron = 35.7K Ron = 46.4k 100 0.6 Ron = 100k Ron = 61.9k Ron = 46.4k 0.5 RON PIN VOLTAGE (V) ON-TIME (ns) 1000 0.4 0.3 0.2 0.1 0.0 10 0 10 20 30 40 0 50 INPUT VOLTAGE (V) 10 20 30 40 50 INPUT VOLTAGE (V) C007 Operating Current into VIN C001 Shutdown Current into VIN 6.00 0.20 INPUT CURRENT (A) INPUT CURRENT (mA) 5.00 4.00 3.00 2.00 1.00 0.15 0.10 0.05 No Load FB = 3V EN = 0V 0.00 0.00 0 5 10 15 20 25 30 35 40 45 50 INPUT VOLTAGE (V) 0 5 15 20 25 30 35 40 45 INPUT VOLTAGE (V) C002 Gate Drive UVLO vs. Temperature 50 C006 Reference Voltage vs. Temperature 4.0 2.57 Driver On 2.56 REFERENCE VOLTAGE (V) Driver Off GATE DRIVE UVLO (V) 10 3.5 3.0 2.5 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.0 Vin = 12V 2.47 50 25 0 25 50 75 100 JUNCTION TEMPERATURE (|C) 125 150 50 C004 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 150 C007 9 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com Typical Performance Characteristics (continued) Soft-Start Current vs. Temperature Operating Current vs. Temperature 3.6 CURRENT INTO VIN (mA) SOFT-START CURRENT (A) 11.5 11.0 10.5 10.0 9.5 3.2 2.8 2.4 2.0 1.6 1.2 VIN = 12V Vin = 12V 9.0 0.8 50 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) 150 50 25 C001 VCC UVLO at Vin vs. Temperature 25 50 75 100 125 150 C008 VCC Voltage vs. Temperature 4.50 8.0 7.5 4.25 7.0 6.5 4.00 VCC (V) VCC UVLO MEASURED AT VIN (V) 0 JUNCTION TEMPERATURE (|C) 3.75 3.50 6.0 5.5 5.0 4.5 4.0 Vin Increasing 3.25 Vin = 12V 3.5 Vin Decreasing 3.00 Vin = 4.5V 3.0 50 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) 150 50 25 50 75 100 125 JUNCTION TEMPERATURE (|C) C003 VCC Current Limit vs. Temperature 150 C005 VCC Output Impedence vs. Temperature 40 30 VCC OUTPUT IMPEDANCE ( VCC CURRENT LIMIT (mA) 25 0 35 30 25 20 Vin = 8V Vin = 4.5V 25 20 15 10 5 Vin = 12V 15 0 50 25 0 25 50 75 100 JUNCTION TEMPERATURE (|C) 10 125 150 50 C006 Submit Documentation Feedback 25 0 25 50 75 100 JUNCTION TEMPERATURE (|C) 125 150 C009 Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 Typical Performance Characteristics (continued) Minimum Off-Time vs. Temperature On-Time vs. Temperature 400 150 140 300 135 ON-TIME (ns) MINIMUM OFF-TIME (ns) 145 130 125 120 115 100 110 105 200 RON = 100k VIN = 12V Vin = 12V 100 0 50 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) 150 50 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) C007 Current Limit Threshold vs. Temperature 150 C002 EN Pin Threshold vs. Temperature 0.80 3.0 EN Rising 0.75 ENABLE THRESHOLD (V) CURRENT LIMIT THRESHOLD (A) 25 0.70 0.65 0.60 0.55 EN Falling 2.5 2.0 1.5 1.0 0.5 VIN = 12V 0.50 0.0 50 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) 150 50 25 0 25 50 75 100 125 JUNCTION TEMPERATURE (|C) C003 150 C004 PGD vs. Sink Current 0.30 PGD VOLTAGE (V) 0.25 0.20 0.15 0.10 0.05 0.00 0 2 4 6 PGD SINK CURRENT (mA) 8 10 C005 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 11 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com VIN EN UVLO VCC PGD SS SW FB VOUT tt1t tt2t Figure 6. Start-Up Sequence Functional Description Device Information The LM34919C Step Down Switching Regulator features all the functions needed to implement a low cost, efficient buck bias power converter capable of supplying 600 mA to the load. This high voltage regulator is easy to implement and is available in DSBGA and WSON packages. The regulator's operation is based on a constant on-time control scheme, where the on-time is determined by VIN. This feature allows the operating frequency to remain relatively constant with load and input voltage variations. The feedback control requires no loop compensation resulting in fast load transient response. The valley current limit detection circuit, internally set at 0.64 A, holds the buck switch off until the high current level subsides. This scheme protects against excessively high current if the output is short-circuited when VIN is high. The LM34919C can be applied in numerous applications to efficiently step down higher voltages. Additional features include: Thermal shutdown, VCC undervoltage lockout, gate drive undervoltage lockout, maximum duty cycle limiter, power good, and enable. Control Circuit Overview The LM34919C buck DC-DC regulator employs a control scheme based on a comparator and a one-shot ontimer, with the output voltage feedback (FB) compared to an internal reference (2.52 V). If the FB voltage is below the reference the N-channel buck switch is turned on for a time period determined by the input voltage and a programming resistor RON. Following the on-time the switch remains off until the FB voltage falls below the reference but not less than the minimum off-time. The buck switch then turns on for another on-time period. Typically, during start-up, or when the load current increases suddenly, the off-times are at the minimum. Once regulation is established, in steady state operations, the off-times are longer and automatically adjust to produce the SW pin duty cycle required for output regulation. 12 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 When in regulation, the LM34919C operates in continuous conduction mode at heavy load currents and discontinuous conduction mode at light load currents. In continuous conduction mode current always flows through the inductor, never reaching zero during the off-time. In this mode the operating frequency remains relatively constant with load and line variations. The minimum load current for continuous conduction mode is one-half the inductor's ripple current amplitude. The operating frequency is approximately: VOUT FS Hz RON u 35.5 u 10-12 (1) The buck switch duty cycle is approximately equal to: VOUT tON DC = tON + tOFF = VIN (2) In discontinuous conduction mode, current through the inductor ramps up from zero to a peak during the on-time, then ramps back to zero before the end of the off-time. The next on-time period starts when the voltage at FB falls below the reference. Until then the inductor current remains zero, and the load current is supplied by the output capacitor. In this mode the operating frequency is lower than in continuous conduction mode, and varies with load current. Conversion efficiency is maintained at light loads since the switching losses decrease with the reduction in load and frequency. The output voltage is set by two external resistors (R1, R2). The regulated output voltage is calculated as follows: VOUT = 2.52 x (R1 + R2) / R2 (3) Output voltage regulation is based on ripple voltage at the feedback input, normally obtained from the output voltage ripple through the feedback resistors. The LM34919C requires a minimum of 25 mV of ripple voltage at the FB pin. In cases where the output capacitor's ESR is insufficient additional series resistance may be required (R3). Start-Up Regulator, VCC The start-up regulator is integral to the LM34919C. The input pin (VIN) can be connected directly to line voltage up to 50 V with transient capability to 65 V. The VCC output regulates at 7.0 V and is current limited at 27 mA. Upon power up, the regulator sources current into the external capacitor at VCC (C3). When the voltage on the VCC pin reaches the undervoltage lockout rising threshold of 3.75 V, the buck switch is enabled and the softstart pin is released to allow the soft-start capacitor (C6) to charge up. The minimum input voltage is determined by the VCC UVLO falling threshold (3.6 V). When VCC falls below the falling threshold the VCC UVLO activates to shut off the output. If VCC is externally loaded, the minimum input voltage increases. To reduce power dissipation in the start-up regulator, an auxiliary bias voltage can be diode connected to the VCC pin (see Figure 7). Setting the auxiliary bias voltage between 7.6 V and 14 V shuts off the internal regulator reducing internal power dissipation. The sum of the auxiliary voltage and the input voltage (VCC + VIN) cannot exceed 79 V. An internal diode connects VCC to VIN. (See Figure 5). Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 13 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com VCC C3 BST C4 L1 LM34919C D2 SW VOUT D1 ISEN R1 R3 SGND R2 C2 FB Figure 7. Self Biased Configuration Regulation Comparator The feedback voltage at FB is compared to the voltage at the soft-start pin. In normal operation (the output voltage is regulated), an on-time period is initiated when the voltage at FB falls below 2.52 V. The buck switch stays on for the programmed on-time causing the FB voltage to rise above 2.52 V. After the on-time period, the buck switch stays off until the FB voltage falls below 2.52 V. Input bias current at the FB pin is less than 100 nA over temperature. Overvoltage Comparator and Undervoltage Comparator The voltage at FB is compared to an internal overvoltage comparator reference (120% of internal reference voltage). If the voltage at FB rises above this reference, the on-time pulse is immediately terminated. This condition can occur if the input voltage or the output load changes suddenly, or if the inductor (L1) saturates. The buck switch remains off until the voltage at FB falls below 2.52 V. When the FB pin voltage rises above the undervoltage comparator voltage reference (92% of the internal reference voltage), the PGD pin is released and is pulled high by the external pull-up resistor. When the FB pin voltage measures less than 90% of the internal reference voltage, the PGD pin switches low. ON-Time Timer The on-time is determined by the RON resistor and the input voltage (VIN), and is calculated from: TON RON u 35.5 u 10-12 s VIN (4) The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. To set a specific continuous conduction mode switching frequency (fS), the RON resistor is determined from the following: VOUT RON : FS u 35.5 u 10-12 (5) The minimum off-time limits the maximum duty cycle achievable with a low voltage at VIN. The minimum on-time is limited to 90 ns. Enable The LM34919C can be remotely shut down by forcing the Enable (EN) pin low. The bias and control circuits are turned off when EN is pulled below the enable shutdown falling threshold of 1.3 V (typ). In the shutdown mode the input current falls below 10 A. If remote shutdown feature is not needed the EN pin can be connected to the input voltage or any voltage greater than 3 V. In this case the device is enabled and disabled based on the VCC UVLO threshold. 14 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 Current Limit Current limit detection occurs during the off-time by monitoring the recirculating current through the free-wheeling diode (D1). Referring to Figure 5, when the buck switch is turned off the inductor current flows out of ISEN and through D1. If the valley point of that current exceeds 0.64 A the current limit comparator output switches to delay the start of the next on-time period. The next on-time starts when the valley point of the current out of ISEN is below 0.64 A and the voltage at FB is below 2.52 V. If the overload condition persists causing the inductor current valley point to exceed 0.64 A during each cycle the operating frequency is lower due to longer-thannormal off-times. Figure 8 illustrates the inductor current waveform. During normal operation the load current is Io, the average of the ripple waveform. When the load resistance decreases the current ratchets up until the lower peak reaches 0.64 A. During the Current Limited portion of Figure 8, the current ramps down to 0.64 A during each off-time, initiating the next on-time (assuming the voltage at FB is <2.52 V). During each on-time the current ramps up an amount equal to: I = (VIN - VOUT) x tON / L1 (6) During this time the LM34919C operates in a constant current mode with an average load current (IOCL) equal to 0.64 A + I/2. Generally, in applications where the switching frequency is higher than 300 kHz and a relatively small value inductor is used, the higher dl/dt of the inductor's ripple current results in an effectively lower valley current limit threshold due to the response time of the current limit detection circuit. However, since the small value inductor results in a relatively high ripple current amplitude (I in Figure 8), the load current (IOCL) at current limit typically exceeds 640 mA. IPK 'I IOCL Inductor Current 0.64A IO Normal Operation Load Current Increases Current Limited Figure 8. Inductor Current - Current Limit Operation N - Channel Buck Switch and Driver The LM34919C integrates an N-Channel buck switch and associated floating high side gate driver. The peak current allowed through the buck switch is 1.5 A, and the maximum allowed average current is 1 A. The gate driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.022 F capacitor (C4) connected between BST and SW provides the voltage to the driver during the on-time. During each off-time, the SW pin is at approximately -1 V, and C4 charges from VCC through the internal diode. The minimum off-time of LM34919C ensures sufficient time each cycle to recharge the bootstrap capacitor. Soft-Start The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing start-up stresses and current surges. Upon turn-on, after VCC reaches the undervoltage threshold, an internal 10.5 A current source charges up the external capacitor at the SS pin to 2.52 V. The ramping voltage at SS (and the inverting input of the regulation comparator) ramps up the output voltage in a controlled manner. An internal switch grounds the SS pin if VCC is below the undervoltage lockout threshold, or if the EN pin is grounded. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 15 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com Power Good Output The Power Good Output (PGD) indicates when the voltage at the FB pin is close to the internal 2.52 V reference voltage. The PGD pin remains low inside the device when the FB pin voltage is outside the range set by the PGDUV and PGDOV thresholds (see Electrical Characteristics). The PGD pin is internally connected to the drain of an N-channel MOSFET switch. An external pull-up resistor (RPGD), connected to an appropriate voltage not exceeding 14 V, is required at PGD to indicate the status of LM34919C to other circuitry. For best results, pull up the PGD pin to the output voltage. When PGD is low, the voltage at the pin is determined by the current into the pin. See the graph "PGD Low Voltage vs. Sink Current." Upon powering, as VIN is increased, PGD stays low until the output voltage takes the voltage at the FB pin above 92% of the internal reference voltage, at which time PGD switches high. As VIN is decreased (e.g., during shutdown), PGD remains high until the voltage at the FB pin falls below 90% (typ.) of the internal reference. PGD then switches low and remains low. Thermal Shutdown The LM34919C should be operated such that the junction temperature does not exceed 125C. If the junction temperature increases to 175C (typical), an internal Thermal Shutdown circuit forces the controller to a lowpower reset state by disabling the buck switch. This feature helps prevent catastrophic failures from accidental device overheating. When the junction temperature reduces below 155C (hysteresis = 20C) normal operation resumes. 16 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 APPLICATION INFORMATION External Components The procedure for calculating the external components is illustrated with the following design example. Referring to Figure 5, the circuit is to be configured for the following specifications: - VOUT = 3.3 V - VIN = 4.5 V to 24 V - Minimum load current = 200 mA - Maximum load current = 600 mA - Switching Frequency = 1.5 MHz - Soft-start time = 5 ms R1 and R2: These resistors set the output voltage. The ratio of the feedback resistors is calculated from: R1/R2 = (VOUT/2.52 V) - 1 (7) For this example, R1/R2 = 0.32. R1 and R2 should be chosen from standard value resistors in the range of 1.0 k - 10 k which satisfy the above ratio. For this example, 2.49 k is chosen for R2 and 787 for R1. RON: This resistor sets the on-time and the switching frequency. The switching frequency must be less than 1.53 MHz to ensure the minimum forced on-time does not cause cycle skipping when operating at the maximum input voltage. The RON resistor is calculated from Equation 8: VOUT RON 61.9k: FSW x 35.5 x1012 (8) Check that this value resistor does not set an on-time less than 90 ns at maximum VIN. A standard value 61.9 k resistor is used, resulting in a nominal frequency of 1.50 MHz. The minimum on-time is calculated 92 ns at Vin = 24 V, and the maximum on-time is 488 ns at Vin = 4.5 V. Alternately, RON can be determined using Equation 4 if a specific on-time is required. L1: The main parameter affected by the inductor is the inductor current ripple amplitude (IOR). The minimum load current is used to determine the maximum allowable ripple in order to maintain continuous conduction mode, where the lower peak does not reach 0 mA. This is not a requirement of the LM34919C, but serves as a guideline for selecting L1. For this case the maximum ripple current is: IOR(MAX) = 2 x IOUT(min) = 400 mA (9) If the minimum load current is zero, use 20% of IOUT(max) for IOUT(min) in Equation 9. The ripple calculated in Equation 9 is then used in Equation 10: L1 = ( V IN (m ax ) - V OUT ) x t on (min I OR (MAX ) = 4.76 H (10) ) A standard value 8.2 H inductor is selected. The maximum ripple amplitude, which occurs at maximum VIN, calculates to 232 mA p-p, and the peak current is 716 mA at maximum load current. Ensure the selected inductor is rated for this peak current. C2 and R3: Since the LM34919C requires a minimum of 25 mVp-p ripple at the FB pin for proper operation, the required ripple at VOUT is increased by R1 and R2. This necessary ripple is created by the inductor ripple current flowing through R3, and to a lesser extent by the ESR of C2. The minimum inductor ripple current is calculated using Equation 6, rearranged to solve for IOR at minimum VIN. IOR (MIN ) = kVIN:min ; F VOUT o x t on (max ) = 71.4 mA L1 (11) The minimum value for R3 is equal to: R3(min ?) = 25mV x (R1+ R2) R2 x I OR (MI N ?) = 0.47 3 (12) Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 17 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com A standard value 0.47 resistor is used for R3 to allow for tolerances. C2 should generally be no smaller than 3.3 F, although that is dependent on the frequency and the desired output characteristics. C2 should be a low ESR, good quality ceramic capacitor. Experimentation is usually necessary to determine the minimum value for C2, as the nature of the load may require a larger value. A load which creates significant transients requires a larger value for C2 than a non-varying load. C1 and C5: C1's purpose is to supply most of the switch current during the on-time and limit the voltage ripple at VIN. At maximum load current, when the buck switch turns on, the current into VIN suddenly increases to the lower peak of the inductor's ripple current, ramps up to the upper peak, then drops to zero at turn-off. The average current during the on-time is the load current. For a worst case calculation, C1 must supply this average load current during the maximum on-time, without letting the voltage at VIN drop more than 0.5 V. The minimum value for C1 is calculated from: C1 = IOUT (max) x tON 'V = 0.5 PF (13) where tON is the maximum on-time, and V is the allowable ripple voltage. Input ripple of 0.5 V is acceptable in typical applications. C5's purpose is to minimize transients and ringing due to long lead inductance leading to the VIN pin. A low ESR, 0.1 F ceramic chip capacitor must be located close to the VIN and RTN pins. C3: The capacitor at the VCC pin provides noise filtering and stability for the Vcc regulator. C3 should be no smaller than 0.1 F, and should be a good quality, low ESR, ceramic capacitor. C3's value, and the VCC current limit, determine a portion of the turn-on-time (t1 in (Figure 6). C4: The recommended value for C4 is 0.022 F. A high quality ceramic capacitor with low ESR is recommended as C4 supplies a surge current to charge the buck switch gate at each turn-on. A low ESR also helps ensure a complete recharge during each off-time. C6: The capacitor at the SS pin determines the soft-start time, i.e. the time for the output voltage to reach its final value (t2 in Figure 6). The capacitor value is determined from the following: C6 = t2 x 10.5 PA 2.5V = 0.021 PF (14) D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed transitions at the SW pin may inadvertently affect the device's operation through external or internal EMI. The diode should be rated for the maximum input voltage, the maximum load current, and the peak current which occurs in current limiting. The diode's average power dissipation is calculated from: PD1 = VF x IOUT x (1-D) (15) where VF is the diode forward voltage drop, and D is the duty cycle at the SW pin. Final Circuit The final circuit is shown in Figure 9, and its performance is shown in Figure 10 and Figure 11. 4.5V - 24V Input C1 2.2 F C5 0.1 F R4 C3 0.1 F 100 k RON 61.9 k VOUT VCC VIN EN RON BST VOUT SW 3.3V D1 R5 10 k SS L1 8.2 H LM34919C PGD C6 0.022 F C4 0.022 F ISEN R1 787 FB RTN SGND R2 2.49 k R3 0.47 C2 22 F Figure 9. Example Circuit 18 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 95 4.5V EFFICIENCY (%) 90 85 9V 80 12V 75 18V 70 65 24V 60 55 0.2 0.3 0.4 0.5 0.6 LOAD CURRENT (A) Figure 10. Efficiency (1.5 MHz, VOUT = 3.3 V) FREQUENCY (MHz) 3 2.5 2 1.5 1 Ron=61.9k 0.5 4 8 12 16 20 INPUT VOLTAGE (V) 24 28 Figure 11. Frequency vs. VIN (VOUT = 3.3 V) Low Output Ripple Configurations For applications where lower ripple at VOUT is required, the following options can be used to reduce or nearly eliminate the ripple. a) Reduced ripple configuration: In Figure 12, Cff is added across R1 to AC-couple the ripple at VOUT directly to the FB pin. This allows the ripple at VOUT to be reduced to a minimum of 25 mVp-p by reducing R3, since the ripple at VOUT is not attenuated by the feedback resistors. The minimum value for Cff is determined from: Cff = tON (max) x 3 (R1//R2) (16) where tON(max) is the maximum on-time, which occurs at VIN(min). The next larger standard value capacitor should be used for Cff. R1 and R2 should each be towards the upper end of the 2 k to 10 k range. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 19 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 www.ti.com L1 SW VOUT LM34919C Cff R1 R3 FB R2 C2 Figure 12. Reduced Ripple Configuration b) Minimum ripple configuration: The circuit of Figure 13 provides minimum ripple at VOUT, determined primarily by characteristics of C2 and the inductor's ripple current since R3 is removed. RA and CA are chosen to generate a sawtooth waveform at their junction and that voltage is AC-coupled to the FB pin via CB. To determine the values for RA, CA and CB, use the following procedure: Calculate VA = VOUT - (VSW x (1 - (VOUT/VIN(min)))) (17) where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1 V). VA is the DC voltage at the RA/CA junction. Calculate the RA-CA product in Equation 18. (VIN(min) - VA) x tON RA x CA = (18) 'V where tON is the maximum on-time (at minimum input voltage), and V is the desired ripple amplitude at the RA/CA junction, typically 50 mV. RA and CA are then chosen from standard value components to achieve the above product. Typically CA is 3000 pF to 5000 pF and RA is 10 k to 300 k. CB is then chosen large compared to CA, typically 0.1 F. R1 and R2 should each be towards the upper end of the 2 k to 10 k range. L1 SW VOUT LM34919C RA FB CB CA C2 R1 R2 Figure 13. Minimum Output Ripple Using Ripple Injection c) Alternate minimum ripple configuration: The circuit in Figure 14 is the same as that in Figure 9, except the output voltage is taken from the junction of R3 and C2. The ripple at VOUT is determined by the inductor ripple current and C2's characteristics. R3 slightly degrades the load regulation because the feedback resistors are not directly connected to VOUT. This circuit may be suitable if the load current is fairly constant. L1 SW LM34919C R1 R3 FB VOUT R2 C2 Figure 14. Alternate Minimum Output Ripple Configuration Minimum Load Current 20 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 LM34919C-Q1 www.ti.com SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 The LM34919C requires a minimum load current of 1 mA. If the load current falls below that level, the bootstrap capacitor (C4) may discharge during the long off-time, and the circuit will either shutdown or cycle on and off at a low frequency. If the load current is expected to drop below 1 mA in the application, R1 and R2 should be chosen low enough in value so they provide the minimum required current at nominal VOUT. PC Board Layout Refer to application note AN-1112 for PC board guidelines for the DSBGA package. The LM34919C regulation, overvoltage, and current limit comparators are very fast, and respond to short duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout should be as compact as possible, and all of the components must be as close as possible to their associated pins. The two major current loops have currents which switch very fast, and so these loops should be as small as possible to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW pins, L1, C2, and back to C1.The second current loop is formed by D1, L1, C2 and the SGND and ISEN pins. The power dissipation within the LM34919C can be approximated by determining the total conversion loss (PIN POUT), and then subtracting the power losses in the free-wheeling diode and the inductor. The power loss in the diode is approximately: PD1 = IOUT x VF x (1-D) (19) where IOUT is the load current, VF is the diode's forward voltage drop, and D is the on-time duty cycle. The power loss in the inductor is approximately: PL1 = IOUT2 x RL x 1.1 (20) where RL is the inductor's DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is expected that the internal dissipation of the LM34919C will produce excessive junction temperatures during normal operation, good use of the PC board ground plane can help to dissipate heat. Additionally the use of wide PC board traces, where possible, can help conduct heat away from the device. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) will help reduce the junction temperatures. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 21 LM34919C-Q1 SNVS831A - SEPTEMBER 2013 - REVISED DECEMBER 2013 Changes from Revision splat (September 2013) to Revision A * 22 www.ti.com Page Added value of the integrated high side switch for WSON package .................................................................................... 3 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: LM34919C-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM34919CQSD/NOPB ACTIVE WSON DNT 12 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L34919C LM34919CQSDX/NOPB ACTIVE WSON DNT 12 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L34919C LM34919CQTL/NOPB ACTIVE DSBGA YZR 12 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SL9C LM34919CQTLX/NOPB ACTIVE DSBGA YZR 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SL9C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM34919CQSD/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 4.3 1.3 8.0 12.0 Q1 WSON DNT 12 1000 178.0 12.4 LM34919CQSDX/NOPB WSON DNT 12 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM34919CQTL/NOPB DSBGA YZR 12 250 178.0 8.4 2.03 2.21 0.76 4.0 8.0 Q1 LM34919CQTLX/NOPB DSBGA YZR 12 3000 178.0 8.4 2.03 2.21 0.76 4.0 8.0 Q1 Pack Materials-Page 1 4.3 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 11-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM34919CQSD/NOPB WSON DNT 12 1000 210.0 185.0 35.0 LM34919CQSDX/NOPB WSON DNT 12 4500 367.0 367.0 35.0 LM34919CQTL/NOPB DSBGA YZR 12 250 210.0 185.0 35.0 LM34919CQTLX/NOPB DSBGA YZR 12 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DNT0012B WSON - 0.8mm max height SON (PLASTIC SMALL OUTLINE - NO LEAD) SDA12B (Rev A) 4214928/A 03/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com MECHANICAL DATA YZR0012xxx 0.6000.075 D E TLA12XXX (Rev C) D: Max = 2.055 mm, Min =1.995 mm E: Max = 1.844 mm, Min =1.784 mm 4215049/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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