VIN
SW
BST
LM34919C
VCC
SS
RON
4.5V - 50V
Input
VOUT
RTN
ISEN
SGND
FB
PGD
EN
PGD
VOUT
C1 C5 RON
REN
RPGD
C3
C4 L1
R3
C2
R2
R1
D1
C6
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
LM34919C-Q1 Ultra Small 50V, 600 mA Constant On-Time Buck Switching Regulator
Check for Samples: LM34919C-Q1
1FEATURES APPLICATIONS
2• AEC-Q100 qualified (Tj= -40°C to 125°C) • Automotive Safety and Infotainment
• Maximum Switching Frequency: 2.6 MHz • High Efficiency Point-of-Load (POL) Regulator
• Input Voltage Range: 4.5 V to 50 V • Telecommunication Buck Regulator
• Integrated N-Channel buck switch • Secondary Side Post Regulator
• Integrated Start-Up Regulator DESCRIPTION
• No Loop Compensation Required The LM34919C Step Down Switching Regulator
• Ultra-Fast Transient Response features all of the functions needed to implement a
• Operating Frequency Remains Constant with low-cost, efficient, buck bias regulator capable of
Load Current and Input Voltage supplying 0.6 A to the load. This buck regulator
contains an N-Channel Buck Switch and is available
• Adjustable Output Voltage in DSBGA and WSON packages. The constant on-
• Power Good Output time feedback regulation scheme requires no loop
• Enable Input compensation, results in fast load transient response,
and simplifies circuit implementation. The operating
• Valley Current Limit at 0.64 A Typical frequency remains constant with line and load
• Precision Internal Voltage Reference variations due to the inverse relationship between the
• Low IQShutdown (<10 µA) input voltage and the on-time. The valley current limit
results in a smooth transition from constant voltage to
• Highly Efficient Operation constant current mode when current limit is detected,
• Thermal Shutdown reducing the frequency and output voltage, without
• 12-Bump 2 mm x 2 mm DSBGA and 12-pin 4 the use of foldback. Additional features include:
mm x 4 mm WSON Packages Power Good, enable, VCC undervoltage lockout,
thermal shutdown, gate drive undervoltage lockout,
and maximum duty cycle limiter.
Figure 1. Basic Step Down Regulator
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
VALUE UNIT
VIN, EN , RON to RTN 65 V
BST to RTN 79 V
SW to RTN (Steady State) –1.5 to 65 V
SW to VIN +0.3 V
BST to VCC 65 V
BST to SW 14 V
VCC to RTN 14 V
PGD 14 V
SGND to RTN –0.3 to 0.3 V
SS to RTN –0.3 to 4 V
FB to RTN –0.3 to 7 V
Storage Temperature Range –65 to 150 ºC
ESD Rating HBM 2 kV
Junction Temperature 150 ºC
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the devices at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (1)
VALUE UNIT
VIN 4.5 to 50 V
Junction Temperature −40 to 125 °C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the
device is intended to be fully functional. For verified specifications and test conditions, see Electrical Characteristics.
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Electrical Characteristics
Unless otherwise specified, these specifications apply for –40°C ≤TJ≤+125°C, VIN = 12 V, RON = 100 kΩ. Typical values
represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
EN Power Up Feature (EN Pin)
EN EN Threshold EN rising 2.1 3.0 V
EN Disable Threshold EN falling 0.5 1.3 V
EN Input Current EN = VIN = 12 V 10 50 µA
ISD VIN Shutdown EN = 0 V 1 8 µA
Current
Start-Up Regulator, VCC
VCCReg VCC Regulated Output VIN = 12 V 6.1 7 7.6 V
VIN =4.5 V, ICC = 3 mA 4.43 V
VIN – VCC Dropout ICC = 0 mA, Non-Switching 20 mV
Voltage VCC = UVLOVCC + 250 mV
VCC Output 0 mA ≤ICC ≤5 mA, VIN = 4.5 V 16 Ω
Impedance 0 mA ≤ICC ≤5 mA, VIN = 8 V 8
VCC Current Limit VCC = 0 V 27 mA
UVLOVCC VCC Under-Voltage VCC Increasing 3.4 3.75 4.1
Lockout Threshold V
VCC Decreasing 3.25 3.6 3.95
Measured at VCC
UVLOVCC Hysteresis, 150 mV
at VCC
VCC Under-Voltage VIN Increasing, ICC = 3 mA
Lock-Out Threshold 3.90 4.50
Measured at VIN V
VCC Under-Voltage VIN Decreasing, ICC = 3 mA
Lock-Out Threshold 3.80 4.25
Measured at VIN
UVLOVCC Filter Delay 100 mV Overdrive 3 µs
IQIIN Operating Current Non-Switching, FB = 3 V, SW = Open 2.2 3.8 mA
Switch Characteristics
Rds(on) Buck Switch Rds(on) ITEST = 200 mA 0.35 0.9
(DSBGA) Ω
Buck Switch Rds(on) ITEST = 200 mA 0.45 1
(WSON-12)
UVLOGD Gate Drive UVLO VBST - VSW Increasing 2.40 2.95 3.60 V
VBST - VSW Decreasing 2.82
UVLOGD Hysteresis 130 mV
Soft-start Pin
VSS Pull-Up Voltage 2.52 V
Internal Current VSS = 1V 10.5 µA
Source
Current Limit
ILIM Threshold Current out of ISEN 0.52 0.64 0.76 A
Resistance from ISEN 190 mΩ
to SGND
Response Time 50 ns
On Timer
tON - 1 On-Time VIN = 12 V, RON = 100 kΩ300
tON - 2 On-Time VIN = 24 V, RON = 100 kΩ175 ns
tON - 3 On-Time VIN = 4.5 V, RON = 100 kΩ760
Off Timer
tOFF Minimum Off-time 100 120 150 ns
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Electrical Characteristics (continued)
Unless otherwise specified, these specifications apply for –40°C ≤TJ≤+125°C, VIN = 12 V, RON = 100 kΩ. Typical values
represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
Regulation and Over-Voltage Comparators (FB Pin)
VREF FB Regulation SS pin = Steady State 2.47 2.52 2.57
Threshold V
FB Over-Voltage 3.0
Threshold
FB Bias Current FB = 3 V 1 nA
Power Good Feature (PGD Pin)
PGDUV PGD UV Threshold FB Increasing
Rising, With Respect 87 92 97
to VREF
PGD UV Threshold FB Decreasing 90
Falling %
PGDOV PGD OV Threshold FB Increasing 120
Rising
PGD OV Threshold FB Decreasing 110
Falling
Td, PGD PGD Delay Falling Edge 10 us
IPGD PGD Pulldown Vin = 4.5 V, FB = 3 V, Vpg = 0.1 V 1 mA
Thermal Shutdown
TSD Thermal Shutdown 175
Temperature °C
Thermal Shutdown 20
Hysteresis
Thermal Resistance
θJA Junction to Ambient
0 LFPM Air Flow 61
(DSBGA Packages) °C/W
For WSON Package 50
(Exposed Pad)
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12
11
10
9
1
2
3
4
WSON-12
Exposed
Pad
85
76
VIN
ISEN
EN
SGND
RTN
RON FB
SS
PGD
VCC
BST
SW
RONRTNFB
SGNDPGDSS
ISENVCC
VINSWBST
EN
D3D2D1
B3B1
A3A21A
C3
C1 C 2
B 2
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
PIN DESCRIPTIONS
Figure 2. DSBGA Package Bump View
Figure 3. DSBGA Package Top View
Figure 4. WSON Top View
Pin Descriptions
PIN PIN NUMBER NAME DESCRIPTION APPLICATION INFORMATION
NUMBER (WSON-12)
A1 6 RON On-time control and shutdown An external resistor from VIN to this pin sets the
buck switch on-time.
A2 5 RTN Circuit Ground Ground for all internal circuitry other than the current
limit detection.
A3 7 FB Feedback input from the Internally connected to the regulation and
regulated output overvoltage comparators. The regulation level is
2.52 V (typ.).
B1 4 SGND Sense Ground Re-circulating current flows into this pin to the
current sense resistor.
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Pin Descriptions (continued)
PIN PIN NUMBER NAME DESCRIPTION APPLICATION INFORMATION
NUMBER (WSON-12)
B2 9 PGD Power Good Open drain. Logic output indicates when the voltage
at the FB pin has increased above 92% of the
internal reference. The falling threshold for PGD is
90% of the internal reference. An external pull-up
resistor connecting PGD pin to a voltage less than
14 V is required.
B3 8 SS Soft-start An internal current source charges an external
capacitor to 2.52 V, providing the soft-start function.
C1 2 ISEN Current sense The re-circulating current flows through the internal
sense resistor and out of this pin to the free-
wheeling diode. Valley current limit is nominally set
at 0.64 A.
C2 3 EN Enable Pin Pull low to disable the part for low shutdown current.
Shutdown threshold is 1.3 V (typ).
C3 10 VCC Output from the startup regulator Nominally regulated at 7.0 V. An external voltage (7
V - 14 V) can be applied to this pin to reduce
internal dissipation. An internal diode connects VCC
to VIN.
D1 1 VIN Input supply voltage Nominal input range is 4.5 V to 50 V.
D2 12 SW Switching Node Internally connected to the buck switch source.
Connects to the inductor, free-wheeling diode, and
bootstrap capacitor.
D3 11 BST Boost pin for bootstrap capacitor Connect a 0.022 µF capacitor from SW to this pin.
The capacitor is charged from VCC via an internal
diode during each off-time.
EP (WSON Only) Exposed pad should be connected to RTN pin and
system ground for proper cooling.
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VOUT
FB
VIN VCC
SW
RTN
VIN
BST
2.52V
64 mV
SS
LM34919C
SD
7V SERIES
REGULATOR
+
-
SGND
ISEN
C6
GND RON
RON
REGULATION
COMPARATOR
LEVEL
SHIFT
CURRENT LIMIT
COMPARATOR +
-
VCC
UVLO
ON TIMER
FINISH
START
RON
LOGIC
2.1V
Driver
Gate Drive
UVLO
FINISH
START
OFF TIMER
THERMAL
SHUTDOWN
4.5V to 50V
Input
RSENSE
GND
PGD
RPGD
Power
Good
0.92VREF
C4
L1
C3
C1 C5
R1 R3
R2 C2
D1
100 m
10.5 µA
UNDER-VOLTAGE
COMPARATOR
EN
1.2VREF
OVER-VOLTAGE
COMPARATOR
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Figure 5. Functional Block Diagram
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0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30
VCC (V)
ICC (mA)
Vin = 4.5V
Vin = 12V
C005
Vcc Externally Loaded
Fsw = 2 MHz
0
2
4
6
8
10
7 8 9 10 11 12 13 14
ICC (mA)
APPLIED VCC (V)
C006
Fsw = 2 MHz
65
75
85
95
0.2 0.3 0.4 0.5 0.6
EFFICIENCY (%)
LOAD CURRENT (A)
Vin = 9V
Vin = 12V
Vin = 18V
Vin = 24V
C003
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40 45 50
VCC (V)
INPUT VOLTAGE (V)
C004
60
70
80
90
0.2 0.3 0.4 0.5 0.6
EFFICIENCY (%)
LOAD CURRENT (A)
Vin = 6V
Vin = 9V
Vin = 12V
Vin = 18V
C002
70
75
80
85
90
95
0.2 0.3 0.4 0.5 0.6
EFFICIENCY (%)
LOAD CURRENT (A)
Vin = 4.5V
Vin = 6V
Vin = 9V
Vin = 12V
Vin = 18V
Vin = 24V
C002
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
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Typical Performance Characteristics
Efficiency at 2.1 MHz, VOUT = 3.3 V Efficiency at 250 kHz, VOUT = 3.3 V
Efficiency at 2.1 MHz, VOUT = 5 V VCC vs. VIN
VCC vs. ICC ICC vs. Externally Applied VCC
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2.0
2.5
3.0
3.5
4.0
±50 ±25 0 25 50 75 100 125 150
GATE DRIVE UVLO (V)
JUNCTION TEMPERATURE (|C)
Driver On
Driver Off
C004
2.47
2.48
2.49
2.50
2.51
2.52
2.53
2.54
2.55
2.56
2.57
±50 ±25 0 25 50 75 100 125 150
REFERENCE VOLTAGE (V)
JUNCTION TEMPERATURE (|C)
C007
Vin = 12V
0.00
1.00
2.00
3.00
4.00
5.00
6.00
0 5 10 15 20 25 30 35 40 45 50
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
C002
No Load
FB = 3V
0.00
0.05
0.10
0.15
0.20
0 5 10 15 20 25 30 35 40 45 50
INPUT CURRENT (µA)
INPUT VOLTAGE (V)
C006
EN = 0V
10
100
1000
0 10 20 30 40 50
ON-TIME (ns)
INPUT VOLTAGE (V)
Ron = 100k
Ron = 61.9k
Ron = 35.7K
Ron = 46.4k
C007
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0 10 20 30 40 50
RON PIN VOLTAGE (V)
INPUT VOLTAGE (V)
Ron = 100k
Ron = 61.9k
Ron = 46.4k
C001
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Typical Performance Characteristics (continued)
ON-TIME vs. VIN and RON Voltage at the RON Pin
Operating Current into VIN Shutdown Current into VIN
Gate Drive UVLO vs. Temperature Reference Voltage vs. Temperature
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15
20
25
30
35
40
±50 ±25 0 25 50 75 100 125 150
VCC CURRENT LIMIT (mA)
JUNCTION TEMPERATURE (|C)
C006
Vin = 12V
0
5
10
15
20
25
30
±50 ±25 0 25 50 75 100 125 150
VCC OUTPUT IMPEDANCE (
JUNCTION TEMPERATURE (|C)
Vin = 8V
Vin = 4.5V
C009
3.00
3.25
3.50
3.75
4.00
4.25
4.50
±50 ±25 0 25 50 75 100 125 150
VCC UVLO MEASURED AT VIN (V)
JUNCTION TEMPERATURE (|C)
Vin Increasing
Vin Decreasing
C003
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
±50 ±25 0 25 50 75 100 125 150
VCC (V)
JUNCTION TEMPERATURE (|C)
Vin = 12V
Vin = 4.5V
C005
9.0
9.5
10.0
10.5
11.0
11.5
±50 ±25 0 25 50 75 100 125 150
SOFT-START CURRENT (µA)
JUNCTION TEMPERATURE (|C)
C001
VIN = 12V
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
±50 ±25 0 25 50 75 100 125 150
CURRENT INTO VIN (mA)
JUNCTION TEMPERATURE (|C)
C008
Vin = 12V
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
Typical Performance Characteristics (continued)
Soft-Start Current vs. Temperature Operating Current vs. Temperature
VCC UVLO at Vin vs. Temperature VCC Voltage vs. Temperature
VCC Current Limit vs. Temperature VCC Output Impedence vs. Temperature
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0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 2 4 6 8 10
PGD VOLTAGE (V)
PGD SINK CURRENT (mA)
C005
0.50
0.55
0.60
0.65
0.70
0.75
0.80
±50 ±25 0 25 50 75 100 125 150
CURRENT LIMIT THRESHOLD (A)
JUNCTION TEMPERATURE (|C)
C003
VIN = 12V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
±50 ±25 0 25 50 75 100 125 150
ENABLE THRESHOLD (V)
JUNCTION TEMPERATURE (|C)
EN Rising
EN Falling
C004
100
105
110
115
120
125
130
135
140
145
150
±50 ±25 0 25 50 75 100 125 150
MINIMUM OFF-TIME (ns)
JUNCTION TEMPERATURE (|C)
C007
Vin = 12V
0
100
200
300
400
±50 ±25 0 25 50 75 100 125 150
ON-TIME (ns)
JUNCTION TEMPERATURE (|C)
C002
RON = 100k
VIN = 12V
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Typical Performance Characteristics (continued)
Minimum Off-Time vs. Temperature On-Time vs. Temperature
Current Limit Threshold vs. Temperature EN Pin Threshold vs. Temperature
PGD vs. Sink Current
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VIN
EN
VCC
PGD
SS
SW
VOUT
UVLO
FB
tt1t tt2t
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
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Figure 6. Start-Up Sequence
Functional Description
Device Information
The LM34919C Step Down Switching Regulator features all the functions needed to implement a low cost,
efficient buck bias power converter capable of supplying 600 mA to the load. This high voltage regulator is easy
to implement and is available in DSBGA and WSON packages. The regulator’s operation is based on a constant
on-time control scheme, where the on-time is determined by VIN. This feature allows the operating frequency to
remain relatively constant with load and input voltage variations. The feedback control requires no loop
compensation resulting in fast load transient response. The valley current limit detection circuit, internally set at
0.64 A, holds the buck switch off until the high current level subsides. This scheme protects against excessively
high current if the output is short-circuited when VIN is high.
The LM34919C can be applied in numerous applications to efficiently step down higher voltages. Additional
features include: Thermal shutdown, VCC undervoltage lockout, gate drive undervoltage lockout, maximum duty
cycle limiter, power good, and enable.
Control Circuit Overview
The LM34919C buck DC-DC regulator employs a control scheme based on a comparator and a one-shot on-
timer, with the output voltage feedback (FB) compared to an internal reference (2.52 V). If the FB voltage is
below the reference the N-channel buck switch is turned on for a time period determined by the input voltage and
a programming resistor RON. Following the on-time the switch remains off until the FB voltage falls below the
reference but not less than the minimum off-time. The buck switch then turns on for another on-time period.
Typically, during start-up, or when the load current increases suddenly, the off-times are at the minimum. Once
regulation is established, in steady state operations, the off-times are longer and automatically adjust to produce
the SW pin duty cycle required for output regulation.
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DC = tON
tON + tOFF =VOUT
VIN
OUT
S-12
ON
V
F Hz
R 35.5 10
u u
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
When in regulation, the LM34919C operates in continuous conduction mode at heavy load currents and
discontinuous conduction mode at light load currents. In continuous conduction mode current always flows
through the inductor, never reaching zero during the off-time. In this mode the operating frequency remains
relatively constant with load and line variations. The minimum load current for continuous conduction mode is
one-half the inductor’s ripple current amplitude. The operating frequency is approximately:
(1)
The buck switch duty cycle is approximately equal to:
(2)
In discontinuous conduction mode, current through the inductor ramps up from zero to a peak during the on-time,
then ramps back to zero before the end of the off-time. The next on-time period starts when the voltage at FB
falls below the reference. Until then the inductor current remains zero, and the load current is supplied by the
output capacitor. In this mode the operating frequency is lower than in continuous conduction mode, and varies
with load current. Conversion efficiency is maintained at light loads since the switching losses decrease with the
reduction in load and frequency.
The output voltage is set by two external resistors (R1, R2). The regulated output voltage is calculated as
follows:
VOUT = 2.52 x (R1 + R2) / R2 (3)
Output voltage regulation is based on ripple voltage at the feedback input, normally obtained from the output
voltage ripple through the feedback resistors. The LM34919C requires a minimum of 25 mV of ripple voltage at
the FB pin. In cases where the output capacitor’s ESR is insufficient additional series resistance may be required
(R3).
Start-Up Regulator, VCC
The start-up regulator is integral to the LM34919C. The input pin (VIN) can be connected directly to line voltage
up to 50 V with transient capability to 65 V. The VCC output regulates at 7.0 V and is current limited at 27 mA.
Upon power up, the regulator sources current into the external capacitor at VCC (C3). When the voltage on the
VCC pin reaches the undervoltage lockout rising threshold of 3.75 V, the buck switch is enabled and the soft-
start pin is released to allow the soft-start capacitor (C6) to charge up.
The minimum input voltage is determined by the VCC UVLO falling threshold (≊3.6 V). When VCC falls below the
falling threshold the VCC UVLO activates to shut off the output. If VCC is externally loaded, the minimum input
voltage increases.
To reduce power dissipation in the start-up regulator, an auxiliary bias voltage can be diode connected to the VCC
pin (see Figure 7). Setting the auxiliary bias voltage between 7.6 V and 14 V shuts off the internal regulator
reducing internal power dissipation. The sum of the auxiliary voltage and the input voltage (VCC + VIN) cannot
exceed 79 V. An internal diode connects VCC to VIN. (See Figure 5).
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OUT
ON -12
S
V
RF 35.5 10
:
u u
-12
ON
ON IN
R 35.5 10
T s
V
u u
FB
SW
L1
C2
R1
R2
R3
LM34919C
BST
VCC
D2
C3
C4
D1
ISEN
SGND
VOUT
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
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Figure 7. Self Biased Configuration
Regulation Comparator
The feedback voltage at FB is compared to the voltage at the soft-start pin. In normal operation (the output
voltage is regulated), an on-time period is initiated when the voltage at FB falls below 2.52 V. The buck switch
stays on for the programmed on-time causing the FB voltage to rise above 2.52 V. After the on-time period, the
buck switch stays off until the FB voltage falls below 2.52 V. Input bias current at the FB pin is less than 100 nA
over temperature.
Overvoltage Comparator and Undervoltage Comparator
The voltage at FB is compared to an internal overvoltage comparator reference (120% of internal reference
voltage). If the voltage at FB rises above this reference, the on-time pulse is immediately terminated. This
condition can occur if the input voltage or the output load changes suddenly, or if the inductor (L1) saturates. The
buck switch remains off until the voltage at FB falls below 2.52 V.
When the FB pin voltage rises above the undervoltage comparator voltage reference (92% of the internal
reference voltage), the PGD pin is released and is pulled high by the external pull-up resistor. When the FB pin
voltage measures less than 90% of the internal reference voltage, the PGD pin switches low.
ON-Time Timer
The on-time is determined by the RON resistor and the input voltage (VIN), and is calculated from:
(4)
The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. To set a specific
continuous conduction mode switching frequency (fS), the RON resistor is determined from the following:
(5)
The minimum off-time limits the maximum duty cycle achievable with a low voltage at VIN. The minimum on-time
is limited to ≊90 ns.
Enable
The LM34919C can be remotely shut down by forcing the Enable (EN) pin low. The bias and control circuits are
turned off when EN is pulled below the enable shutdown falling threshold of 1.3 V (typ). In the shutdown mode
the input current falls below 10 µA. If remote shutdown feature is not needed the EN pin can be connected to the
input voltage or any voltage greater than 3 V. In this case the device is enabled and disabled based on the VCC
UVLO threshold.
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0.64A
Load Current
Increases
IPK
IOCL
IO
'I
Normal Operation Current Limited
Inductor Current
LM34919C-Q1
www.ti.com
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Current Limit
Current limit detection occurs during the off-time by monitoring the recirculating current through the free-wheeling
diode (D1). Referring to Figure 5, when the buck switch is turned off the inductor current flows out of ISEN and
through D1. If the valley point of that current exceeds 0.64 A the current limit comparator output switches to
delay the start of the next on-time period. The next on-time starts when the valley point of the current out of ISEN
is below 0.64 A and the voltage at FB is below 2.52 V. If the overload condition persists causing the inductor
current valley point to exceed 0.64 A during each cycle the operating frequency is lower due to longer-than-
normal off-times.
Figure 8 illustrates the inductor current waveform. During normal operation the load current is Io, the average of
the ripple waveform. When the load resistance decreases the current ratchets up until the lower peak reaches
0.64 A. During the Current Limited portion of Figure 8, the current ramps down to 0.64 A during each off-time,
initiating the next on-time (assuming the voltage at FB is <2.52 V). During each on-time the current ramps up an
amount equal to:
ΔI = (VIN - VOUT) x tON / L1 (6)
During this time the LM34919C operates in a constant current mode with an average load current (IOCL) equal to
0.64 A + ΔI/2.
Generally, in applications where the switching frequency is higher than ≊300 kHz and a relatively small value
inductor is used, the higher dl/dt of the inductor's ripple current results in an effectively lower valley current limit
threshold due to the response time of the current limit detection circuit. However, since the small value inductor
results in a relatively high ripple current amplitude (ΔIinFigure 8), the load current (IOCL) at current limit typically
exceeds 640 mA.
Figure 8. Inductor Current - Current Limit Operation
N - Channel Buck Switch and Driver
The LM34919C integrates an N-Channel buck switch and associated floating high side gate driver. The peak
current allowed through the buck switch is 1.5 A, and the maximum allowed average current is 1 A. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A 0.022
µF capacitor (C4) connected between BST and SW provides the voltage to the driver during the on-time. During
each off-time, the SW pin is at approximately -1 V, and C4 charges from VCC through the internal diode. The
minimum off-time of LM34919C ensures sufficient time each cycle to recharge the bootstrap capacitor.
Soft-Start
The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing
start-up stresses and current surges. Upon turn-on, after VCC reaches the undervoltage threshold, an internal
10.5 µA current source charges up the external capacitor at the SS pin to 2.52 V. The ramping voltage at SS
(and the inverting input of the regulation comparator) ramps up the output voltage in a controlled manner.
An internal switch grounds the SS pin if VCC is below the undervoltage lockout threshold, or if the EN pin is
grounded.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15
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LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
Power Good Output
The Power Good Output (PGD) indicates when the voltage at the FB pin is close to the internal 2.52 V reference
voltage. The PGD pin remains low inside the device when the FB pin voltage is outside the range set by the
PGDUV and PGDOV thresholds (see Electrical Characteristics). The PGD pin is internally connected to the drain
of an N-channel MOSFET switch. An external pull-up resistor (RPGD), connected to an appropriate voltage not
exceeding 14 V, is required at PGD to indicate the status of LM34919C to other circuitry. For best results, pull up
the PGD pin to the output voltage. When PGD is low, the voltage at the pin is determined by the current into the
pin. See the graph "PGD Low Voltage vs. Sink Current." Upon powering, as VIN is increased, PGD stays low
until the output voltage takes the voltage at the FB pin above 92% of the internal reference voltage, at which time
PGD switches high. As VIN is decreased (e.g., during shutdown), PGD remains high until the voltage at the FB
pin falls below 90% (typ.) of the internal reference. PGD then switches low and remains low.
Thermal Shutdown
The LM34919C should be operated such that the junction temperature does not exceed 125°C. If the junction
temperature increases to 175°C (typical), an internal Thermal Shutdown circuit forces the controller to a low-
power reset state by disabling the buck switch. This feature helps prevent catastrophic failures from accidental
device overheating. When the junction temperature reduces below 155°C (hysteresis = 20°C) normal operation
resumes.
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Product Folder Links: LM34919C-Q1
R3(min ?) =25mV x (R1+ R2)
R2 x IOR (MI N ?)
= 0.47 3
IOR (MIN ) =kVIN:min ;FVOUT o x ton (max )
L1 = 71.4 mA
L1 = VIN m ax - V OUT x t on ( min )
IOR (MAX ) = 4.76 µH
( )
( )
OUT
ON 12
SW
V
R 61.9k
F x35.5x10
:
LM34919C-Q1
www.ti.com
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
APPLICATION INFORMATION
External Components
The procedure for calculating the external components is illustrated with the following design example. Referring
to Figure 5, the circuit is to be configured for the following specifications:
- VOUT = 3.3 V
- VIN = 4.5 V to 24 V
- Minimum load current = 200 mA
- Maximum load current = 600 mA
- Switching Frequency = 1.5 MHz
- Soft-start time = 5 ms
R1 and R2: These resistors set the output voltage. The ratio of the feedback resistors is calculated from:
R1/R2 = (VOUT/2.52 V) - 1 (7)
For this example, R1/R2 = 0.32. R1 and R2 should be chosen from standard value resistors in the range of 1.0
kΩ- 10 kΩwhich satisfy the above ratio. For this example, 2.49 kΩis chosen for R2 and 787 Ωfor R1.
RON:This resistor sets the on-time and the switching frequency. The switching frequency must be less than 1.53
MHz to ensure the minimum forced on-time does not cause cycle skipping when operating at the maximum input
voltage. The RON resistor is calculated from Equation 8:
(8)
Check that this value resistor does not set an on-time less than 90 ns at maximum VIN.
A standard value 61.9 kΩresistor is used, resulting in a nominal frequency of 1.50 MHz. The minimum on-time is
calculated ≊92 ns at Vin = 24 V, and the maximum on-time is ≊488 ns at Vin = 4.5 V. Alternately, RON can be
determined using Equation 4 if a specific on-time is required.
L1: The main parameter affected by the inductor is the inductor current ripple amplitude (IOR). The minimum load
current is used to determine the maximum allowable ripple in order to maintain continuous conduction mode,
where the lower peak does not reach 0 mA. This is not a requirement of the LM34919C, but serves as a
guideline for selecting L1. For this case the maximum ripple current is:
IOR(MAX) = 2 x IOUT(min) = 400 mA (9)
If the minimum load current is zero, use 20% of IOUT(max) for IOUT(min) in Equation 9. The ripple calculated in
Equation 9 is then used in Equation 10:
(10)
A standard value 8.2 µH inductor is selected. The maximum ripple amplitude, which occurs at maximum VIN,
calculates to 232 mA p-p, and the peak current is 716 mA at maximum load current. Ensure the selected inductor
is rated for this peak current.
C2 and R3: Since the LM34919C requires a minimum of 25 mVp-p ripple at the FB pin for proper operation, the
required ripple at VOUT is increased by R1 and R2. This necessary ripple is created by the inductor ripple current
flowing through R3, and to a lesser extent by the ESR of C2. The minimum inductor ripple current is calculated
using Equation 6, rearranged to solve for IOR at minimum VIN.
(11)
The minimum value for R3 is equal to:
(12)
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM34919C-Q1
FB
SW
LM34919C
BST
VCC
D1
ISEN
RON
VIN
4.5V - 24V
Input
SS
RTN SGND
VOUT
3.3V
C1
2.2 µF
C6
0.022 µF
C5
0.1 µF
RON
61.9 k
C3
0.1 µF
C4
0.022 µF L1
8.2 µH
R3
0.47
C2
22 µF
R1
787
R2
2.49 k
EN
PGD
R4
R5
VOUT
10 k
100 k
C6 =t2 x 10.5 PA
2.5V = 0.021 PF
C1 = IOUT (max) x tON
'V= 0.5 PF
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
A standard value 0.47 Ωresistor is used for R3 to allow for tolerances. C2 should generally be no smaller than
3.3 µF, although that is dependent on the frequency and the desired output characteristics. C2 should be a low
ESR, good quality ceramic capacitor. Experimentation is usually necessary to determine the minimum value for
C2, as the nature of the load may require a larger value. A load which creates significant transients requires a
larger value for C2 than a non-varying load.
C1 and C5: C1’s purpose is to supply most of the switch current during the on-time and limit the voltage ripple at
VIN.
At maximum load current, when the buck switch turns on, the current into VIN suddenly increases to the lower
peak of the inductor’s ripple current, ramps up to the upper peak, then drops to zero at turn-off. The average
current during the on-time is the load current. For a worst case calculation, C1 must supply this average load
current during the maximum on-time, without letting the voltage at VIN drop more than 0.5 V. The minimum value
for C1 is calculated from:
(13)
where tON is the maximum on-time, and ΔV is the allowable ripple voltage. Input ripple of 0.5 V is acceptable in
typical applications. C5’s purpose is to minimize transients and ringing due to long lead inductance leading to the
VIN pin. A low ESR, 0.1 µF ceramic chip capacitor must be located close to the VIN and RTN pins.
C3: The capacitor at the VCC pin provides noise filtering and stability for the Vcc regulator. C3 should be no
smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. C3’s value, and the VCC current
limit, determine a portion of the turn-on-time (t1in (Figure 6).
C4: The recommended value for C4 is 0.022 µF. A high quality ceramic capacitor with low ESR is recommended
as C4 supplies a surge current to charge the buck switch gate at each turn-on. A low ESR also helps ensure a
complete recharge during each off-time.
C6: The capacitor at the SS pin determines the soft-start time, i.e. the time for the output voltage to reach its final
value (t2in Figure 6). The capacitor value is determined from the following:
(14)
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may inadvertently affect the device's operation through external or internal EMI. The
diode should be rated for the maximum input voltage, the maximum load current, and the peak current which
occurs in current limiting. The diode’s average power dissipation is calculated from:
PD1 = VFx IOUT x (1-D) (15)
where VFis the diode forward voltage drop, and D is the duty cycle at the SW pin.
Final Circuit
The final circuit is shown in Figure 9, and its performance is shown in Figure 10 and Figure 11.
Figure 9. Example Circuit
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Product Folder Links: LM34919C-Q1
Cff = tON (max) x 3
(R1//R2)
0.5
1
1.5
2
2.5
3
4 8 12 16 20 24 28
FREQUENCY (MHz)
INPUT VOLTAGE (V)
Ron=61.9k
55
60
65
70
75
80
85
90
95
0.2 0.3 0.4 0.5 0.6
EFFICIENCY (%)
LOAD CURRENT (A)
12V
18V
24V
4.5V
9V
LM34919C-Q1
www.ti.com
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
Figure 10. Efficiency (1.5 MHz, VOUT = 3.3 V)
Figure 11. Frequency vs. VIN (VOUT = 3.3 V)
Low Output Ripple Configurations
For applications where lower ripple at VOUT is required, the following options can be used to reduce or nearly
eliminate the ripple.
a) Reduced ripple configuration: In Figure 12, Cff is added across R1 to AC-couple the ripple at VOUT directly
to the FB pin. This allows the ripple at VOUT to be reduced to a minimum of 25 mVp-p by reducing R3, since the
ripple at VOUT is not attenuated by the feedback resistors. The minimum value for Cff is determined from:
(16)
where tON(max) is the maximum on-time, which occurs at VIN(min). The next larger standard value capacitor should
be used for Cff. R1 and R2 should each be towards the upper end of the 2 kΩto 10 kΩrange.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM34919C-Q1
FB
SW
L1
R1
LM34919C
R2
R3
C2
VOUT
SW
FB
LM34919C
L1
R1
R2
C2
CB
CA
RA
VOUT
RA x CA = (VIN(min) - VA) x tON
'V
FB
SW
L1
LM34919C Cff R1 R3
R2 C2
VOUT
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
Figure 12. Reduced Ripple Configuration
b) Minimum ripple configuration: The circuit of Figure 13 provides minimum ripple at VOUT, determined
primarily by characteristics of C2 and the inductor’s ripple current since R3 is removed. RA and CA are chosen to
generate a sawtooth waveform at their junction and that voltage is AC-coupled to the FB pin via CB. To
determine the values for RA, CA and CB, use the following procedure:
Calculate VA= VOUT - (VSW x (1 - (VOUT/VIN(min)))) (17)
where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1 V). VAis the DC
voltage at the RA/CA junction. Calculate the RA-CA product in Equation 18.
(18)
where tON is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
RA/CA junction, typically 50 mV. RA and CA are then chosen from standard value components to achieve the
above product. Typically CA is 3000 pF to 5000 pF and RA is 10 kΩto 300 kΩ. CB is then chosen large
compared to CA, typically 0.1 µF. R1 and R2 should each be towards the upper end of the 2 kΩto 10 kΩrange.
Figure 13. Minimum Output Ripple Using Ripple Injection
c) Alternate minimum ripple configuration: The circuit in Figure 14 is the same as that in Figure 9, except the
output voltage is taken from the junction of R3 and C2. The ripple at VOUT is determined by the inductor ripple
current and C2’s characteristics. R3 slightly degrades the load regulation because the feedback resistors are not
directly connected to VOUT. This circuit may be suitable if the load current is fairly constant.
Figure 14. Alternate Minimum Output Ripple Configuration
Minimum Load Current
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Product Folder Links: LM34919C-Q1
LM34919C-Q1
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SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
The LM34919C requires a minimum load current of 1 mA. If the load current falls below that level, the bootstrap
capacitor (C4) may discharge during the long off-time, and the circuit will either shutdown or cycle on and off at a
low frequency. If the load current is expected to drop below 1 mA in the application, R1 and R2 should be
chosen low enough in value so they provide the minimum required current at nominal VOUT.
PC Board Layout
Refer to application note AN-1112 for PC board guidelines for the DSBGA package.
The LM34919C regulation, overvoltage, and current limit comparators are very fast, and respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout should
be as compact as possible, and all of the components must be as close as possible to their associated pins. The
two major current loops have currents which switch very fast, and so these loops should be as small as possible
to minimize conducted and radiated EMI. The first loop is that formed by C1, through the VIN to SW pins, L1, C2,
and back to C1.The second current loop is formed by D1, L1, C2 and the SGND and ISEN pins.
The power dissipation within the LM34919C can be approximated by determining the total conversion loss (PIN -
POUT), and then subtracting the power losses in the free-wheeling diode and the inductor. The power loss in the
diode is approximately:
PD1 = IOUT x VFx (1-D) (19)
where IOUT is the load current, VFis the diode’s forward voltage drop, and D is the on-time duty cycle. The power
loss in the inductor is approximately:
PL1 = IOUT2x RLx 1.1 (20)
where RLis the inductor’s DC resistance, and the 1.1 factor is an approximation for the AC losses. If it is
expected that the internal dissipation of the LM34919C will produce excessive junction temperatures during
normal operation, good use of the PC board ground plane can help to dissipate heat. Additionally the use of wide
PC board traces, where possible, can help conduct heat away from the device. Judicious positioning of the PC
board within the end product, along with the use of any available air flow (forced or natural convection) will help
reduce the junction temperatures.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM34919C-Q1
LM34919C-Q1
SNVS831A –SEPTEMBER 2013–REVISED DECEMBER 2013
www.ti.com
Changes from Revision splat (September 2013) to Revision A Page
• Added value of the integrated high side switch for WSON package .................................................................................... 3
22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LM34919C-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Dec-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM34919CQSD/NOPB ACTIVE WSON DNT 12 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L34919C
LM34919CQSDX/NOPB ACTIVE WSON DNT 12 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L34919C
LM34919CQTL/NOPB ACTIVE DSBGA YZR 12 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SL9C
LM34919CQTLX/NOPB ACTIVE DSBGA YZR 12 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 SL9C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Dec-2013
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM34919CQSD/NOPB WSON DNT 12 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM34919CQSDX/NOPB WSON DNT 12 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM34919CQTL/NOPB DSBGA YZR 12 250 178.0 8.4 2.03 2.21 0.76 4.0 8.0 Q1
LM34919CQTLX/NOPB DSBGA YZR 12 3000 178.0 8.4 2.03 2.21 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Dec-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM34919CQSD/NOPB WSON DNT 12 1000 210.0 185.0 35.0
LM34919CQSDX/NOPB WSON DNT 12 4500 367.0 367.0 35.0
LM34919CQTL/NOPB DSBGA YZR 12 250 210.0 185.0 35.0
LM34919CQTLX/NOPB DSBGA YZR 12 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Dec-2013
Pack Materials-Page 2
DNT0012B WSON - 0.8mm max height
SON (PLASTIC SMALL OUTLINE - NO LEAD)
www.ti.com
MECHANICAL DATA
4214928/A 03/2013
SDA12B (Rev A)
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance.
For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
NOTES:
MECHANICAL DATA
YZR0012xxx
www.ti.com
TLA12XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215049/A 12/12
NOTES:
D: Max =
E: Max =
2.055 mm, Min =
1.844 mm, Min =
1.995 mm
1.784 mm
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