TPS51100DGQ - Texas Instruments

VIN

GND

VDDQSNS

VLDOIN

PGND

VTT

TPS51100DGQ

0.1 µF

5 6VTTREFVTTSNS

2 x 10 µF

VTTREF

5V_IN

Capacitor

Manuf

TDK

Part Number

C2012JB0J106K

C1608JB1H104K

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

3-A SINK/SOURCE DDR TERMINATION REGULATOR

Check for Samples: TPS51100

1FEATURES The TPS51100 is a 3-A sink/source tracking

2• Input Voltage Range: 4.75 V to 5.25 V termination regulator. It is specifically designed for

• VLDOIN Voltage Range: 1.2 V to 3.6 V low-cost/low-external component count systems,

where space is a premium.

• 3-A Sink/Source Termination Regulator

Includes Droop Compensation The TPS51100 maintains fast transient response,

• Requires Only 20-μF Ceramic Output only requiring 20 μF (2 × 10 μF) of ceramic output

capacitance. The TPS51100 supports remote sensing

Capacitance functions and all features required to power the DDR

• Supports High-Z in S3 and Soft-Off in S5 and DDR2 VTT bus termination according to the

• 1.2-V Input (VLDOIN) Helps Reduce Total JEDEC specification. The part also supports DDR3

Power Dissipation VTT termination with VDDQ at 1.5 V (typ). In addition,

the TPS51100 includes integrated sleep-state

• Integrated Divider Tracks 0.5 VDDQSNS for controls, placing VTT in high-Z in S3 (suspend to

VTT and VTTREF RAM) and soft-off for VTT and VTTREF in S5

• Remote Sensing (VTTSNS) (suspend to disk). The TPS51100 is available in the

• ±20-mV Accuracy for VTT and VTTREF thermally efficient 10-pin MSOP PowerPAD™

package and is specified from –40°C to 85°C.

• 10-mA Buffered Reference (VTTREF)

• Built-In Soft-Start, UVLO and OCL ORDERING INFORMATION

• Thermal Shutdown PLASTIC MSOP PowerPAD™

• Supports JEDEC Specifications PACKAGE (DGQ)(1)

–40°C to 85°C TPS51100DGQ

APPLICATIONS

• DDR, DDR2, DDR3 Memory Termination

• SSTL-2, SSTL-18 and HSTL Termination (1) The DGQ package is also available taped and reeled. Add an

R suffix to the device type (i.e., TPS51100DGQR). See the

application section of the data sheet for the PowerPAD

package drawing and layout information.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

VALUE UNIT

VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5 –0.3 to 6

Input voltage range(2) V

PGND –0.3 to 0.3

Output voltage range(2) VTT, VTTREF –0.3 to 6 V

TAOperating ambient temperature range –40 to 85 °C

Tstg Storage temperature –55 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.c

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

THERMAL INFORMATION TPS51100

THERMAL METRIC(1) UNITS

DGQ

10 PINS

θJA Junction-to-ambient thermal resistance 60.3

θJCtop Junction-to-case (top) thermal resistance 63.5

θJB Junction-to-board thermal resistance 51.6 °C/W

ψJT Junction-to-top characterization parameter 1.5

ψJB Junction-to-board characterization parameter 22.3

θJCbot Junction-to-case (bottom) thermal resistance 9.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

VIN Supply voltage 4.75 5.25 V

S3, S5 –0.10 5.25

VLDOIN, VDDQSNS, VTT, VTTSNS –0.1 3.6

Voltage range V

VTTREF –0.1 1.8

PGND –0.1 0.1

TAOperating free-air temperature –40 85 °C

Product Folder Link(s) :TPS51100

VDDQSNS

TT A

V 1.25 V, T = 25 C

æ ö

= ´ °

ç ÷

è ø

VDDQSNS

TT A

V 1.25 V, T = 25 C

æ ö

= ´ °

ç ÷

è ø

VDDQSNS

V 1.05, PGOOD = High

æ ö

= ´

ç ÷

è ø

VDDQSNS

V 0.95, PGOOD = High

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= ´

ç ÷

è ø

TPS51100

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SLUS600D –APRIL 2004–REVISED MAY 2012

ELECTRICAL CHARACTERISTICS

TA= –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

IVIN Supply current, VIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V 0.25 0.5 1 mA

IVINSTB Standby currrent, VIN TA= 25°C, VVIN = 5 V, no load, VS3 = 0 V, VS5 = 5 V 25 50 80 μA

TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V, VVLDOIN

IVINSDN Shutdown current, VIN 0.3 1 μA

= VVDDQSNS = 0 V

IVLDOIN Supply current, VLDOIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 5 V 0.7 1.2 2 mA

IVLDOINSTB Standby currrent, VLDOIN TA= 25°C, VVIN = 5 V, no load,VS3 = 0 V, VS5 = 5 V 6 10 μA

IVLDOINSDN Shutdown current, VLDOIN TA= 25°C, VVIN = 5 V, no load, VS3 = VS5 = 0 V 0.3 1 μA

INPUT CURRENT

IVDDQSNS Input current, VDDQSNS VVIN = 5 V, VS3 = VS5 = 5 V 1 3 5 μA

IVTTSNS Input current, VTTSNS VVIN = 5 V, VS3 = VS5 = 5 V –1 –0.25 1 μA

VTT OUTPUT

VVLDOIN = VVDDQSNS = 2.5 V 1.25

VVTTSNS Output voltage, VTT VVLDOIN = VVDDQSNS = 1.8 V 0.9 V

VVLDOIN = VVDDQSNS = 1.5 V 0.75

VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 0 A –20 20

VVTTTOL25 VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 1.5 A –30 30

VVLDOIN = VVDDQSNS = 2.5 V, |IVTT| = 3 A –40 40

VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 0 A –20 20

Output votlage tolerance to VTTREF, VTT mV

VVTTTOL18 VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 1 A –30 30

VVLDOIN = VVDDQSNS = 1.8 V, |IVTT| = 2 A –40 40

VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 0 A –20 20

VVTTTOL15 VVLDOIN = VVDDQSNS = 1.5 V, |IVTT| = 1 A –30 30

3 3.8 6

IVTTOCLSRC Source current limit, VTT A

VVTT = 0 V 1.5 2.2 3

3 3.6 6

IVTTOCLSNK Sink current limit, VTT A

VVTT = VVDDQ 1.5 2.2 3

IVTTLK Leakage current, VTT –1 0.5 10 μA

VS3 = 0 V, VS5 = 5 V

IVTTSNSLK Leakage current, VTTSNS –1 0.01 1 μA

TA= 25°C, VS3 = VS5 = 0 V,

IDSCHRG Discharge current, VTT 10 17 mA

VVDDQSNS = 0 V, VVTT = 0.5 V

VTTREF OUTPUT

VVTTREF Output voltage, VTTREF V

VVTTREFTOL25 VVLDOIN = VVDDQSNS = 2.5 V, IVTTREF < 10 mA –20 20

Output voltage tolerance to VDDQSNS/2,

VVTTREFTOL18 VVLDOIN = VVDDQSNS = 1.8 V, IVTTREF < 10 mA –17 17 mV

VTTREF

VVTTREFTOL15 VVLDOIN = VVDDQSNS = 1.5 V, IVTTREF < 10 mA –15 15

IVTTREFOCL Source current limit, VTTREF VVTTREF = 0 V 10 20 30 mA

Product Folder Link(s) :TPS51100

ActualSize

3,05mmx4,98mm

VDDQSNS

VLDOIN

VTT

PGND

VTTSNS

VIN

GND

VTTREF

DGQPackage

(TopView)

P0083-01

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

TA= –40°C to 85°C, VVIN = 5 V, VLDOIN and VDDQSNS are connected to 2.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UVLO/LOGIC THRESHOLD

Wake up 3.4 3.7 4

VVINUV UVLO threshold voltage, VIN V

Hysteresis 0.15 0.25 0.35

VIH High-level input voltage S3, S5 1.6 V

VIL Low-level input voltage S3, S5 0.3 V

VIHYST Hysteresis voltage S3, S5 0.2 V

IILEAK Logic input leakage current S2, S5, TA= 25°C –1 1 μA

THERMAL SHUTDOWN

Shutdown temperature 160

TSDN Thermal shutdown threshold °C

Hysteresis 10

DEVICE INFORMATION

NOTE: For more information on the DGQ package, see the PowerPAD Thermally Enhanced Package application report

(SLMA002).

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

GND 8 – Signal ground. Connect to negative terminal of the output capacitor

PGND 4 – Power ground output for the VTT LDO

S3 7 I S3 signal input

S5 9 I S5 signal input

VDDQSNS 1 I VDDQ sense input

VIN 10 I 5-V power supply

VLDOIN 2 I Power supply for the VTT LDO and VTTREF output stage

VTT 3 O Power output for the VTT LDO

VTTREF 6 O VTT reference output. Connect to GND through 0.1-μF ceramic capacitor.

VTTSNS 5 I Voltage sense input for the VTT LDO. Connect to plus terminal of the output capacitor.

Product Folder Link(s) :TPS51100

B0319-01

VIN

GND

VDDQSNS VLDOIN

PGND

VTT

TPS51100DGQ

VTTREF

VTTSNS

ENVTT

3.7V/3.5V

HalfDDQ

VinOK

5V/10%

–5V/10%

PGOOD

ENREF

ENVTT

ENREF

–

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

SIMPLIFIED BLOCK DIAGRAM

Product Folder Link(s) :TPS51100

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

DETAILED DESCRIPTION

VTT SINK/SOURCE REGULATOR

The TPS51100 is a 3-A sink/source tracking termination regulator designed specially for low-cost, low-external-

components systems where space is at premium, such as notebook PC applications. The TPS51100 integrates a

high-performance, low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This

VTT linear regulator employs an ultimate fast-response feedback loop so that small ceramic capacitors are

enough to keep tracking to the VTTREF within ±40 mV under all conditions, including fast load transient. To

achieve tight regulation with minimum effect of trace resistance, a remote sensing terminal, VTTSNS, should be

connected to the positive node of the VTT output capacitor(s) as a separate trace from the high-current line from

VTT.

VTTREF Regulator

The VTTREF block consists of an on-chip 1/2 divider, low-pass filter (LPF), and buffer. This regulator can source

current up to 10 mA. Bypass VTTREF to GND using a 0.1-μF ceramic capacitor to ensure stable operation.

Soft-Start

The soft-start function of the VTT is achieved via a current clamp, allowing the output capacitors to be charged

with low and constant current that gives linear ramp-up of the output voltage. The current-limit threshold is

changed in two stages using an internal powergood signal. When VTT is outside the powergood threshold, the

current limit level is 2.2 A. When VTT rises above (VTTREF – 5%) or falls below (VTTREF + 5%), the current

limit level switches to 3.8 A. The thresholds are typically VTTREF ±5% (from outside regulation to inside) and

±10% (when it falls outside). The soft-start function is completely symmetrical, and it works not only from GND to

VTTREF voltage, but also from VDDQ to VTTREF voltage. Note that the VTT output is in a high-impedance state

during the S3 state (S3 = low, S5 = high), and its voltage can be up to VDDQ voltage, depending on the external

condition. Note that VTT does not start under a full-load condition.

S5 Control and Soft-Off

The S3 and S5 terminals should be connected to SLP_S3 and SLP_S5 signals, respectively. Both VTTREF and

VTT are turned on at the S0 state (S3 = high, S5 = high). VTTREF is kept alive while VTT is turned off and left

high-impedance in the S3 state (S3 = low, S5 = high). Both VTT and VTTREF outputs are turned off and

discharged to ground through internal MOSFETs during S4/S5 state (both S3 and S5 are low).

Table 1. S3 and S5 Control Tabl

STATE S3 S5 VTTREF VTT

S0 H H 1 1

S3(1) L H 1 0 (high-Z)

S4/S5(1) L L 0 (discharge) 0 (discharge)

(1) In case S3 is forced to H and S5 to L, VTTREF is discharged and VTT is at High-Z state. This

condition is NOT recommended.

VTT Current Protection

The LDO has a constant overcurrent limit (OCL) at 3.8 A. This trip point is reduced to 2.2 A before the output

voltage comes within ±5% of the target voltage or goes outside of ±10% of the target voltage.

VIN UVLO Protection

For VIN undervoltage lockout (UVLO) protection, the TPS51100 monitors VIN voltage. When the VIN voltage is

lower than UVLO threshold voltage, the VTT regulator is shut off. This is a non-latch protection.

Thermal Shutdown

TPS51100 monitors its temperature. If the temperature exceeds the threshold value, typically 160°C, the VTT

and VTTREF regulators are shut off. This is also a non-latch protection.

Product Folder Link(s) :TPS51100

( )

J(max) A(max)

PKG

T T

W-

DSNK VTT VTT

W V I= ´

( )

DSRC VLDOIN VTT VTT

W V V I= - ´

OUT VTT

VTTOCL

C V

æ ö

=ç ÷

è ø

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

Output Capacitor

For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. Attach

two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If the ESR is greater than 2 mΩ,

insert an R-C filter between the output and the VTTSNS input to achieve loop stability. The R-C filter time

constant should be almost the same or slightly lower than the time constant of the output capacitor and its ESR.

Soft-start duration, tSS, is also a function of this output capacitance. Where ITTOCL = 2.2 A (typ), tSS can be

calculated as,

(1)

Input Capacitor

Depending on the trace impedance between the VLDOIN bulk power supply to the part, transient increase of

source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-μF (or more) ceramic

capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at

VTT. In general, use 1/2 COUT for the input.

VIN Capacitor

Add a ceramic capacitor with a value between 1 μF and 4.7 μF placed close to the VIN pin, to stabilize 5 V from

any parasitic impedance from the supply.

Thermal Design

As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generates power

dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT times VTT

current becomes the power dissipation, WDSRC.

(2)

In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be

decreased.

For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and

WDSNK, is calculated by:

(3)

Because the device does not sink and source the current at the same time and IVTT varies rapidly with time, the

actual power dissipation that must be considered for thermal design is an average over the thermal relaxation

duration of the system. Another power consumption is the current used for internal control circuitry from the VIN

supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This

power must be effectively dissipated from the package. Maximum power dissipation allowed to the package is

calculated by,

(4)

where

TJ(max) is 125°C

TA(max) is the maximum ambient temperature in the system

θJA is the thermal resistance from the silicon junction to the ambient

This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced

PowerPAD package that has an exposed die pad underneath the body. For improved thermal performance, this

die pad must be attached to the ground trace via thermal land on the PCB. This ground trace acts as a heat

sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with

two vias without air flow. It can be improved by using larger thermal land and/or increasing the number of vias.

For example, assuming a 3 mm × 3 mm thermal land with four vias without air flow, it is 45.4°C/W. Further

information about the PowerPAD package and its recommended board layout is described in the PowerPAD

Thermally Enhanced Package application report (SLMA002). This document is available at www.ti.com.

Product Folder Link(s) :TPS51100

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

LAYOUT CONSIDERATIONS

Consider the following points before the layout of TPS51100 design begins.

• The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with a short and

wide connection.

• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the

high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to

sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of the ground trace between the GND

pin and the output capacitor(s).

• Consider adding an LPF at VTTSNS in case the ESR of the VTT output capacitor(s) is larger than 2 mΩ.

• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference

voltage of VTTREF. Avoid any noise generative lines.

• The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together,

avoiding common impedance to the high-current path of the VTT source/sink current.

• The GND (signal GND) pin node represents the reference potential for the VTTREF and VTT outputs.

Connect GND to the negative nodes of the VTT capacitor(s), VTTREF capacitor, and VDDQ capacitor(s) with

care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single

point connection between them.

• In order to remove heat from the package effectively, prepare the thermal land and solder to the package

thermal pad. The wide trace of the component-side copper, connected to this thermal land, helps heat

spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder-side

ground plane(s) should be used to help dissipation.

NOTES: 1. The positive terminal of each output capacitor should be directly connected to VTT of the IC; do not use a VIA.

2. The negative terminal of each output capacitor should be directly connected to GND of the IC; do not use a VIA.

3. VIAs

VIA between 1st and 2nd layers

VIA between 1st and other layers under 2nd

4. Rs and Cs with dotted outlines are options.

Figure 1. TPS51100 PCB Layout Guideline

Product Folder Link(s) :TPS51100

IVTT − VTT Load Current − A

−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0

IVIN − VIN Supply Current − mA

G003

DDR2

VVTT = 1.8 V

TJ − Junction Temperature − °C

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

−50 0 50 100 150

IVLDOIN − VLDOIN Supply Current − mA

G004

TJ − Junction Temperature − °C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

−50 0 50 100 150

IVIN − VIN Supply Current − mA

G001

TJ − Junction Temperature − °C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

−50 0 50 100 150

IVINSDN − VINSDN Supply Current − µA

G002

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

TYPICAL CHARACTERISTICS

VIN SUPPLY CURRENT VIN SHUTDOWN CURRENT

vs vs

TEMPERATURE TEMPERATURE

Figure 2. Figure 3.

VIN SUPPLY CURRENT VLDOIN SUPPLY CURRENT

vs vs

VTT LOAD CURRENT TEMPERATURE

Figure 4. Figure 5.

Product Folder Link(s) :TPS51100

IVTT − VTT Load Current − A

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

−4 −3 −2 −1 0 1 2 3 4

VVTT − VTT Voltage − V

G007

VVLDOIN = 2.5 V

VVLDOIN = 1.8 V

IVTT − VTT Load Current − A

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

−4 −3 −2 −1 0 1 2 3 4

VVTT − VTT Voltage − V

G008

VVLDOIN = 1.8 V

VVLDOIN = 1.5 V

VVLDOIN = 1.2 V

TJ − Junction Temperature − °C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

−50 0 50 100 150

IVLDOINSDN − VLDOINSDN Supply Current − µA

G005

TJ − Junction Temperature − °C

−50 0 50 100 150

IDSCHRG − VTT Discharge Current − mA

G006

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

VLDOIN SHUTDOWN CURRENT DISCHARGE CURRENT

vs vs

TEMPERATURE TEMPERATURE

Figure 6. Figure 7.

VTT VOLTAGE LOAD REGULATION VTT VOLTAGE LOAD REGULATION

vs vs

VTT LOAD CURRENT (DDR) VTT LOAD CURRENT (DDR2)

Figure 8. Figure 9.

Product Folder Link(s) :TPS51100

IVTTREF − VTTREF Load Current − mA

898

899

900

901

902

0 2 4 6 8 10

VVTTREF − VTTREF Voltage − mV

G011

IVTTREF − VTTREF Load Current − mA

748

749

750

751

752

0 2 4 6 8 10

VVTTREF − VTTREF Voltage − mV

G012

VVLDOIN = 1.5 V

IVTTREF − VTTREF Load Current − mA

1.248

1.249

1.250

1.251

1.252

0 2 4 6 8 10

VVTTREF − VTTREF Voltage − V

G010

IVTT − VTT Load Current − A

0.71

0.72

0.73

0.74

0.75

0.76

0.77

0.78

0.79

−3 −2 −1 0 1 2 3

VVTT − VTT Voltage − V

G009

VVLDOIN = 1.5 V

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

TYPICAL CHARACTERISTICS (continued)

VTT VOLTAGE LOAD REGULATION VTTREF VOLTAGE LOAD REGULATION

vs vs

VTT LOAD CURRENT (DDR3) VTTREF LOAD CURRENT (DDR)

Figure 10. Figure 11.

VTTREF VOLTAGE LOAD REGULATION VTTREF VOLTAGE LOAD REGULATION

vs vs

VTTREF LOAD CURRENT (DDR2) VTTREF LOAD CURRENT (DDR3)

Figure 12. Figure 13.

Product Folder Link(s) :TPS51100

G015

t − Time − 10 µs/div

VVTT

(0.5 V/div)

VS3

(5 V/div)

VS5

(5 V/div)

VS5 = 5 V

IVTT = IVTTREF = 0 A

VTTREF

G016

t − Time − 1 ms/div

VVTTREF

(0.5 V/div)

VVTT

(0.5 V/div)

VS5

(5 V/div)

VS3

(5 V/div)

VS5 = 5 V

IVTT = IVTTREF = 0 A

G014

t − Time − 10 µs/div

VVTTREF

(0.5 V/div)

VS3

(5 V/div)

VS5

(5 V/div)

VVTT (0.5 V/div)

VS3 = 0 V

IVTT = IVTTREF = 0 A

G013

t − Time − 20 µs/div

VVTT (20 mV/div)

Offset 0.9 V

VVTTREF

(20 mV/div)

Offset 0.9 V

IVTT

(2 A/div)

VVLDOIN (50 mV/div)

Offset: 1.8 V

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

VTT VOLTAGE LOAD STARTUP WAVEFORMS

TRANSIENT RESPONSE S5 LOW-TO-HIGH

Figure 14. Figure 15.

STARTUP WAVEFORMS SHUTDOWN WAVEFORMS

S3 LOW-TO-HIGH S3 HIGH-TO-LOW

Figure 16. Figure 17.

Product Folder Link(s) :TPS51100

f − Frequency − Hz

−40

−20

Gain − dB

Phase − °

10k 100k 1M 10M

180

135

−45

−90

G019

C1 = 2 × 10 µF

Phase

(1 A)

Phase

(0.1 A)

Gain

(1 A)

Gain

(0.1 A)

f − Frequency − Hz

−40

−20

Gain − dB

Phase − °

10k 100k 1M 10M

180

135

−45

−90

G020

C1 = 2 × 10 µF

Phase

(−1 A)

Phase

(−0.1 A)

Gain

(−1 A)

Gain

(−0.1 A)

G017

t − Time − 1 ms/div

VS5

(5 V/div)

VS3

(5 V/div)

VVTT

(0.5 V/div)

IVTT = IVTTREF = 0 A

VTTREF

(0.5 V/div)

f − Frequency − Hz

−40

−20

Gain − dB

Phase − °

10k 100k 1M 10M

180

135

−45

−90

G018

Phase

(−1 A)

Phase

(−0.1 A)

Gain

(−1 A)

Gain

(−0.1 A)

C1 = 2 × 10 µF

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

TYPICAL CHARACTERISTICS (continued)

SHUTDOWN WAVEFORMS

S3 AND S5 HIGH-TO-LOW BODE PLOT DDR SOURCE

Figure 18. Figure 19.

BODE PLOT DDR SINK BODE PLOT DDR2 SOURCE

Figure 20. Figure 21.

Product Folder Link(s) :TPS51100

f − Frequency − Hz

−40

−20

Gain − dB

Phase − °

10k 100k 1M 10M

180

135

−45

−90

G021

C1 = 2 × 10 µF

Phase

(1 A)

Phase

(0.1 A)

Gain

(1 A)

Gain

(0.1 A)

TPS51100

SLUS600D –APRIL 2004–REVISED MAY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

BODE PLOT DDR2 SINK

Figure 22.

Product Folder Link(s) :TPS51100

TPS51100

www.ti.com

SLUS600D –APRIL 2004–REVISED MAY 2012

Changes from Revision C (JUNE 2008) to Revision D Page

• Added updated Thermal data ............................................................................................................................................... 2

Product Folder Link(s) :TPS51100

PACKAGE OPTION ADDENDUM

www.ti.com 9-May-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS51100DGQ ACTIVE MSOP-

PowerPAD DGQ 10 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TPS51100DGQG4 ACTIVE MSOP-

PowerPAD DGQ 10 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TPS51100DGQR ACTIVE MSOP-

PowerPAD DGQ 10 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TPS51100DGQRG4 ACTIVE MSOP-

PowerPAD DGQ 10 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS51100DGQR MSOP-

Power

PAD

DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51100DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-May-2012

Pack Materials-Page 2

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