DS1250Y/AB
4096K Nonvolatile SRAM
DS1250Y/AB
042398 1/11
FEATURES
•10 years minimum data retention in the absence of
external power
•Data is automatically protected during power loss
•Replaces 512K x 8 volatile static RAM, EEPROM or
Flash memory
•Unlimited write cycles
•Low–power CMOS
•Read and write access times as fast as 70 ns
•Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
•Full ±10% VCC operating range (DS1250Y)
•Optional ±5% VCC operating range (DS1250AB)
•Optional industrial temperature range of –40°C to
+85°C, designated IND
•JEDEC standard 32–pin DIP package
•New PowerCap Module (PCM) package
– Directly surface–mountable module
– Replaceable snap–on PowerCap provides lith-
ium backup battery
– Standardized pinout for all nonvolatile SRAM
products
– Detachment feature on PCM allows easy
removal using a regular screwdriver
PIN ASSIGNMENT
32–PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
CE
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
34
33
32
31
30
29
28
27
26
25
24
23
22
14
15
16
17
21
20
19
18
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
A15
A16
NC
GND VBAT
34–PIN POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0 – A18 – Address Inputs
DQ0 – DQ7 – Data In/Data Out
CE – Chip Enable
WE – Write Enable
OE – Output Enable
VCC – Power (+5V)
GND – Ground
NC – No Charge
DS1250Y/AB
042398 2/11
DESCRIPTION
The DS1250 4096K Nonvolatile SRAMs are
4,194,304–bit, fully static, nonvolatile SRAMs orga-
nized as 524,288 words by 8 bits. Each complete NV
SRAM has a self–contained lithium energy source and
control circuitry which constantly monitors VCC for an
out–of–tolerance condition. When such a condition oc-
curs, the lithium energy source is automatically
switched on and write protection is unconditionally en-
abled to prevent data corruption. DIP–package
DS1250 devices can be used in place of existing 512K x
8 static RAMs directly conforming to the popular byte-
wide 32–pin DIP standard. DS1250 devices in the Pow-
erCap Module package are directly surface mountable
and are normally paired with a DS9034PC PowerCap to
form a complete Nonvolatile SRAM module. There is no
limit on the number of write cycles that can be executed
and no additional support circuitry is required for micro-
processor interfacing.
READ MODE
The DS1250 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 19 address inputs (A0 –
A18) defines which of the 524,288 bytes of data is to be
accessed. V alid data will be available to the eight data
output drivers within tACC (Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either tCO for CE or tOE
for OE rather than address access.
WRITE MODE
The DS1250 devices execute a write cycle whenever
the WE and CE signals are active (low) after address in-
puts are stable. The later occurring falling edge of CE or
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (tWR) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However , if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in tODW from its
falling edge.
DATA RETENTION MODE
The DS1250AB provides full functional capability for
VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1250Y provides full functional capabil-
ity for VCC greater than 4.5 volts and write protects by
4.25 volts. Data is maintained in the absence of VCC
without any additional support circuitry . The nonvolatile
static RAMs constantly monitor VCC. Should the supply
voltage decay, the NV SRAMs automatically write pro-
tect themselves, all inputs become “don’t care,” and all
outputs become high impedance. As VCC falls below
approximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when VCC rises above approximately
3.0 volts, the power switching circuit connects external
VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds
4.75 volts for the DS1250AB and 4.5 volts for the
DS1250Y.
FRESHNESS SEAL
Each DS1250 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first
applied at a level greater than 4.25 volts, the lithium en-
ergy source is enabled for battery back–up operation.
PACKAGES
The DS1250 devices are available in two packages:
32–pin DIP and 34–pin PowerCap Module (PCM). The
32–pin DIP integrates a lithium battery, an SRAM
memory and a nonvolatile control function into a single
package with a JEDEC–standard 600 mil DIP pinout.
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC Pow-
erCap. The PowerCap Module package design allows
a DS1250 PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1250 PCM is
reflow soldered, a DS9034PC PowerCap is snapped on
top of the PCM to form a complete Nonvolatile SRAM
module. The DS9034PC is keyed to prevent improper
attachment. DS1250 PowerCap Modules and
DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC
data sheet for further information.
DS1250Y/AB
042398 3/11
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C, –40°C to +85°C for Ind parts
Storage Temperature –40°C to +70°C, –40°C to +85°C for Ind parts
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1250AB Power Supply Voltage VCC 4.75 5.0 5.25 V
DS1250Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 +0.8 V
(VCC=5V ± 5% for DS1250AB)
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=5V ± 10% for DS1250Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current IIL –1.0 +1.0 µA
I/O Leakage Current
CE > VIH < VCC IIO –1.0 +1.0 µA
Output Current @ 2.4V IOH –1.0 mA
Output Current @ 0.4V IOL 2.0 mA
Standby Current CE=2.2V ICCS1 5.0 10.0 mA
Standby Current CE=VCC–0.5V ICCS2 3.0 5.0 mA
Operating Current ICCO1 85 mA
Write Protection Voltage
(DS1250AB) VTP 4.50 4.62 4.75 V
Write Protection Voltage
(DS1250Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510 pF
Input/Output Capacitance CI/O 510 pF
DS1250Y/AB
042398 4/11
(VCC=5V ± 5% for DS1250AB)
AC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=5V ± 10% for DS1250Y)
PARAMETER SYMBOL DS1250AB–70
DS1250Y–70 DS1250AB–100
DS1250Y–100 UNITS NOTES
PARAMETER
SYMBOL
MIN MAX MIN MAX
UNITS
NOTES
Read Cycle Time tRC 70 100 ns
Access Time tACC 70 100 ns
OE to Output Valid tOE 35 50 ns
CE to Output Valid tCO 70 100 ns
OE or CE to Output Active tCOE 5 5 ns 5
Output High Z from Deselection tOD 25 35 ns 5
Output Hold from Address
Change tOH 5 5 ns
Write Cycle Time tWC 70 100 ns
Write Pulse Width tWP 55 75 ns 3
Address Setup T ime tAW 0 0 ns
Write Recovery Time tWR1
tWR2 5
15 5
15 ns
ns 12
13
Output High Z from WE tODW 25 35 ns 5
Output Active from WE tOEW 5 5 ns 5
Data Setup T ime tDS 30 40 ns 4
Data Hold T ime tDH1
tDH2 0
10 0
10 ns
ns 12
13
DS1250Y/AB
042398 5/11
READ CYCLE
tRC
tACC
VIH
VIL
VIH
VIL
VIH
VIL
tOH
VIH
tOD
tOD
VIH
VOH
VOL
VOH
VOL
tCOE
tCOE
OUTPUT
DATA VALID
DOUT
OE
ADDRESSES
VIH
VIH tOE
VIL
VIL
CE tCO
SEE NOTE 1
WRITE CYCLE 1
tWC
VIH
VIL
VIH
VIL
VIH
VIL
ADDRESSES
tAW
DATA IN STABLE
HIGH
IMPEDANCE
VIL VIL
VIL VIL
VIH VIH
tWP tWR1
tODW tOEW
tDS tDH1
VIH
VIL
VIH
VIL
CE
WE
DOUT
DIN
SEE NOTES 2, 3, 4, 6, 7, 8, AND 12
VCC
3.2V
tF
tPD
tR
tREC
DATA RETENTION
TIME
tDR
LEAKAGE CURRENT
IL SUPPLIED FROM
LITHIUM CELL
CE
VTP
SEE NOTE 11
DS1250Y/AB
042398 6/11
WRITE CYCLE 2
tWC
VIL
VIH VIL
VIH VIL
VIH
ADDRESSES
CE
WE
DOUT
DIN DATA IN STABLE
tAW tWP tWR2
VIH
VIL VIL VIL
VIH
VIH
VIL VIL
tCOE tODW
tDS tDH2
VIL
VIH
VIL
VIH
SEE NOTES 2, 3, 4, 6, 7, 8, AND 13
POWER–DOWN/POWER–UP CONDITION
DS1250Y/AB
042398 7/11
POWER–DOWN/POWER–UP TIMING (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE, WE at VIH before
Power–Down tPD 0µs11
VCC Slew from VTP to 0V tF300 µs
VCC Slew from 0V to VTP tR300 µs
CE, WE at VIH after Power–Up tREC 2125 ms
(tA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expected Data Retention Time tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. tDH, tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain
in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
9. Each DS1250 has a built–in switch that disconnects the lithium source until VCC is first applied by the user . The
expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied
by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod-
ucts, this range is 0°C to 70°C. For industrial products (IND), this range is –40°C to +85°C.
11.In a power–down condition the voltage on any pin may not exceed the voltage on VCC.
12.tWR1 and tDH1 are measured from WE going high.
13.tWR2 and tDH2 are measured from CE going high.
14.DS1250 DIP modules are recognized by Underwriters Laboratory (U.L.) under file E99151. DS1250 PowerCap
modules are pending U.L. review. Contact the factory for status.
A
1
DIM MIN MAX
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
1.680
42.67 1.700
43.18
0.720
18.29 0.740
18.80
0.355
9.02 0.375
9.52
0.080
2.03 0.110
2.79
0.015
0.38 0.025
0.63
0.120
3.05 0.160
4.06
0.090
2.29 0.110
2.79
0.590
14.99 0.630
16.00
0.008
0.20 0.012
0.30
0.015
0.38 0.021
0.53
C
F
GKD
H
B
E
J
32–PINPKG
DS1250Y/AB
042398 8/11
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 – 3.0V
T iming Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall T imes: 5 ns
ORDERING INFORMATION
DS1250 TTP– SSS – III Operating Temperature Range
blank: 0°to 70°
IND: –40° to +85°C
Access
70:
100:
Speed
70 ns
100 ns
Package T ype
blank: 32–pin 600 mil DIP
P: 34–pin PowerCap Module
Device T ype
AB: ±5%
Y: ±10%
DS1250Y/AB NONVOLATILE SRAM 32–PIN 740 MIL EXTENDED DIP MODULE
DS1250Y/AB
042398 9/11
DS1250Y/AB NONVOLATILE SRAM, 34–PIN POWERCAP MODULE
PKG
DIM
INCHES
MIN NOM MAX
A 0.920 0.925 0.930
B 0.980 0.985 0.990
C – – 0.080
D 0.052 0.055 0.058
E 0.048 0.050 0.052
F 0.015 0.020 0.025
G 0.020 0.025 0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW: REFERENCE ONLY
COMPONENTS AND PLACEMENTS
MAY DIFFER FROM THOSE SHOWN
DS1250Y/AB
042398 10/11
DS1250Y/AB NONVOLATILE SRAM, 34–PIN POWERCAP MODULE WITH POWERCAP
PKG
DIM
INCHES
MIN NOM MAX
A 0.920 0.925 0.930
B 0.955 0.960 0.965
C 0.240 0.245 0.250
D 0.052 0.055 0.058
E 0.048 0.050 0.052
F 0.015 0.020 0.025
G 0.020 0.025 0.030
TOP VIEW
SIDE VIEW
BOTTOM VIEW: REFERENCE ONLY
COMPONENTS AND PLACEMENTS
MAY DIFFER FROM THOSE SHOWN
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that
PowerCap Module bases experience
one pass through solder reflow oriented
label–side up (live–bug).
Hand soldering and touch–up
Do not touch soldering iron to leads for
more than 3 seconds. To solder, apply
flux to the pad, heat the lead frame pad
and apply solder . To remove part, apply
flux, heat pad until solder reflows, and
use a solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a
68–pin PLCC socket, attach a
DS9034PC PowerCap to a module base
then insert the complete module into the
socket one row of leads at a time, push-
ing only on the corners of the cap. Never
apply force to the center of the device.
To remove from a socket, use a PLCC
extraction tool and ensure that it does
not hit or damage any of the module IC
components. Do not use any other tool
for extraction.
DS1250Y/AB
042398 11/11
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
INCHES
MIN NOM MAX
A – 1.050 –
B – 0.826 –
C – 0.050 –
D – 0.030 –
E – 0.112 –
A
D
B
C
E
16 PL
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
PKG
DIM
INCHES
MIN NOM MAX
A – 1.050 –
B – 0.890 –
C – 0.050 –
D – 0.030 –
E – 0.080 –
A
D
B
C
E
16 PL
