L5963 Automotive dual monolithic switching regulator with LDO and HSD Datasheet - production data '!0'03 '!0'03 PowerSSO-36 (exposed pad) PowerSSO-36 (slug-up) *$3*36 VQFPN-48 Independent current limit on all regulators Extremely low quiescent current in standby conditions Power good / adjustable voltage detector outputs to realize customized power up/down sequences Featuress Description AEC-Q100 qualified Two step-down synchronous switching voltage regulators with internal power switches: - Wide input voltage range (from 3.5 V to 26 V) - Internal high-side/ low-side NDMOS - 1 V minimum output - 3.0 A load current - 250 kHz free-run frequency - 250 kHz < f < 2 MHz synchronization range - Integrated soft-start - Independent hardware enable pins - Independent power supply - 180 PWM output phase shift - Programmable switching frequency divider by 1, 2, 4 or 8 between the two DC/DC regulators - Power good function One standby / linear regulator - Output voltage programmable with external resistor divider - 250 mA maximum current capability - Backup function - Power good function One high side driver - 0.5 V max drop @ 0.5 A - Protected against short to ground and battery, loss of ground and battery, unsupplied short to battery Programmable under voltage battery detector - Under voltage threshold adjustable through dedicated pin (VDIN) Load dump protection Independent thermal protection on all regulators L5963 is a dual step-down switching regulator with internal power switches, high side driver and a low drop-out linear regulator that can operate as standby regulator or normal LDO. June 2017 This is information on a product in full production. All the regulators can be connected directly to the vehicle battery. In addition to an adjustable voltage detector, voltage supervisors are available. The two DC-DC converters can work in free-run condition or synchronize themselves to an external clock. DC/DCs' PWM outputs have a 180 phase shift. The high operating frequency allowed by the synchronization input helps to reduce AM and FM interferences and grants the use of small and low cost inductors and capacitors. This IC finds application in the automotive segment, where load dump protection and wide input voltage range are mandatory. A slug-up package option is available for applications which require heatsink use. In standby condition the device guarantees extremely low quiescent current (25 A typical @ -40 C < T < 85 C) Table 1. Device summary Order code Package Packing L5963DN-EHX L5963DN-EHT L5963U-KBX L5963U-KBT L5963Q-V0Y L5963Q-V0T PowerSSO36 (exposed pad) Tube Tape & Reel Tube Tape & Reel Tray Tape & Reel DocID028553 Rev 3 PowerSSO36 (slug-up) VQFPN-48 1/49 www.st.com Contents L5963 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 7 2/49 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Operative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Blocks functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.1 Unregulated supply input voltage (VINLDO) . . . . . . . . . . . . . . . . . . . . . 19 6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY) . . . 19 6.2.3 Power-good reset (related pins: LDOOK, LDOOKDLY) . . . . . . . . . . . . . 20 6.2.4 Power-good function of DC/DC1 (related pins: SW1OK, SW1OKDLY) . 20 6.2.5 Over voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.6 Power ground (PGND1 and PGND2) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.7 Signal ground (SGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.8 PWM signal ground (SWGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.9 TAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.10 Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.11 High-side driver (HSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.12 Switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 Output inductor (Lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 Output capacitors (COUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Input capacitors (CIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 Bootstrap capacitor (CBOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID028553 Rev 3 L5963 Contents 7.5 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 9.1 Package variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 PowerSSO-36 (exposed pad) package information . . . . . . . . . . . . . . . . . 40 9.3 PowerSSO-36 (slug-up) package information . . . . . . . . . . . . . . . . . . . . . 43 9.4 VFQFPN-48 (7x7x1.0 - opt. D) package information . . . . . . . . . . . . . . . . 45 9.5 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID028553 Rev 3 3/49 3 List of tables L5963 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. 4/49 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PowerSSO-36 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VQFPN-48 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal data (PowerSSO-36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal data (VQFPN-48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Components value for different output voltage cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum suggested power for L5963 in PSSO36 slug-down package . . . . . . . . . . . . . . . 37 Maximum suggested power for L5963 in QFN48 package. . . . . . . . . . . . . . . . . . . . . . . . . 37 PowerSSO-36 exposed pad package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-36 slug-up package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID028553 Rev 3 L5963 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Example of a typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Example of usage of two regulators in the same application . . . . . . . . . . . . . . . . . . . . . . . . 9 PowerSSO-36 pinout configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VQFPN-48 pinout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRR LDO 50 mA load vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Efficiency vs. output current (VIN = 14 V, fsw = 2 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Efficiency vs. output current (VIN = 14 V, fsw = 250 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 18 Low voltage warning monitor & delay schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Linear regulator diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Enable timing for standby regulator (ENLDO pin connect to supply directly) . . . . . . . . . . . 22 Enable timing for linear regulator (pin ENLDO isn't connected to VINLDO) . . . . . . . . . . . . 23 Switching regulators diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Closed loop system with TYPE III network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TYPE III compensated network diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-36 (slug-up) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VFQFPN-48 (7x7x1.0 - opt. D) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PowerSSO-36 (exp. pad) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PowerSSO-36 (slug up) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VFQFPN-48 (7x7x1.0) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DocID028553 Rev 3 5/49 5 Overview 1 L5963 Overview The L5963 integrates two switching mode synchronous step down converters, a linearly regulated power supply, a protected high side driver and voltage detectors. To guarantee a robust operation, all the outputs have independent thermal protection and current limitation. The two switching mode synchronous step-down converters employ voltage mode control and feed forward functions to provide good load regulation and line regulation. Each converter has its own enable. The users can adjust the output voltage of the two converters by an external resistor divider. If the converters need to work with a frequency different from the free running frequency, in order to consider EMC performance in system level, they can be synchronized to an external clock by applying it on the SYNCIN pin. The frequency should be higher than half of the free running frequency. If there are more than one L5963 in the system they can work in Master-Slave configuration, to make sure all L5963 have the same operating frequency of the Master device. This Master-Slave function is implemented by a dedicated pin SYNCOUT which always gives the operating frequency of DC/DC1. A dedicated voltage detector is integrated in the first switching converter to monitor DC/DC1 output. When the output voltage of DC/DC1 goes above the threshold, SW1OK is released and goes back to high with configurable delay set by a capacitor on the SW1OKDLY pin. The linear regulator can work as standby regulator with low Iq or as a non-standby regulator. Connecting its enable ENLDO to its supply VINLDO the regulator works as a standby regulator, while connecting ENLDO to a voltage lower than 5 V the regulator works as nonstandby regulator, with higher load capability but also higher quiescent current. In standby state, i.e. only the linear regulator is powered and works as a standby regulator, with a load below 100 A the device has a quiescent current of just 25 A. The small drop-out voltage of the linear regulator allows its use with low operating supply voltage. In many cases, the linear regulator has to provide voltages to devices which need the reset function, like a MCU: this is provided by the LDOOK output, that is pulled low when VOUTLDO goes below a threshold. Once VOUTLDO returns above that threshold, with a specified hysteresis, LDOOK goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY. The high side driver is enabled by a dedicated pin and has a very low drop-out voltage. Protection circuits, like independent thermal protection, OCP, OVP and some special protections (loss of GND, SPU, short to supply and so on), are implemented to make it very robust. L5963 also embeds a voltage monitor (VDOUT), adjustable by means of an external resistor divider, that can be used to sense the battery or other voltages in the system. Sensing voltage is fed to pin VDIN. For instance, VDOUT might be used to monitor the output of DC/DC2, realizing in this way the Power Good function for that block. VDOUT is pulled low when voltage on VDIN goes below the specified threshold. Once VDIN returns above that threshold, with a specified hysteresis, VDOUT goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY Two different packages are available. The PowerSSO-36 slug-down allows to dissipate the heat on the board and reduce the application size. The slug has to be connected to the ground plane. This is the package suggested for standard applications. When this is not enough, because the L5963 is used as pre-regulator for high consuming applications and both the 2 DC-DC are working at high currents, the PSSO36 slug-up allows the use of a heat-sink to make easier power dissipation. 6/49 DocID028553 Rev 3 L5963 2 Block diagram Block diagram Figure 1. Block diagram 6).37 6).,$/ "3 )NTERNAL REGULATOR 07- #,+ 2EF?6 2EF?6 3WITCHING 2EGULATOR "ANDGAP 2EF #/-0 39.#/54 6BG &"37 &",$/ 2EF?6 ,INEAR REGULATOR 6/54,$/ ,$//+ 37/+ 2ESET$ELAY 0OWER 'OOD $ELAY 07- ,$//+$,9 37/+$,9 6$). 6$/54 6OLTAGE SUPERVISORY WITH 0/2 DELAY 6$$,9 %.37 ,OGIC #ONTROL %.37 6).37 %.,$/ "3 %.(3$ 07- 2EF?6 #,+ 3WITCHING 2EGULATOR &"37 )NTERNAL REGULATOR 6"!4 #/-0 /SCILLATOR #,+ 3YNC ,OGIC 39.#). 6).(3$ #,/#+ #,+ &REQ ,OGIC 6BG (IGH 3IDE DRIVER (3$ &2$)6 '.$ 4!" 3'.$ 37'.$ 0'.$ 0'.$ DocID028553 Rev 3 '!0'03 7/49 48 Application diagrams 3 L5963 Application diagrams Figure 2. Example of a typical application diagram 9%DWW & & Q)9 X)9 5 9,1B/'2 (1B/'2 /'2B9287B2. & 7$% 8 / 7$% & X)9 ' 9%$7 9%DWW 733 9,1/'2 9287/'2 287B/'2 (1/'2 5 )%/'2 /'22. . & & X9 Q & & 5 /'22.'/< . Q &203 9,1B6: & & X)9 X)9 & (1B6: Q)9 6:B9287B2. & 6,1.B&/.B287 5 S )%6: (16: (1B6: 3:0 3*1' 6<1&B,1 / & Q9 S9 Q X9 X9 5 . & Q) & 9,16: S )%6: (16: %6 & 287B6: & )5',9 3*1' X+ 6<1&B287 3:0 & Q 5 & 9'287 9',1 5 5 9',1B2. 5 . 6:2. 6:2.'/< &203 & Q)9 5 5 . 9%DWW & X)9 Q & %6 & 9,16: Q 6,1.B&/.B,1 5. 5. . / & Q X+ 287B6: & & 5 & Q9 S9 9',1 +6'B287 Q & X9 & X9 9''/< Q 9,1+6' +6' 1& (1+6' 6:*1' 6*1' (1B+6' +6'B,1 *$3*36 8/49 DocID028553 Rev 3 L5963 Application diagrams Figure 3. Example of usage of two regulators in the same application 9%DWW & & Q)9 X)9 5. 9,1B/'2 5 287/'2 7$% 287B/'2 (1/'2 /'2B9287B2. 9287/'2 9,1/'2 (1B/'2 8 / 7$% & X)9 ' 9%$7 9%DWW 733 5 )%/'2 /'22. & & X9 Q 5 /'22.'/< & . . Q &203 9,1B6: & X)9 & (1B6: & S )%6: (16: Q)9 3:0 6:2.'/< & Q %6 5 3*1' 6<1&B,1 6,1.B&/.B287 &203 & S9 287B6: & Q & & X9 X9 5. & Q) & S )%6: (16: 5 3:0 / 3*1' 9'287 9',1 Q X+ 287B6: 5 & & %6 & 5 . 5. 9',1B2. Q X+ 5 & Q9 9,16: (1B6: / )5',9 & Q)9 & 6<1&B287 9%DWW & X)9 5 . 6:2. 6,1.B&/.B,1 5 5. 6:B9287B2. 5. & Q 9,16: & X)9 & Q S9 Q9 9',1 +6'B287 & X9 & X9 9''/< & Q +6' 9,1+6' 1& 6:*1' (1+6' 6*1' (1B+6' +6'B,1 9%DWW & & Q)9 X)9 & X)9 (1B/'2 /'2B9287B2. & 7$% 8 / 7$% 9%$7 9%DWW 733 9287/'2 9,1/'2 287B/'2B (1/'2 5 )%/'2 /'22. . & & X9 Q 5 /'22.'/< . Q &203 9,1B6: & & X)9 X)9 & (1B6: Q)9 6:B9287B2. & & S (16: )%6: 6,1.B&/.B287 5 6:2.'/< 3:0 3*1' 6<1&B,1 (1B6: / & S9 & Q 5. & Q) S (16: )%6: 5 5 . / 3*1' 9'287 9',1 & Q X+ 287B6:B & & X9 & %6 & X9 9,16: 3:0 & 287B6:B 5 & Q9 5. 9',1B2. Q X+ 6<1&B287 &203 & 5 & Q9 S9 9',1 +6'B287 Q & X9 & X9 9''/< Q +6' 9,1+6' (1+6' 1& 6*1' (1B+6' 6:*1' +6'B,1 & Q)9 & )5',9 & X)9 5 . 5. 9%DWW 5 6:2. %6 5. & Q 9,16: Q 6,1.B&/.B,1 *$3*36 DocID028553 Rev 3 9/49 48 Pins description 4 L5963 Pins description Figure 4. PowerSSO-36 pinout configuration 4! " 0'.$ 0'.$ %.37 %.37 "3 "3 07- 07- %.,$/ %.(3$ 6).37 6).37 37/+ 39.#/54 4%34 39.#). 37/+$,9 3LUG DOWN &2$)6 6"!4 6$/54 37'.$ &"37 &"37 #/-0 #/-0 3'.$ 6).,$/ 6$). ,$//+$,9 6).(3$ ,$//+ (3$ 6/54,$/ 6$$,9 &",$/ '!0'03 0'.$ 4!" %.37 0'.$ "3 %.37 07- "3 %.,$/ 07- 6).37 %.(3$ 37/+ 6).37 4%34 39.#/54 37/+$,9 39.#). 6"!4 &2$)6 37'.$ 6$/54 &"37 &"37 #/-0 #/-0 6).,$/ 3'.$ ,$//+$,9 6$). ,$//+ 6).(3$ 6/54,$/ (3$ &",$/ 6$$,9 3LUG UP '!0'03 Table 2. PowerSSO-36 pins description 10/49 Pin # Name Type 1 TAB n.a. 2 PGND1 Ground 3 ENSW1 Input 4 BS1 Supply Function Device slug terminal. To be connected to ground Switching regulator 1 power ground Switching regulator 1 enable. 1.8/3.3 V compatible Switching regulator 1 boosted supply DocID028553 Rev 3 L5963 Pins description Table 2. PowerSSO-36 pins description (continued) Pin # Name Type Function 5 PWM1 Output 6 ENHSD Input 7 VINSW1 Supply Switching regulator 1 supply voltage 8 SYNCOUT Output External synchronization output (push-pull) 9 SYNCIN Input 10 FRDIV Input/output Switching frequency divider setting 11 VDOUT Output Voltage detector output (open drain) 12 FBSW1 Input/output Switching regulator 1 feedback voltage 13 COMP1 Input/output Switching regulator 1 compensation 14 SGND Ground 15 VDIN Input 16 VINHSD Supply High Side Driver supply 17 HSD Output High Side Driver output 18 VDDLY Input/output Voltage Detector delay setting 19 FBLDO Input/output LDO feedback voltage 20 VOUTLDO Output LDO output 21 LDOOK Output LDO voltage detector output (open drain) 22 LDOOKDLY Input/output 23 VINLDO Supply 24 COMP2 Input/output Switching regulator 2 compensation 25 FBSW2 Input/output Switching regulator 2 feedback voltage 26 SWGND Ground Low-power switching ground 27 VBAT Supply Common linear blocks supply voltage 28 SW1OKDLY Input/output 29 TEST n.a. 30 SW1OK Output Switching regulator 1 voltage detector output (open drain) 31 VINSW2 Supply Switching regulator 2 supply voltage 32 ENLDO Input 33 PWM2 Output Switching regulator 2 switching output 34 BS2 Supply Switching regulator 2 boosted supply 35 ENSW2 Input 36 PGND2 Ground Switching regulator 1 switching output Enable for High Side Driver. 1.8/3.3 V compatible External synchronization input Ground for linear blocks Voltage detector threshold setting LDOOK delay setting LDO supply SW1OK delay setting Pin for testing purposes. To be left unconnected LDO enable. 1.8/3.3 V compatible Switching regulator 2 enable. 1.8/3.3 V compatible Switching regulator 2 power ground DocID028553 Rev 3 11/49 48 Pins description L5963 Figure 5. VQFPN-48 pinout configuration 3:0 (1/'2 9,16: 9,16: 7(67 6:2. 9%$7 6:2.'/< 6:*1' )%6: &203 9,1/'2 /'22.'/< /'22. %6 (16: 1& 1& 9287/'2 1& 9287/'2 3*1' )%/'2 3*1' 9''/< 3*1' +6' 3*1' +6' 1& 9,1+6' (16: 9,1+6' 1& 1& %6 3: (1+6' 6<1&,1 6<1&287 9,16: 9,16: )5',9 9'287 )%6: &203 6*1' 9',1 *$3*36 Table 3. VQFPN-48 pins description 12/49 Pin # Name Type Function 1 BS2 Supply 2 ENSW2 Input Switching regulator 2 enable. 1.8/3.3 V compatible 3 NC N.C. Not connected 4 NC N.C. Not connected 5 PGND2 Ground Switching regulator 2 power ground 6 PGND2 Ground Switching regulator 2 power ground 7 PGND1 Ground Switching regulator 1 power ground 8 PGND1 Ground Switching regulator 1 power ground 9 NC N.C. Not connected 10 ENSW1 Input Switching regulator 1 enable. 1.8/3.3 V compatible 11 NC N.C. Not connected 12 BS1 Supply Switching regulator 1 boosted supply 13 PWM1 Output Switching regulator 1 switching output 14 ENHSD Input 15 SYNCOUT Output Switching regulator 2 boosted supply Enable for High Side Driver. 1.8/3.3 V compatible External synchronization output (push-pull) DocID028553 Rev 3 L5963 Pins description Table 3. VQFPN-48 pins description (continued) Pin # Name Type Function 16 SYNCIN Input 17 VINSW1 Supply Switching regulator 1 supply voltage 18 VINSW1 Supply Switching regulator 1 supply voltage 19 FRDIV Input/output Switching frequency divider setting 20 VDOUT Output Voltage detector output (open drain) 21 FBSW1 Input/output Switching regulator 1 feedback voltage 22 COMP1 Input/output Switching regulator 1 compensation 23 SGND Ground 24 VDIN Input Voltage detector threshold setting 25 NC N.C. Not connected 26 VINHSD Supply High Side Driver supply 27 VINHSD Supply High Side Driver supply 28 HSD Output High Side Driver output 29 HSD Output High Side Driver output 30 VDDLY Input/output Voltage Detector delay setting 31 FBLDO Input/output LDO feedback voltage 32 VOUTLDO Output LDO output 33 VOUTLDO Output LDO output 34 NC N.C. 35 LDOOK Output 36 LDOOKDLY Input/output 37 VINLDO Supply 38 COMP2 Input/output Switching regulator 2 compensation 39 FBSW2 Input/output Switching regulator 2 feedback voltage 40 SWGND1 Ground Low-power switching ground 41 VBAT Supply Common linear blocks supply voltage 42 SW1OKDLY Input/output 43 TEST n.a. 44 SW1OK Output Switching regulator 1 voltage detector output (open drain) 45 VINSW2 Supply Switching regulator 2 supply voltage 46 VINSW2 Supply Switching regulator 2 supply voltage 47 ENLDO Input 48 PWM2 Output External synchronization input Ground for linear blocks Not connected LDO voltage detector output (open drain) LDOOK delay setting LDO supply SW1OK delay setting Pin for testing purposes. To be left unconnected LDO enable. 1.8/3.3 V compatible Switching regulator 2 switching output DocID028553 Rev 3 13/49 48 Electrical specifications L5963 5 Electrical specifications 5.1 Absolute maximum ratings Table 4. Absolute maximum ratings Pin name / symbol Parameter Unit VBATOP VINOP Operating input voltage -0.3 to +26 V VBATMAX VINMAX Maximum transient supply voltage -0.3 to +40 V Ground pins voltage -0.3 to +0.3 V LDO enable pin voltage -0.3 to +40 V Other pins operating voltage -0.3 to +3.6 V Other pins voltage -0.3 to +4.6 V Top Operating ambient temperature range -40 to +105 C Tstg Storage temperature range -55 to +150 C 150 C PGND1/2, SGND, SWGND, TAB ENLDO Vpinop Vpinmax Tj 5.2 Value Junction temperature Thermal data Table 5. Thermal data (PowerSSO-36) Symbol Rth j-a-2s Rth j-a-2s2p Parameter Thermal resistance junction-to-ambient (Max) (slug down configuration) Rth j-a-2s2pv Rth j-case Board Value Unit 2s 53 C/W 2s2p 27 C/W 2s2p+vias 22 C/W 1.5 C/W Board Value Unit 2s 66 C/W 2s2p 32 C/W 2s2p+vias 26 C/W 2.2 C/W Thermal resistance junction-to-case (Max) Table 6. Thermal data (VQFPN-48) Symbol Parameter Rth j-a-2s Rth j-a-2s2p Thermal resistance junction-to-ambient (Max) Rth j-a-2s2pv Rth j-case 14/49 Thermal resistance junction-to-case (Max) DocID028553 Rev 3 L5963 5.3 Electrical specifications Electrical characteristics VBAT = VIN = 14.4 V, Tamb = 25 C unless otherwise specified. Table 7. Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit 3.5 4 - 26 26 V V Shutdown mode - 1.5 2 Standby mode; IloadLDO = 100 A - 23 28 Inputs and controls Standby mode VOUTLDO = 1.2 V/100 mA VOUTLDO = 3.3 V/100 mA VBATOP VBAT operating range Iq Total quiescent current OVVBAT Overvoltage shut-down threshold on VBAT VBAT rising 27 29 31 V UVVBAT Undervoltage shut-down threshold on VBAT VBAT falling VDOUT forced to 0 V 2.7 3 3.3 V HysUV Hysteresis on UVVBAT - - 0.1 0.5 V ENmin Min voltage for enable pins high level - 1.6 - - V ENmax Max voltage for enable pins low level - - - 1 V fswSW2 = fswSW1 0 - 30 RFRDIV Thresholds of value of resistor fsw SW2 = fswSW1/2 connected between FRDIV pin fswSW2 = fswSW1/4 and ground 60 - 70 110 - 115 fswSW2 = fswSW1/8 180 - A k Voltage detector THRVDIN Voltage Detector input voltage threshold - 0.9 0.94 0.98 V HysVDIN Voltage Detector input voltage hysteresis - - 30 40 mV I = 1 mA in VDOUT pin - - 0.1 V VDDLY output current - 6 9 12 A VDDLY threshold - 2.1 2.3 2.5 V 990 1000 1010 mV VmaxVDOUT VDOUT saturation voltage IVDDLY THRVDDLY Linear regulator VFBLDO Feedback voltage Iload = 100 mA UVLDO Undervoltage shut-down threshold on LDO VINLDO decreasing - 2.2 2.4 V HysLDO Hysteresis on UVLDO - - - 100 mV LdRLDO FBLDO load regulation 10 mA < Iload < 250 mA - 5 - mV LnRLDO FBLDO line regulation 3.5 < VINLDO < 26 V Iload = 100 mA - 1 - mV DocID028553 Rev 3 15/49 48 Electrical specifications L5963 Table 7. Electrical characteristics (continued) Symbol Min Typ Max 5 mA 250 mA Iload transition -5 - 5 8 18 V VINLDO transition -5 - 5 VOUTLDO = 3.3 V Iload = 250 mA VOUTLDO decreasing of 100 mV - 270 320 mV VOUTLDO shorted to ground - 350 420 mA VOUTLDO (st-by) shorted to ground - 65 80 mA Power supply rejection ratio Iload = 50 mA, 10 Hz < f < 10 kHz 1 Vacpp on VINLDO - 70 - dB Output noise 20 Hz < f < 20 kHz Iload = 5 mA - 100 - V Thermal shut-down temperature Temperature rising 150 160 - C HysTSDLDO Hysteresis on thermal shutdown temperature - 5 - 15 C Co Output capacitance(1) - 3 - - F Output capacitor ESR(1) - - - 0.2 - 91 94 97 % - - 90 - mV VmaxLDOOK LDOOK saturation voltage I = 1 mA in LDOOK pin - - 0.2 V TglitchLDOOK Glitch filter time for LDO-OK - 5 12 20 s - 7 10 13 A - 2 2.2 2.4 V 980 1000 1020 mV 50 mA < Iload < 1 A - 1 - mV 3.5 V < VINSWx < 26 V - 1 - mV VFBLDO / VFBLDO VdoLDO Parameter Test conditions FBLDO Undershoot/overshoot(1) Drop-out voltage IshortLDO IshortST-BY PSRRLDO nLDO TSDLDO ESR Short circuit current limit Unit % Voltage detector on LDO THRLDOOK / LDOOK threshold as VFBLDO percentage of FBLDO voltage HysLDOOK ILDOOKDLY Hysteresis on LDOOK LDOOKDLY output current THRLDOOKDLY LDOOKDLY threshold Switching regulators(2) VFBSWx LdRSWx Feedback voltage FBSWx load Iload = 100 mA regulation(3) (3) LnRSWx FBSWx line regulation UVSW1 Undervoltage shut-down threshold on SW1 VINSWx decreasing - 2.8 3 V HysSW1 Hysteresis on UVSW1 (3) - - 0.15 - V UVSW2 Undervoltage shut-down threshold on SW2 VINSWx decreasing - 2.8 3 V HysSW2 Hysteresis on UVSW2 (3) - - 0.15 - V VFBSWx / VFBSWx FBSWx pin undershoot/overshoot(3) 500 mA 1.5 A Iload transition -5 - 5 % 8 18 V VINSWx transition -5 - 5 % 16/49 DocID028553 Rev 3 L5963 Electrical specifications Table 7. Electrical characteristics (continued) Symbol Parameter IlimSW1 Peak current limitation on sw1 IlimSW2 fsw fsync Min Typ Max Unit - 2.5 3 3.5 A Peak current limitation on sw2 - 3 3.5 4 A Free-run switching frequency - 225 250 275 kHz 50% duty-cycle wave on SYNC pin 250 - 2000 kHz VINSWx > 3.5 V; including bonding wires - 85 - m - 105 - m Free run frequency VOUTSW1/2 = 5 V; Iload = 2.5 A VOUTSW1/2 = 5 V; Iload = 1 A - 90 93 - % Including bonding wires - 0.95 - V/ms 150 160 - C Switching frequency range(3) Test conditions RonHS High side MOS on resistance(3) RonLS Low side MOS on resistance(3) Including bonding wires Efficiency(3) VFBSWx / t FB pin slope at turn-on(3) TSDSWx Thermal shutdown temperature Temperature rising Hysteresis on thermal shutdown temperature - 5 - 15 C - 91 94 97 % - - 35 50 mV VmaxSW1OK SW1OK saturation voltage I = 1 mA in SW1OK pin - - 0.2 V TglitchSW1OK Glitch filter time for SW1-OK - 9 13 17 s - 6 10 13 A - 2 2.2 2.4 V - - 20 - ns - 140 170 mV HysTSDSWx THRSW1OK / SW1OK threshold as VFBSW1 percentage of FBSW1 voltage HysSW1OK ISW1OKDLY Hysteresis on SW1OK SW1OKDLY output current THRSW1OKDLY SW1OKDLY threshold ton-min Minimum on time(3) High side driver VdropHSD Output saturation Iload = 0.5 A IshortHSD Short circuit current limit - 0.7 1 1.3 A TSDHSD Thermal shut-down temperature Temperature rising 150 160 - C Hysteresis on thermal shutdown temperature - 5 - 15 C HysTSDHSD 1. Not tested at ATE. 2. Tests involving switching frequencies higher than 1 MHz are guaranteed by design. 3. Test guaranteed by application measurements. DocID028553 Rev 3 17/49 48 Electrical specifications L5963 Figure 6. PSRR LDO 50 mA load vs. frequency G% Figure 7. Efficiency vs. output current (VIN = 14 V, fsw = 2 MHz) 9 (IILFLHQF\ 9 +] N N N N N *$3*36 Figure 8. Efficiency vs. output current (VIN = 14 V, fsw = 250 kHz) 9 (IILFLHQF\ 9 18/49 /RDGP$ *$3*36 DocID028553 Rev 3 /RDG P$ *$3*36 L5963 Functional Description 6 Functional Description 6.1 Operative modes L5963 has three main operative modes: Shutdown mode: all enable pins are low and the device is completely off. In this condition the quiescent current is typically 1.5 A. Standby mode: the linear regulator is configured as stand-by regulator by connecting ENLDO directly to VINLDO. In this condition the quiescent current is typically 25 A. Normal mode: the linear regulator works as LDO and/or other blocks (DC/DC or HSD) are turned on. 6.2 Blocks functional description 6.2.1 Unregulated supply input voltage (VINLDO) This terminal provides the power for internal circuitry to bias band-gap reference, standby regulator and other circuitry in the device. If backup function is needed, an external capacitor connected to this pin shall be charged through an external diode which is used to block reverse discharging. With backup function, when the system battery is removed or drops too low suddenly, the internal bias and regulator can operate correctly for a certain time, which avoids MCU to work abnormally and allows MCU to have enough time to turn-off. 6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY) An external voltage can be sensed through the VDIN pin. This voltage is scaled using an external resistor network and compared with an internal threshold to detect a low voltage condition (Figure 9.). Once the input voltage is below the threshold, the low voltage warning output terminal (VDOUT) is pulled low after the designed glitch-filtering (~12 s). VDOUT is an open drain output. If the input returns above the threshold with the specified hysteresis, VDOUT is released after a defined delay, determined by the capacitor on pin VDDLY. The threshold is fixed to 0.95 V typ. The capacitor on VDDLY pin sets VDOUT delay. A current source (~9 A) on this pin charges the external capacitor to generate the required delay, programmable by adjusting the value of the capacitor. This voltage monitor can also be used to monitor DC/DC2 output. Changing the ratio of the external resistor divider the low voltage warning threshold can be adjusted. DocID028553 Rev 3 19/49 48 Functional Description L5963 Figure 9. Low voltage warning monitor & delay schematic 9Y .([WHUQDOUHVLVWRU %DWWHU\ YGG 9'287 ODWFK )%6:SLQ RSWLRQDO SZPSRZHU JRRGIXQFWLRQ 9',1 GHJOLWFK 6 4 5 4 &203 97+ YGG ODWFK 64 6 4 54 5 4 9'287'/< ([WHUQDOFDSDFLWRU :LQGRZFRPS *$3*36 6.2.3 Power-good reset (related pins: LDOOK, LDOOKDLY) LDOOK monitors the regulator output VOUTLDO. Its circuit topology is the same as the voltage detector one (Figure 9). Its threshold is fixed to 95% typ of the feedback voltage, and the hysteresis is always ~2% typ. Pin LDOOK is an open drain output, and pin LDOOKDLY is used to adjust the delay in the release of LDOOK output. 6.2.4 Power-good function of DC/DC1 (related pins: SW1OK, SW1OKDLY) SW1OK monitors DC/DC1 output. Its circuit topology is the same as the voltage detector one (Figure 9). Its threshold can't be adjusted, it is always 95% typ of the feedback voltage, and the hysteresis is ~35mV typ. Pin SW1OK is an open drain output, and pin SW1OKDLY is used to adjust its delay. 6.2.5 Over voltage shutdown Two internal over voltage shutdown (OV) blocks are included in L5963. One (OV1) senses VBAT pin, the other (OV2) detects VINLDO pin. If VBAT gets too high, to prevent any damage, DC/DC1, DC/DC2 and the high-side driver are disabled by OV1. They will be turned on once VBAT returns below the detection threshold with the specified hysteresis. If the linear regulator works as a non-standby regulator and VINLDO gets too high, to prevent any damage the LDO is disabled by OV2. It is turned on once VINLDO returns below the detection threshold with the specified hysteresis. On the contrary, the linear regulator works as a standby regulator, OV2 doesn't intervene and the regulator continues to work even if VINLDO increases. 20/49 DocID028553 Rev 3 L5963 6.2.6 Functional Description Power ground (PGND1 and PGND2) PGND1 pin and PGND2 pin are power ground references for the DC/DC1 and DC/DC2 respectively. All switching nodes are referred to these two pins. 6.2.7 Signal ground (SGND) This pin is the ground reference for standby regulator, HSD and internal bias. 6.2.8 PWM signal ground (SWGND) This pin is the ground reference for signal part of DC/DC1 and DC/DC2. 6.2.9 TAB TAB is connected to the device substrate. This pin must be connected to GND to guarantee the substrate is always at the lowest potential to avoid parasitic activation. 6.2.10 Linear regulator Figure 10. Linear regulator diagram 9,1/'2 6WDQGE\UHJXODWRU 5() ($ 'ULYHU 9287/'2 (1 C (1B&RQWURO (1/'2 5 (1 (1 ([WHUQDOUHVLVWRU )%/'2 (1 &RPPRQ/'2 ($ 5() 5 9,1/'2 'ULYHU *$3*36 The linear regulator has two operative modes: standby mode and non-standby mode. Its output voltage is set by an external resistor divider through the feedback pin FBLDO. As a standby regulator, the current capability is reduced to 50 mA and the quiescent current minimized. In this case, the external resistor divider should be in the Mega ohm order to reduce total quiescent current. As a non standby regulator, it has higher load capability (up to 250 mA). DocID028553 Rev 3 21/49 48 Functional Description L5963 Connecting ENLDO pin directly to its supply VINLDO (it should be higher than 5 V), the regulator works as a standby regulator. Once ENLDO is ever higher than 5 V, the regulator works as a standby regulator till VINLDO is powered down, to reset a flag stored in an internal register. Figure 11. Enable timing for standby regulator (ENLDO pin connect to supply directly) 3TANDBY MODE 3TANDBY MODE 6).,$/%.,$/ .ORMAL MODE .ORMAL MODE .ORMAL MODE 3HUT DOWN 3HUTDOWN 64( 6 THRESHOLD 64( 56,/ THRESHOLD 64( %NBLE PIN THRESHOLD T %. %NABLE STAND BY REGULATOR T %. %NABLE COMMON ,$/ T '!0'03 The linear regulator works as a non-standby regulator if ENLDO is <5 V. 22/49 DocID028553 Rev 3 L5963 Functional Description Figure 12. Enable timing for linear regulator (pin ENLDO isn't connected to VINLDO) 6).,$/ T .ORMAL MODE %.,$/ 3HUTDOWN 3TANDBY MODE 3HUTDOWN 64( 64( T %. %NABLE STANDBY REGULATOR T %. %NABLE COMMON ,$/ T '!0'03 The linear regulator operates with output voltages down to 1.2 V, and offers a maximum dropout voltage of 500 mV at rated load current. This regulator has an independent thermal protection and a current-limiting circuit. It should be always supplied (by VINLDO) with a voltage not lower than 3.5 V because, even if not used, it gives the common supply to all internal blocks which have to stay alive when the battery drops too low (backup functionality). 6.2.11 High-side driver (HSD) The HSD pin is the output of the high side driver. It has a dedicated enable pin ENHSD. Following protections are implemented: Over-current protection Short to supply Short to ground Short through the load to -1 V Unpowered short to supply Loss of ground Over voltage protection DocID028553 Rev 3 23/49 48 Functional Description L5963 Thermal protection The HSD has an independent thermal shutdown protection. If the local die temperature exceeds the thermal shutdown detection threshold, the HSD is disabled. It is enabled once the local die temperature falls below the detection threshold with the specified hysteresis. The invoking of thermal shut down on HSD does not directly affect any other outputs or circuitry in the IC. Short to ground The high side driver output is protected against shorts to ground. The faulted output returns to its pre-fault operating condition once the fault is removed. Short to supply The high-side driver is protected against shorts to battery. In such an event, the IC is not damaged. External components connected directly to the IC are not damaged by such exposure. Loss of ground protection The high side driver is protected against excessive leakage current to an external ground during a loss of supply ground (i.e. ground is open). During this event, the HSD is disabled and the IC is not damaged. Loss of battery protection (Unpowered shorts to battery, SPU) The high-side driver is protected against unpowered shorts to battery. In such an event, in typical applicative conditions, the IC will not suffer any damage. Below-ground protection The HSD output can be brought below ground by the inductive load. In this case, Power PMOS is turned on to charge the output, protecting itself. 24/49 DocID028553 Rev 3 L5963 6.2.12 Functional Description Switching regulators Figure 13. Switching regulators diagram /3# 39.#). 39.#/54 39.# FOSC FOSC 07- #,+ 6).37 39.# 3AWTOOTH GENERATOR WITH FEEDFORWARD 6).37 &REQUENCY $IVIDER BY &2$)6 "3 6607- $RIVER 3OFT 3TART 62%& 07#/-0 %22/2 !-0 3 1 2 ? 1 07- 6# P 6&"37 &"37 M: 0'.$ $RIVER #/-0 $-$ !MP %.37 2EGULATOR 6607- 07- #,+ PHASESHIFT /#0 !MP )2%& 0ROTECT "LOCKS 56,/ $UMP 34' /40 6"!4 %.37 37'.$ 2EGULATOR 0ROTECT "LOCKS 56,/ $UMP 34' /40 66 07- 07- #,+ 6).37 6).37 3AWTOOTH GENERATOR WITH FEEDFORWARD "3 6607- $RIVER 3OFT 3TART 62%& &"37 %22/2 !-0 07#/-0 3 1 2 ? 1 M: 07- 6# P 6&"37 0'.$ $RIVER #/-0 $-$ !MP /#0 !MP )2%& '!0'03 L5963 embeds two synchronous DC/DC converters that incorporate all the control and necessary protection circuitries to satisfy a wide range of applications. DC/DC1 and DC/DC2 are enabled by pin ENSW1 and pin ENSW2 respectively. The two switching converters employ voltage mode control and feed forward function to provide good load regulation and line regulation. DocID028553 Rev 3 25/49 48 Functional Description L5963 Both switching regulators can operate up to a 100% duty cycle. Once every four switching periods, the PWM output is forced low for 100ns typ to refresh the bootstrap capacitor. Their features include: Wide input voltage range (from 3.5 V to 26 V) Min output of 1 V 250 kHz free-run frequency and synchronization range from 250 kHz to 2 MHz. The voltage feed forward is implemented in all frequency range Internal 85 m high-side and 105 m low-side switching MOSFET Up to 3 A load current capability Power ok (SW1OK) output Internal soft start function to minimize startup inrush current Pulse-by-pulse current limiting (OCP) Discontinuous mode detection (DMC) Over temperature protection (OTP) UVLO with stop threshold at 2.8 V (typ) Load dump protection Externally adjustable compensation Stable with ceramic output capacitors Oscillator/switching frequency The internal oscillator provides a constant frequency clock of 250 kHz. The switching frequency of DC/DC1 and DC/DC2 are determined by the internal frequency clock and the external synchronization clock. When no clock is applied to the SYNCIN pin or the synchronization clock is lower than 125 kHz (half of the internal clock), the two switching regulators work both with the internal 250 kHz clock. When the SYNCIN pin has a synchronization clock larger than 125 kHz, the external synchronization clock is adopted. There is a phase shift of 180 between PWM1 and PWM2, and the frequency of PWM2 can be the same, 1/2, 1/4, 1/8 of PWM1 one. The division factor is programmed by FRDIV pin. The switching clock of DC/DC1 can be sent out by pin SYNCOUT to synchronize another device, in view of reducing EM disturbance. Internal high-side and low-side Power MOSFET / Bootstrap structure The two synchronous switching regulators don't need the external Schottky diode. Each of them integrates a high-side and a low-side n-channel Power MOSFET, which allows a very low drop voltage under high load current operation (up to 3 A). The Bootstrap structure is used to drive the high-side n-channel Power MOSFET. A Bootstrap capacitor of about 47 nF is needed. Internal soft start function (SS) To reduce the inrush current during startup, an internal soft start is implemented. The total soft start time is about 400 s and it doesn't change with operating frequency. 26/49 DocID028553 Rev 3 L5963 Functional Description Pulse-by-pulse current limiting (OCP) The current in the upper MOSFET is monitored and if it exceeds the pulse-by-pulse overcurrent threshold (ILIM) then the upper MOSFET is turned off. Normal PWM operation resumes on the next oscillator clock pulse. DC/DCs' embed leading edge blanking to prevent falsely triggering the pulse-by-pulse current limit when the upper MOSFET is turned on. The blanking time is about 100 ns, so the minimum switching on time should be bigger than 100 ns: Equation 1 6/54 $ $ !NS I 37 NS 6). NS I 37 From the above equation, when the input and output voltage are already known, the switching frequency should be within the range of the above equation, otherwise the OCP function is not guaranteed. Pulse-by-pulse current limiting is always active. The threshold of OCP is about 3.5 A for dc-dc1 and 4A for dc-dc2. Low-Side Over Current Protection (LS OCP) LS OCP protects DC/DCs by limiting inductor current, when either the load is too high at high frequency or when the output of the converter is shorted to ground. The current in the low-side MOSFET is monitored and, if it exceeds the pulse-by-pulse overcurrent threshold (ILIM), it prevents the turning on of the high-side MOSFET in the successive switching period. In high frequency and high load conditions, the inductor current cannot decrease even if HS OCP is triggered due to the blanking time, which results in the inductor current getting higher and higher every switching period. If inductor current reaches LS OCP threshold, that is set to a level higher than HS OCP one, PWM switching is stopped, waiting for the inductor current to decrease to a lower value. PWM switching will recover as soon as LS OCP is released. If high load and high frequency conditions remain, for instance in case of a short circuit being present on the regulator output, another LS OCP will occur. Upon removal of the short circuit PWM switching will immediately recover, bringing the regulator back to normal operation. Discontinuous Mode Detection (DMD) In order to save quiescent current when switching regulators are working in light load condition, L5963 embeds a Discontinuous Mode Detection (DMD) circuit: DMD prevents inductor current to continuously flow to ground during Toff by turning off LS MOSFET and leaving PWM in tristate. Over temperature protection (OTP) Each DC/DC has its own OTP, which detects the local temperature and shuts down the regulator when temperature reaches the specified threshold. Dump protection If the voltage on VBAT supply exceeds the over-voltage shut-down threshold, DC/DCs are disabled. Once VBAT returns to working conditions, the output recovers to the normal state. DocID028553 Rev 3 27/49 48 Functional Description L5963 Under voltage lock out (UVLO) The UVLO circuit generates the shutdown signal to turn off DC/DCs when VBAT is lower than the specified threshold. They are turned back on once VBAT goes above the detection threshold with the specified hysteresis. 28/49 DocID028553 Rev 3 L5963 Application information 7 Application information 7.1 Output inductor (Lo) The value of the output inductor (Lo) is usually calculated to satisfy the peak-to-peak ripple current requirement. For the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between 20% and 40% of the maximum current. For example, if IL = IRipple = 0.3 x IOUT(max). Where, IOUT(max) is the maximum output current. Then, the inductor value can be estimated by the following equation: Equation 2 ,t * 6/54 6 /54 I 37 u ') , (c) 6). MAX Where, fSW is the switching frequency, VIN(max) is the maximum input voltage. If VOUT = 3.3 V, VIN(max) = 26 V, fSW = 250 kHz, IL = 0.3 x 3 A = 0.9 A Equation 3 ,t * u ( u u (c) ( The next higher available value should be used, so L = 15 H. The peak current flowing in Inductor is IL(peak) = IOUT(max) + IL / 2. If the Inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device. An inductor having saturation current higher than the device current limit has to be chosen. DocID028553 Rev 3 29/49 48 Application information 7.2 L5963 Output capacitors (COUT) Output capacitors are selected to support load transients and output ripple current, as well as to get loop stability. The amount of voltage ripple can be calculated by the output ripple current flowing in the Inductor: Equation 4 '6OUT %32 u ') , ') , u #OUT u F SW Usually the first term is dominant. However, if a ceramic capacitor (which is recommended) is adopted, the first term on the above equation can be neglected as the ESR value is very low. For example, in case Vout = 3.3 V, Vin = 14 V, fSW = 250 kHz, IL = 0.3 x 3 A = 0.9 A, in order to have a Vout = 5%* Vout =0.165 V, a 4.7 F ceramic capacitor is needed. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. In the above example, if a 100 F with ESR = 100 m electrolytic capacitor is chosen, the voltage drop on ESR dominates and the voltage ripple is 90 mV. The output capacitor is also important to sustain the output voltage during a load transient. In general, minimizing the ESR value and increasing the output capacitance results in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel, or by using higher quality capacitors. If ceramic capacitors are chosen, in presence of a fast load transient the output voltage will change by the amount. Equation 5 '6OUT , ) OUT MAX ) OUT MIN u #OUT u 6OUT Where: Iout(max), Iout(min) refer to the worst case load in the system and Vout is the tolerance of the regulated output voltage, 5% of Vout. For example, Vout = 5 V, Vin = 14 V, Iout(max) =1.5 A, Iout(min) = 0.5 A, L = 22 H Equation 6 #OUT , )OUT MAX )OUT MIN u '6OUT u 6OUT & So two 10 F ceramic capacitors in parallel are needed. The output capacitor is also important for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Section 7.5: Compensation network, it will be illustrated how to consider its effect in the system stability. 30/49 DocID028553 Rev 3 L5963 7.3 Application information Input capacitors (CIN) The input capacitors must be chosen to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitors must deliver the RMS current according to below equation: Equation 7 )RMS )O $ u $ Where Io is the maximum DC output current and D is the duty cycle. This function has a maximum at D = 0.5 and it is equal to Io/2. Equation 8 $ 6OUT 6DL 6IN 6DH 6DL Vdl is the voltage drop across the low side DMOS, and Vdh is the voltage drop across the high side DMOS. For example, with 20% duty cycle, the input/output current multiplier is 0.400. Therefore, if the regulator is delivering 3 A of steady-state load current, the input capacitor(s) must support 0.400 x 3 A or 1.2 Arms. Ceramic capacitors can deliver quite a bit of current but their total capacitance is relatively low. Electrolytic capacitors typically offer much more capacitance than ceramic capacitors, but can typically deliver a current of 100 to 500 mArms. So a good design will employ both types of capacitors with the ceramic capacitors placed closest to the input pins of the device. As a result, ceramic capacitors which have very low ESR and inductance are the best for filtering the high frequency switching noise, and electrolytic capacitors are typically able to provide more current over extended periods of time where VIN would otherwise droop. 7.4 Bootstrap capacitor (CBOOT) A bootstrap capacitor must be connected between the BOOT and SW pins to provide floating gate drive to the high-side MOSFET. For most applications 47 nF is sufficient. This should be a ceramic capacitor with a voltage rating of at least 6 V. 7.5 Compensation network The compensation network has to assure stability and good dynamic performance. The loop of the device is based on the voltage mode control, compatible with TYPE III compensation network (Figure 14). The error amplifier is a voltage operational amplifier with large bandwidth, which is much larger than the closed-loop one. DocID028553 Rev 3 31/49 48 Application information L5963 Figure 14. Closed loop system with TYPE III network '6/3# 6IN $2)6%2 /3# 07#/-0!2!4/2 ,O VOUT $#2 0(!3% # %32 $2)6%2 # # 2 #O 2 2 6#/-0 2%&%2%.#% '!).3934%- 2 * * (c) S 2 # u (c) S 2 2 u # S u %32 u #/54 6 2u 2 u u IN u 2u 2u # # # * * '6/3# S u %32 $#2 u #/54 S u , /54 u #/54 S u S u S 2 u # u # (c) 2 u # (c) '!0'03 The above figure shows the closed loop system with a TYPE III compensation network and presents the closed loop transfer function. See the guidelines for calculation of TYPE III network below: 1. Choose a value for R1, usually between 2 k and 5 k. 2. Choose a gain (R2/R1) that shifts the Open Loop Gain up to give the desired bandwidth. This allows the 0 dB crossover to occur in the frequency range where the Type III network has its second plateau in the gain. The following equation calculates an R2 that accomplishes this, given the system parameters and a chosen R1. Equation 9 2 3. C2 is calculated by placing the zero at 50% of the output filter double pole frequency: Equation 10 # 4. # 32/49 S u 2 u &,# C1 can be calculated by placing the first pole at the ESR zero frequency: Equation 11 5. $7" '6OSC u u 2 &,# 6). # u S u 2 u # u &%32 Set the second pole at half the switching frequency and also set the second zero at the output filter double pole. This combination brings the following equation: DocID028553 Rev 3 L5963 Application information Equation 12 2 2 # &37 u &,# S u 2 u &37 The figure below shows the asymptotic Bode gain plot for the TYPE III compensated system and the gain and phase equations for the compensated system Figure 15. TYPE III compensated network diagram '!). $" &: &,# &: &,# &0 &%32 &0 &37 %22/2 !-0 $# '!). #/.6%24%2 '!). /0%. ,//0 %22/2 !-0 '!). '!). "!.$7)$4( 02/$5#4 D"$%# -/$5,!4/2 &),4%2 '!). #/-0%.3!4)/. '!). &,# "!.$7)$4( &%32 &2%15%.#9 '!0'03 Here an example of calculating the external components network step by step. Suppose the requirements for a dc-dc regulator are the following: Input voltage minimum Vin(min) 8V Input voltage maximum Vin(max) 26 V Input voltage typical Vin(typ) 14 V Output voltage buck regulator 1- VBUCK 1 Min = 4.75 V, Max = 5.25 V Converter switching frequency, fsw 250 kHz Maximum output current on buck regulator 1-VBUCK 1 3A Maximum ripple current IRipple 0.3* Iout Load transition requirement 500 mA 1.5 A in t = TBD Assume TYPE III Compensation network. STEP 1 - Calculate the inductor value Using Equation 13, to find the inductor value, assume inductor ripple current of 0.9 A. Equation 13 ,t * 6OUT 6 OUT &37 u ' ), (c) 6IN MAX DocID028553 Rev 3 * (c) ( | ( u u 33/49 48 Application information L5963 The next higher available value should be used, so L = 22 H. STEP 2 - Inductor peak current Using Equation 14, the peak inductor current is: Equation 14 IL(peak) = Iout(max) + IL /2 = 3 A + (0.9/2) A= 3.45 A STEP 3 - Calculate the output capacitance Using Equation 15, the output capacitance is: Equation 15 #OUT , )OUT MAX )OUT MIN u '6OUT u 6OUT X u X X & So choose two 10 F ceramic capacitors in parallel, and the voltage ripple is within the spec. Equation 16 '6OUT %32 u '), ') , u #OUT u F SW (ESR can be neglect due to ceramic cap) 34/49 DocID028553 Rev 3 XXXX M6 L5963 Application information STEP 4 - Calculate loop compensation values. Using Equation 17 to determine the "double pole": Equation 17 F ,# S u , #OUT u u u u u K(Z Using Equation 18 to determine the zero due to the ESR of the output capacitor Cout with ESR = 10 m: Equation 18 F%32 S u #OUT u %32 u u u u u K(Z DBW = fc = 0.14 x fsw = 35kHz Choose R1 = 5 k, using Equation 19: Equation 19 2 2 6OUT 62%& K K: R4 =1.24 k PWM modulator gain. Equation 20 'AINMODULATOR 6). '6/3# Where VIN is the typical input operating voltage, VOSC is the saw-tooth peak-to-peak value. Using Equation 21: Equation 21 2 $"7 '6/3# u u 2 F ,# 6). K u u K K K R2 = 2.4 k Using Equation 22: Equation 22 # S 2 F,# u u u u u & Choose C2 = 16 nF Using Equation 23: Equation 23 # u u & S 2# F %32 u u u u u u u DocID028553 Rev 3 35/49 48 Application information L5963 Choose C1= 82 nF. Using Equation 24: Equation 24 2 2 F 37 F ,# K : u u u Choose R3 = 330 . Using Equation 25: Equation 25 # S 2 F37 u u u u & Choose C3 = 3.9 nF. This is a table to summarize components value for different output voltage cases: Table 8. Components value for different output voltage cases VOUT(V) 5 3.3 1.2 36/49 Fsw (Hz) Lo (H) Co (F) R1 (k) R2 (k) R3 () 2M 2.7 4.7 4.99 1.2 220 1.24 33 5.6 0.68 250k 22 2x10 4.99 2.4 390 1.24 82 16 3.9 2M 2.2 10 4.99 1.5 180 2.15 56 6.2 0.82 250k 15 2x10 4.99 2 470 2.15 100 16 3.3 2M 1.5 2x10 4.99 1.8 160 24.9 100 5.6 1 250k 6.8 2x10 4.99 1.2 680 24.9 150 16 2.2 DocID028553 Rev 3 R4 (k) C1 (pF) C2 (nF) C3 (nF) L5963 8 Thermal design Thermal design The PCB design should take into account also thermal aspects. The maximum power manageable by the IC depends on how the board is designed and on the package junction to ambient thermal resistance. The temperature inside the IC (junction temperature) should not exceed 150 C or one or more thermal shut-down protections intervene. The total power dissipation is approximately given by the sum of the power dissipation of the two dc-dc regulators and the linear regulator: Pd = Pdpwm1 + Pdpwm2 + Pdldo Where: PdissDC/DC = IloadDC/DC x VoutDC/DC x (1-)/; is the efficiency, as shown in Figure 7 and 8. PdissLDO = IloadLDO x (VINLDO-VOUTLDO) The junction temperature is estimated in this way: Tj = Ta + Pd x Rthj-a Where: Ta is the maximum ambient temperature; Rthj-amb is the junction to ambient thermal resistance, as defined in Table 5 and Table 6. The slug has to be connected to the ground plane, whenever possible. According to below formula and considering TSD_TH thermal shutdown minimum threshold at 150 C, maximum suggested power dissipation, for a slug-down configuration, can be easily retrieved: PDISS_suggested = (TSHD - Tamb) / Rthj-a Table 9. Maximum suggested power for L5963 in PSSO36 slug-down package Symbol Tamb 105 C Tamb 80 C Rth j-a-2s 0.85 W 1.32 W Rth j-a-2s2p 1.66 W 2.6 W Rth j-a-2s2pvias 2.05 W 3.2 W Table 10. Maximum suggested power for L5963 in QFN48 package Symbol Tamb 105 C Tamb 80 C Rth j-a-2s 0.68 W 1.06 W Rth j-a-2s2p 1.41 W 1.19 W Rth j-a-2s2pvias 1.73 W 2.7 W DocID028553 Rev 3 37/49 48 Thermal design L5963 It is possible to improve performance and application thermal behavior, adopting some expedients: Use the bottom layer as heat-sink, Shield inner layer tracks with ground planes, Use large paths for ground connections, instead of narrow and long paths with sharp corners, and transfer all ground connections to other layers by a proper number of vias, Place compensation network very close to the chip to reduce noise, Put coils and capacitors close to the pins, and build output path with large and short tracks. 38/49 DocID028553 Rev 3 L5963 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 9.1 Package variation This device use package Variations Option B to define exposed pad (see Table 11) or slug-up (see Table 12) dimensions. DocID028553 Rev 3 39/49 48 Package information 9.2 L5963 PowerSSO-36 (exposed pad) package information Figure 16. PowerSSO-36 (exposed pad) package outline %RWWRPYLHZ JJJ 0 & $% ' ' JJJ 0 &$% ' * * ( ( * ' H HHH & $ $ FFF & 6($7,1*3/$1( $ E 6HFWLRQ$$ & GGG 0 &' K K [ III & $% ' 5 + ' $ 1 % VHH6HFWLRQ%% 5 *$8*(3/$1( / % / ' $ 6 / LQGH[DUHD '[( *[ ( ( SLQLQGLFDWRU 6HFWLRQ%% ( E :,7+3/$7,1* * F F [ DDD &' E %$6(0(7$/ [17,36 EEE & % 7RSYLHZ $ VHH6HFWLRQ$$ 1 *$3*36 B,B(+ Table 11. PowerSSO-36 exposed pad package mechanical data Dimensions Ref 40/49 Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. 0 - 8 0 - 8 1 5 - 10 5 - 10 2 0 - - 0 - - A 2.15 - 2.45 0.0846 - 0.0965 DocID028553 Rev 3 L5963 Package information Table 11. PowerSSO-36 exposed pad package mechanical data (continued) Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A1 0.0 - 0.1 0.0 - 0.0039 A2 2.15 - 2.35 0.0846 - 0.0925 b 0.18 - 0.32 0.0071 - 0.0126 b1 0.13 0.25 0.3 0.0051 0.0098 0.0118 c 0.23 - 0.32 0.0091 - 0.0126 c1 0.2 0.2 0.3 0.0079 0.0079 0.0118 D (2) 10.30 BSC 0.4055 BSC D1 VARIATION D2 - 3.65 - - 0.1437 - D3 - 4.3 - - 0.1693 - e 0.50 BSC 0.0197 BSC E 10.30 BSC 0.4055 BSC 7.50 BSC 0.2953 BSC (2) E1 E2 VARIATION E3 - 2.3 - - 0.0906 - E4 - 2.9 - - 0.1142 - G1 - 1.2 - - 0.0472 - G2 - 1 - - 0.0394 - G3 - 0.8 - - 0.0315 - h 0.3 - 0.4 0.0118 - 0.0157 L 0.55 0.7 0.85 0.0217 - 0.0335 L1 1.40 REF 0.0551 REF L2 0.25 BSC 0.0098 BSC N 36 1.4173 R 0.3 - - 0.0118 - - R1 0.2 - - 0.0079 - - S 0.25 - - 0.0098 - - DocID028553 Rev 3 41/49 48 Package information L5963 Table 11. PowerSSO-36 exposed pad package mechanical data (continued) Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. Tolerance of form and position aaa 0.2 0.0079 bbb 0.2 0.0079 ccc 0.1 0.0039 ddd 0.2 0.0079 eee 0.1 0.0039 ffff 0.2 0.0079 ggg 0.15 0.0059 VARIATIONS Option A D1 6.5 - 7.1 0.2559 - 0.2795 E2 4.1 - 4.7 0.1614 - 0.1850 D1 4.9 - 5.5 0.1929 - 0.2165 E2 4.1 - 4.7 0.1614 - 0.1850 D1 6.9 - 7.5 0.2717 - 0.2953 E2 4.3 - 5.2 0.1693 - 0.2047 Option B Option C 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is `0.25 mm' per side D and `0.15 mm' per side E1. D and E1 are Maximum plastic body size dimensions including mold mismatch. 42/49 DocID028553 Rev 3 L5963 PowerSSO-36 (slug-up) package information $ $ Figure 17. PowerSSO-36 (slug-up) package outline 1 *DXJHSODQH & & $ ' %RG\OHQJWK N /($'&203/$1$5,7< DVWDQGRII * & 1 < H / 7239,(: 6 ; 2 ( %RG\ZLGWK + 8 8 7 ) 9.3 Package information % 0 $ % 0 E H *$3*36 B(B.% Table 12. PowerSSO-36 slug-up package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.0846 - 0.0965 A2 2.15 - 2.35 0.0846 - 0.0925 a1 0 - 0.10 - 0.0039 b 0.18 - 0.36 0.0071 - 0.0142 c 0.23 - 0.32 0.0091 - 0.0126 (2) 10.10 - 10.50 0.3976 - 0.4134 (2) 7.4 - 7.6 0.2913 - 0.2992 e - 0.5 - - 0.0197 - e3 - 8.5 - - 0.3346 - D E DocID028553 Rev 3 43/49 48 Package information L5963 Table 12. PowerSSO-36 slug-up package mechanical data (continued) Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. F - 2.3 - - 0.0906 - G - - 0.10 - - 0.0039 H 10.10 - 10.50 0.3976 - 0.4134 h - - 0.40 - - 0.0157 k 0 - 8 0 - 8 L 0.55 - 0.85 0.0217 - 0.0335 M - 4.3 - - 0.1693 - N - - 10 - - 10 O - 1.2 - - 0.0472 - Q - 0.8 - - 0.0315 - S - 2.9 - - 0.1142 - T - 3.65 - - 0.1437 - U - 1.0 - - 0.0394 - X See VARIATIONS Y See VARIATIONS VARIATIONS Option A X 4.1 - 4.7 0.1614 - 0.1850 Y 6.5 - 7.1 0.2559 - 0.2795 X 4.1 - 4.7 0.1614 - 0.1850 Y 4.9 - 5.5 0.1929 - 0.2165 X 4.3 - 5.2 0.1693 - 0.2047 Y 6.9 - 7.5 0.2717 - 0.2953 Option B Option C 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side (0.006") 44/49 DocID028553 Rev 3 L5963 VFQFPN-48 (7x7x1.0 - opt. D) package information Figure 18. VFQFPN-48 (7x7x1.0 - opt. D) package outline $ % ,1'(;$5($ & 5 ( ' ' 5HI / $ ( $ H E & ; GGG & & $ 5HI ; 7HUPLQDO/HQJWK '(7$,/$ 5HI 9.4 Package information 0 & $ % 5HI 7HUPLQDO7KLFNQHVV 5HI 5HI 5HI '(7$,/$ 127( $//',0(16,216$5(,1PP$1*/(6,1'(*5((6 &23/$1$5,7<$33/,(6727+((;326('3$'$6:(//$67+(7(50,1$/6 &23/$1$5,7<6+$//127(;&(('PP :$53$*(6+$//127(;&(('PP 5()(5-('(&02 5HI *$3*36 B*B9 2SW& DocID028553 Rev 3 45/49 48 Package information L5963 Table 13. VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A 0.85 0.95 1.05 0.0335 0.0374 0.0413 A1 - - 0.05 - - 0.0020 A2 - 0.75 - - 0.0295 - A3 - 0.200 - - 0.0079 - b 0.15 0.25 0.35 0.0059 0.0098 0.0138 D 6.80 7.00 7.15 0.2697 0.2756 0.2815 D2 5.15 5.30 5.45 0.2028 0.2087 0.2146 E 6.85 7.00 7.15 0.2697 0.2756 0.2815 E2 5.15 5.30 5.45 0.2028 0.2087 0.2146 e 0.45 0.50 0.55 0.0177 0.0197 0.0217 L 0.45 0.50 0.55 0.0177 0.0197 0.0217 ddd - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 9.5 Package marking information Figure 19. PowerSSO-36 (exp. pad) marking information 0DUNLQJDUHD /DVWWZRGLJLWV (6(QJLQHHULQJVDPSOH EODQN!&RPPHUFLDOVDPSOH 3RZHU6627239,(: QRWLQVFDOH 46/49 DocID028553 Rev 3 *$3*36B(6 L5963 Package information Figure 20. PowerSSO-36 (slug up) marking information 0DUNLQJDUHD /DVWWZRGLJLWV (6(QJLQHHULQJVDPSOH EODQN!&RPPHUFLDOVDPSOH 3RZHU6627239,(: QRWLQVFDOH *$3*36B(6 Figure 21. VFQFPN-48 (7x7x1.0) marking information 0DUNLQJDUHD /DVWWZRGLJLWV (6(QJLQHHULQJVDPSOH EODQN!&RPPHUFLDOVDPSOH *$3*36 Parts marked as `ES' are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. DocID028553 Rev 3 47/49 48 Revision history 10 L5963 Revision history . 48/49 Table 14. Document revision history Date Revision Changes 29-Oct-2015 1 Initial release. 21-Nov-2016 2 Added: - "Automotive" in the title, AEC-Q100 qualifed in the feature and car icon, in cover page, - Two order codes in Table 1: Device summary on page 1. - Figure 5: VQFPN-48 pinout configuration on page 12, - Table 3: VQFPN-48 pins description on page 12, - Table 6: Thermal data (VQFPN-48) on page 14 - Chapter 9.4: VFQFPN-48 (7x7x1.0 - opt. D) package information on page 45 - Figure 21: VFQFPN-48 (7x7x1.0) marking information on page 47. Updated: - Section 1: Overview on page 6, - Section 3: Application diagrams,Table 2: PowerSSO-36 pins description, - Table 7: Electrical characteristics - Section 6.2.2 on page 19, - Section 6.2.5 on page 20, - Pulse-by-pulse current limiting (OCP) on page 27, - Figure 8: Thermal design on page 37, - Section 8: Thermal design. 16-Jun-2017 3 Updated order codes in Table 1: Device summary on page 1 DocID028553 Rev 3 L5963 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID028553 Rev 3 49/49 49