FUJITSU SEMICONDUCTOR DATA SHEET DS04-27204-6E ASSP BIPOLAR SWITCHING REGULATOR CONTROLLER MB3775 LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM control circuits. Complete synchronization is obtained by using the same oscillator output waveform. This IC can provide following types of output voltage: step down, step up, and inverter. Power consumption is low, thus the MB3775 is ideal for use in high-efficiency portable equipment. FEATURES * * * * * * * * Wide supply voltage range: 3.6 V to 18 V Low current consumption: 1.3 mA typical Wide oscillation frequency range: 1 kHz to 500 kHz On-chip timer latch short protection circuit On-chip under voltage lockout protection On-chip reference voltage: 1.28 V Variable dead time provides control over total operating range. Two types of packages (SOP-16pin : 1 type, SSOP-16pin : 1 type) APPLICATIONS * LCD monitor/panel * Surveillance camera etc. Copyright(c)1994-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.9 MB3775 PIN ASSIGNMENT (TOP VIEW) CT 1 16 VREF RT 2 15 SCP +IN1 3 14 +IN2 -IN1 4 13 -IN2 FB1 5 12 FB2 D.T.C.1 6 11 D.T.C.2 OUT1 7 10 OUT2 E/GND 8 9 VCC (FPT-16P-M06) (FPT-16P-M05) 2 DS04-27204-6E MB3775 PIN DESCRIPTION No. Pin Function 1 CT Oscillator timing capacitor pin (150 pF to 15,000 pF) . 2 RT Oscillator timing resistor pin (5.1 k to 100 k) . 3 +IN1 Error amplifier 1 non-inverted input pin. 4 -IN1 Error amplifier 1 inverted input pin. 5 FB1 Error amplifier 1 output pin. A resistor and a capacitor are connected between this pin and the -IN1 pin to adjust gain and frequency. 6 DTC1 OUT1 dead-time control pin. Dead-time control is adjusted by an external resistive divider connected to the VREF pin. A capacitor connected between this pin and GND enables soft-start operation. 7 OUT1 Open collector output pin. Output transistor has common ground independent of signal ground. This output can source or sink up to 50 mA. 8 E/GND Ground pin. 9 VCC 10 OUT2 Open collector output pin. Output transistor has common ground independent of signal ground. This output can source or sink up to 50 mA. 11 DTC2 Sets the dead-time of OUT2. The use of this pin is the same as that of DTC1. 12 FB2 Error amplifier 2 output pin. A resistor and a capacitor are connected between this pin and the -IN2 pin to adjust gain and frequency. 13 -IN2 Error amplifier 2 inverted input pin. 14 + IN2 Error amplifier 2 non-inverted input pin. 15 SCP The time constant setting capacitor connection pin of the timer latch short-circuit protection circuit. Connects a capacitor between this pin and GND. For details, see " HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT PROTECTION CIRCUIT". 16 VREF 1.28 V reference voltage output pin which can be obtained up to 1 mA. This pin is used to set the reference input and idle period of the error amplifiers. DS04-27204-6E Power supply pin (3.6 V to 18 V) 3 MB3775 BLOCK DIAGRAM 9 16 V REF = 1.28 V 1 V CC Reference Voltage 1.9 V Triangular Waveform 1.3 V Error Amp 1 + - - + + - - 7 PWM Comp.1 S.C.P.Comp. + OUT 1 + - - 2.5 V 3 4 5 12 2 OUT 2 10 PWM Comp.2 1.1 V Error Amp 2 14 13 + - 2.5 V 15 1.28 V 1 A S R Latch 0.9 V 0.9 V R U.V.L.O. + + D.T.C.Comp. GND - 8 1.8 V 6 4 11 DS04-27204-6E MB3775 OPERATION DESCRIPTION 1. Reference voltage The reference voltage circuit generates a stable, temperature-compensated 2.5 V reference from Vcc pin (pin 9) for use by internal circuits. A reference voltage of temperature compensated 1/2 VREF can be obtained to external circuit by VREF pin (pin 16). 2. Oscillator A triangular waveform of any frequency is obtained by connecting an external capacitor and resistor to the CT pin (pin 1) and RT pin (pin 2). The amplitude of this waveform is from 1.3 V to 1.9 V. The oscillator is internally connected to the non-inverting inputs of the PWM comparators. The oscillator waveform is available at the CT pin (pin 1). 3. Error amplifiers The error amplifier detects the output voltage of the switching regulator. The common-mode input voltage range is -0.2 V to 1.45 V, so the input reference voltage can be set the VREF pin (pin 16) and GND pin levels. Error amplifiers can be used as either inverting and non-inverting amplifiers. The voltage gain is fixed. Phase compensation is possible by connecting a capacitor to the FB pins (pins 5 and 12) of the error amplifiers. The error amplifier output are internally connected to the inverting inputs of the PWM comparators and also to the short protection circuit. 4. Timer latch short protection circuit The timer latch short protection circuit detects the output levels of the error amplifiers. If one or both error amplifier outputs are 1.1 V or lower, the timer circuit begins charging the externally connected protection enable capacitor. If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage reaches the transistor base-emitter voltage VBE ( =: 0.65 V), the latch circuit turns the output drive transistor off and sets the dead time to 100 %. 5. Under voltage lockout protection circuit An ambiguous transition state at power-on or a momentary fluctuation in the supply line may result in loss of control and may adversely affect or even destroy the system. The under voltage lockout protection circuit compares the internal reference voltage level with the supply voltage level. If the supply voltage level falls below the reference level the latch circuit is reset the output drive transistor is turned off and the dead time is set to 100%. The protection enable pin (pin 15) is pulled "Low". 6. PWM comparator Each PWM comparator has two inverting inputs and one non-inverting input. This voltage-to-pulse-width converter controls the output pulse width according to the input voltage. The PWM comparator turns the output drive transistor on when the oscillator triangular waveform is higher than the error amplifier output and the dead time control pin voltage. 7. Output drive transistor The open-collector output-drive transistors provide common-emitter output of 18 V dielectric capability. The output drive transistors can source up to 50 mA of drive current to the switching power transistor. DS04-27204-6E 5 MB3775 ABSOLUTE MAXIMUM RATING Parameter Symbol Condition VCC Error Amp Input Voltage Rating Unit Min Max 20 V VI -0.3 +10 V Collector Output Voltage VO 20 V Collector Output Current IO 75 mA Power Dissipation PD Ta +25 C(SOP) *620 mW Ta +25 C(SSOP) *430 mW Operating Ambient Temperature Ta -30 +85 C Storage temperature Tstg -55 +125 C Power Supply Voltage *: The packages are mounted on the epoxy board (4 cm x 4 cm x 1.5 mm). WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max VCC 3.6 6.0 18 V Error Amp Input Voltage VI -0.2 +1.45 V Collector Output Voltage VO 18 V Collector Output Current IO 0.3 50 mA Phase Compensation Capacitor CP 0.1 F Timing Capacitor CT 150 15000 pF Timing Resistor RT 5.1 100 k Oscillator Frequency fOSC 1 500 kHz Reference Voltage Output Current IREF -3 -1 mA Ta -30 +25 +85 C Power Supply Voltage Operating Ambient Temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 6 DS04-27204-6E MB3775 ELECTRICAL CHARACTERISTICS (Ta = +25 C, VCC = 6 V) Parameter Reference Section Under Voltage Lockout Protection Section Protection Circuit Section Triangular Waveform Oscillator Section Dead-Time Control Section Condition Symbol Value Min Typ Max Unit Output Voltage IOR = -1 mA VREF 1.26 1.28 1.30 V Output Temp. Stability Ta = -30 C to +85 C VRTC -2 0.2 +2 % Input Stability VCC = 3.6 V to 18 V Line 2 10 mV Load Stability IOR = -0.1 mA to -1 mA Load 1 7.5 mV Short Circuit Output Current VREF = 0 V IOS -30 -10 mA IOR = -0.1 mA VtH 2.72 V IOR = -0.1 mA VtL 2.60 V IOR = -0.1 mA VHYS 80 120 mV Threshold Voltage Hysteresis Width Reset Voltage (VCC) VR 1.5 1.9 V Input Threshold Voltage VtPC 0.60 0.65 0.7 V Input Stand by Voltage No pull up VSTB 50 100 mV Input Latch Voltage No pull up VI 50 100 mV Ibpc -1.4 -1.0 -0.6 A Input Source Current Comparator Threshold Voltage Pin 5, Pin 12 VtC 1.1 V Oscillator Frequency CT = 330 pF, RT = 15 k fOSC 200 kHz Frequency Deviation CT = 330 pF, RT = 15 k fdev 10 % fdV 1 % Frequency Stability (VCC) VCC = 3.6 V to 18 V Frequency Stability (Ta) Ta = -30 C to +85 C fdT -4 - +4 % Input Threshold Voltage (fOSC = 10 kHz) Duty Cycle = 0 % Vt0 1.0 VREF -0.15 V Vt100 0.2 0.4 V Ibdt -0.2 -1 A Duty Cycle = 100 % Input Bias Current Latch Mode Source Current Vdt = 0.7 V Idt -150 -80 A Latch Input Voltage Idt = -40 A Vdt VREF -0.1 V (Continued) DS04-27204-6E 7 MB3775 (Continued) (Ta = +25 C, VCC = 6 V) Parameter Condition Value Min Typ Max Unit Input Offset Voltage VO = 1.6 V VIO -10 +10 mV Input Offset Current VO = 1.6 V IIO -100 +100 nA Input Bias Current VO = 1.6 V IB -500 -100 nA Common Mode Input Voltage Range VCC = 3.6 V to 18 V VICR -0.2 +1.45 V AV 84 120 V/V BW 3 MHz CMRR 60 80 dB VOM+ 2.2 2.4 V VOM- - 0.7 0.9 V Voltage Gain Error Amp Section Symbol Frequency Band Width AV = -3 dB Common Mode Rejection Ratio Max Output Voltage Width Output Sink Current VO = 1.6 V IOM+ 24 50 A Output Source Current VO = 1.6 V IOM- -1.2 -0.7 mA Input Threshold Voltage (fOSC=10 kHz) Duty Cycle = 0 % Vt0 1.9 2.1 V Duty Cycle = 100 % Vt100 1.05 1.3 V Input Sink Current Pin 5, Pin 12 = 1.6 V IIN+ 24 50 A Input Source Current Pin 5, Pin 12 = 1.6 V IIN- -1.2 -0.7 mA Output Leak Current VO = 18 V Leak 10 A Output Saturation Voltage IO = 50 mA VSAT 1.1 1.4 V Stand by Current Output "OFF" ICCS 1.3 1.8 mA Average Supply Current RT = 15 k ICCa 1.7 2.4 mA PWM Comparator Section Output Section 8 DS04-27204-6E MB3775 TEST CIRCUIT VCC=6 V INPUT TEST SW 4.7 k CPE OUTPUT 1 4.7 k OUTPUT 2 16 15 14 13 12 11 10 9 6 7 8 MB3775 1 2 3 4 5 0.1 F 330 pF 15 k TEST INPUT TIMING CHART (Internal Waveform) Error Amp output Triangular waveform oscillator output 1.9 V Dead Time PWM 1.5 V input voltage 1.3 V Short circuit protection 1.1 V comparator Reference input "High" PWM comparator output "Low" Output Transistor collector waveform SCP Pin waveform "High" LOCK-OUT DEAD TIME 100% "Low" 0.6 V tPE 0V Short circuit protection "High" comparator output "Low" LOCK-OUT CANCEL Power supply voltage 3.6 V (VCC : Min Value) 2.8 V (Typ Value) 0V Protection Enable Time tPE =: 0.6 x 106 x CPE (s) DS04-27204-6E 9 MB3775 APPLICATION CIRCUIT Fig. 1 - Chopper Type Step Down/Inverting VIN (10 V) 820 pF 10 k 1 16 2 15 3 14 4 13 0.1 F 56 H 2.3 k 0.1 F 33 k + - 33 k 1 F 33 k MB3775 5 12 6 11 7 10 8 9 1.9 k 0.1 F 33 k - + 220 F + - 1 F 5.6 k 330 330 120 H - - + 220 F 9.1 k V0- (-5 V) 470 470 120 H + 220 F GND V0+ (+5 V) Fig. 2 - Chopper Type Step Up/Inverting VIN (5 V) 820 pF 1 16 2 15 3 14 0.1 F 10 k 2.3 k 4 5 12 6 11 7 10 8 9 0.1 F 33 k + - 13 MB3775 33 k 1 F 33 k 56 H 1.9 k 0.1 F 33 k - 220 F + - 1 F + 16 k 330 3.9 k 120 H 330 120 H - 100 - + 220 F 220 F 9.1 k V0- (-5 V) + GND V0+ (+12 V) (Continued) 10 DS04-27204-6E MB3775 (Continued) Fig. 3 - Chopper Type Step Up/Inverting (For High Speed) VIN (5 V) 820 pF 1 16 2 15 3 14 0.1 F 10 k 2.3 k 4 33 k 0.1 F 33 k + - 13 MB3775 5 12 6 11 7 10 8 9 - 0.1 F 33 k 1 F 33 k 470 + - 56 H 1.9 k + 220 F 16 k 1 F 220 - 470 470 120 H 9.1 k 330 pF 33 k - 33 k - + 220 F V0- (-5 V) 150 120 H 470 1 F + + 220 F GND V0+ (+12 V) Fig. 4 - Multi Output Type (Apply Transformer) VIN (10 V) 820 pF 1 16 2 15 3 14 4 13 0.1 F 10 k MB3775 5 12 6 11 7 10 8 9 56 H 5.6 k 1.9 k 0.1 F 0.1 F - 33 k + 220 F 1.8 k 1 nF 33 k - - + 220 F V02(-12 V) DS04-27204-6E 220 - + 220 F V01(-5 V) - + 220 F GND + 220 F V02+ (+5 V) V01+ (+12 V) 11 MB3775 HOW TO SET OUTPUT VOLTAGE The output voltage is set using the connection shown in Fig. 5 and 6. The error amplifiers are supplied to the internal reference voltage circuit as are the other internal circuits. The common-mode input voltage range is from -0.2 V to +1.45 V. When the amplifiers are operated non-inverting, tie the inverting pin to VREF ( =: 1.28 V). When the amplifiers are operated inverting, tie the non-inverting pin to ground. Fig. 5 -Connection of Error Amp Output Voltage V0 is plus R2 V0+ [V0+ = VREF X (1 + R2/R1)] + PIN 5 or PIN 12 - R1 VREF Fig. 6 -Connection of Error Amp Output Voltage V0 is minus R2 V0- [V0- = -VREF X (R2/R1)] - PIN 5 or PIN 12 R1 + VREF 12 DS04-27204-6E MB3775 HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT TIMING CHART shows the configuration of the protection latch circuit. Error amplifier outputs, are internally connected to the non-inverting inputs of the short-circuit protection comparator and are compared with the reference voltage (1.1 V) connected to the inverting input. When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus, short-circuit protection control is also kept in balance, and the protection enable pin (pin 15) voltage is kept at about 50 mV. If the load condition drastically changes due to a load short-circuit and if low-level signals (1.1 V or lower) are input to the non-inverting inputs of the short-circuit protection comparator from the error amplifiers, the shortcircuit protection comparator outputs a "Low" level to turn transistor Q1 off. The protection enable pin voltage is discharged, and then the short-circuit protection comparator charges the externally connected protection enable capacitor CPE according to the following formula: VPE = 50 mV + tPE x 10-6/CPE 0.65 = 50 mV + tPE x 10-6/CPE CPE = tPE/0.6 (F) When the protection enable capacitor charges to about 0.65 V, the protection latch is set to enable the under voltage lockout protection circuit and to turn the output drive transistor off. The dead time is set to 100 %. Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the protection latch is not reset if the power is not turned off. The non-inverting inputs of the D.T.C. comparator are connected to the D.T.C. pins (pins 6 and 11) through the power supply (about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the inverting input. To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. pins), the D.T.C. comparator outputs a "High" level to turn Q2 on until the D.T.C. pins (pins 6 and 11) voltage drops to about 0.9 V. Fig. 7 - Protection Latch Circuit 2.5 V 1 A S.C.P.Comp. R1 Error Amp1 Error Amp2 SCP 15 + + - CPE Q1 Q2 Q3 S R U.V.L.O. Latch 1.1 V + + 0.9 V - D.T.C.Comp. DS04-27204-6E 0.9 V 1.8 V 6 D.T.C.1 11 D.T.C.2 13 MB3775 SETTING THE IDLE PERIOD When voltage step-up, fly-back step-up or inverted output are set, the voltage at the FB pin may go lower than the triangular wave voltage due to load fluctuation, etc. In this case the output transistor will be in full-on state (ON duty 100%). This can be prevented by setting the maximum duty for the output transistor. This is done by setting the DTC1 pin (pin 6) voltage using resistance division of the VREF voltage as illustrated below. When the DTC1 pin voltage is lower than the triangular waveform voltage, the output transistor is turned on. If the triangular waveform amplitude =: 0.6 V, the lower limit voltage of the triangular waveform =: 1.3 V and the offset voltage is 0.9 V, the formula for the maximum duty would be as follows (Other channels are this conditions) : 1.9 V - (Vdt + 0.9 V) 1.0 V - Vdt Rb Duty (ON) Max (%) =: x 100 =: x 100, Vdt (V) = x VREF 0.6 V 0.6 V (Ra + Rb) Also, if no output duty setting is required, the voltage should be set greater than the lower limit voltage of the triangular waveform, which is 1.3 V (Vdt = 0.4 V). * Setting the idle time at DTC1 (DTC2 is similar) VREF 16 Ra DTC1 6 Rb Vdt 14 DS04-27204-6E MB3775 VCC and VO VO x 100 Vcc VO - Vcc = x 100 VO VO = x 100 VO - Vcc * Step down DUTY[%] = * Step up DUTY[%] * Inverter DUTY[%] Set the DTC voltage using the following Duty Max vs. Vdt characteristics so that this duty is set to the maximum duty or less. Duty Max [%] 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1.0 Vdt [V] Duty Max vs. Vdt characteristics (applies to Vdt 1 and Vdt 2) DS04-27204-6E 15 MB3775 SETTING THE SOFT START TIME When power is switched on, the current begins charging the capacitor (CDTC1) connected the DTC1 pin (pin 6). The soft start process operates by comparing the soft start setting voltage, which is proportional to the DTC1 pin voltage, with the triangular waveform, and varying the ON-duty of the OUT pin (pin 7). The soft start time until the ON duty reaches 50% is determined by the following equation: Soft start time (time until output ON duty = 50%) . ts (s) =: - CDTC1 x Ra x Rb / (Ra + Rb) x ln (1 - 0.7 (Ra + Rb) / (1.28 Ra) ) For example, if Ra = 10 k and Rb = 4.7 k, the result is: ts (s) =: 0.005 x CDTC1 (F) * Soft Start on DCT1 pin (DTC2 is similar) VREF 16 Ra DTC1 CDTC1 6 Rb 16 DS04-27204-6E MB3775 SYNCHRONIZATION OF ICs To synchronize MB3775 ICs, first, the specified capacitor and resistor are connected to the CT and RT pins (pins 1 and 2) of the master IC to start self oscillation. Next, 2 V is applied to the RT pin (pin 2) of the slave ICs to disable the charge/discharge circuit for triangular wave oscillation. Finally, the CT pin (pin 1) of the master and slave ICs are connected. Instead of applying VRT to the RT pin (pin 2), these pins can be pulled up by a resistor (see resistance indicated by the dashed line in Fig. 8). Select the pull-up resistance Rpull from the formula given below. VCC Rpull 0.5 x N Rpull: Pull up Resistor (k) VCC: Power Supply Voltage (V) N: Number of Slave ICs Fig. 8 - Connection of Master, Slave MB3775 VCC (MASTER) Rpull CT RT MB3775 (SLAVE) VRT 2V MB3775 (SLAVE) DS04-27204-6E 17 MB3775 TYPICAL PERFORMANCE CHARACTERISTICS Fig. 9 - Reference voltage vs. Power supply voltage 1.5 1.0 0.5 0 5 10 15 Power supply voltage VCC (V) 1.0 0.5 0.5 5 10 15 Power supply voltage VCC (V) 20 1.28 1.27 1.26 1.25 0 5 10 15 Power supply voltage VCC (V) -30 20 Fig. 13 - Collector saturation voltage vs. Sink current 3.0 Error Amp Max output voltage VOM (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 +0 +30 +60 +90 Operating ambient temperature Ta ( C) Fig. 14 - Error Amp Max output voltage vs. Frequency 3.5 Collector saturation voltage VSAT (V) 1.0 Fig. 12 - Reference voltage vs. Operating ambient temperature 1.29 Reference voltage VREF (V) 1.5 1.5 0 20 Fig. 11 - Stand by current vs. Power supply voltage 2.0 Stand by current ICCS (mA) Fig. 10 - Average supply current vs. Power supply voltage 2.0 Average supply current I CCa (mA) Reference voltage VREF(V) 2.0 50 100 150 200 250 300 Sink current lO (mA) 350 2.0 1.0 0 100 1k 10k 100k Frequency f (Hz) 1M (Continued) 18 DS04-27204-6E MB3775 Fig. 15 - Oscillation Frequency vs. Timing resistor Fig. 16 - Triangular waveform cycle vs. Timing capacitor 103 Triangular waveform cycle ( s) 100k 10k CT = 150 pF CT = 1500 pF 1k 10k 100k 1M Timing resistor RT () 1k Timing resistance = 15 k VCC = 6 V 100 10-1 101 10M Fig. 17 - Triangular waveform Max Amplitude voltage vs. Timing capacitor 2.2 102 103 104 Timing capacitor CT (pF) 105 Fig. 18 - Gain/Phase vs. Frequency 60 Timing resistance=15 k VCC = 6 V 180 2.0 40 1.8 20 90 0 0 1.6 1.4 -20 1.2 -40 1.0 102 103 104 Timing capacitor CT (pF) 101 60 40 90 20 Gain AV 0 Phase -20 -90 -40 -180 -60 100 101 102 103 104 105 Frequency f (Hz) 106 107 Gain A V(dB) 180 0 100k Frequency f (Hz) 90 10M 1M Fig. 20 - Gain/Phase vs. Frequency (Actual Data) Phase (deg) 20 10k 1k CFB = 1 F 40 -90 -180 -60 105 Fig. 19 - Gain/Phase vs. Frequency (Actual Data) 60 Phase Phase (deg) Gain AV Gain AV(dB) Triangular waveform Max Amplitude voltage (V) 101 CT = 15000 pF 100 Gain AV(dB) 102 CFB = 0.1 F 180 90 Gain AV 0 0 Phase -20 -90 -40 -180 -60 100 101 102 103 104 105 Frequency f (Hz) 106 Phase (deg) Oscillation Frequency fOSC (Hz) 1M 107 (Continued) DS04-27204-6E 19 MB3775 (Continued) Fig. 21 - Gain/Phase vs. Frequency (Actual Data) 60 CFB=0.01 F Gain AV (dB) 90 20 Gain AV 0 0 Phase -20 -90 -40 -180 Phase (deg) 180 40 -60 100 20 101 102 103 104 105 Frequency f (Hz) 106 107 DS04-27204-6E MB3775 HOW TO SET THE ERROR AMPLIFIER FREQUENCY CHARACTERISTIC Figure 22 shows the equivalent circuit of the error amplifier. The frequency characteristic of the error amplifier is set by R1, R2, and CP. The high-frequency gain is set by the ratio of resistors R1 and R2 in the IC (set value 0 dB). When CP = 0.1 F, the gain at 20 kHz f 5 MHz is about 0 dB. The roll-off frequency is adjusted by changing external phase compensating capacitor CP (see Fig. 24). When high frequency gain is needed or the phase must be advanced at a low frequency, connect a resistor RP between the FB pins (pins 5 and 12) and CP as shown in Figure 23 (see Fig. 25). Fig. 22 - Error Amp Equivalent Circuit Error Amp [- IN] - R1 38 k x 120 [+ IN] PWM COMP R2 470 + [FB] CP Fig. 23 - Error Amp Equivalent Circuit (Insert RP) Error Amp [- IN] - R1 38 k x 120 [+ IN] PWM COMP R2 470 + [FB] RP CP Note: As shown above, the frequency characteristic of the error amplifier is set by the external phase compensating capacitor CP. When a ceramic chip capacitor must be used to meet the requirements of a small system, be careful of its . . temperature characteristic. (-30 C =.1/5 and +80 C =.1/3 for the frequency characteristic, so a sufficient phase margin must be allowed for at room temperature.) Ceramic chip capacitors with a low temperature characteristic (B characteristic) or film capacitors are recommended (see Fig. 26 to 28). DS04-27204-6E 21 MB3775 Fig. 24 - Error Amp Frequency characteristics 60 AV CP = 0.1 F 180 40 (Large) (Small) 90 0 0 (Small) -20 Phase (deg) Gain AV (dB) 20 -90 (Large) CP = 0.1 F -40 -180 -60 10 100 1k 10k 100k 1M 10M 100M Frequency f (Hz) Fig. 25 - Error Amp Frequency characteristics 60 CP = 0.1 F 40 180 20 90 RP=0 (Large) 0 0 (Large) Phase (deg) Gain AV (dB) AV -90 -20 RP=0 -180 -40 -60 10 100 1k 10k 100k 1M 10M 100M Frequency f (Hz) 22 DS04-27204-6E MB3775 Fig. 26 - Ceramic Chip Capacitor (0.1 F) Temp. characteristic Temp. : Ratio -30C : 0.19 +25C : 1.0 +80C : 0.32 Gain AV (dB) 10 90 -30C 0 0 AV -10 +80C +25C -90 Phase (deg) 20 -30C +25C +80C -20 1k 10k 100k 1M Frequency f (Hz) Fig. 27 - Tantal Capacitor (0.33 F) Temp. characteristic Temp. : Ratio -30C : 0.95 to 1.05 +25C : 1.0 +80C : 0.95 to 1.05 Gain AV (dB) 10 90 AV 0 0 -30C +25C -10 Phase (deg) 20 +80C -20 +25C +80C 1k 10k -90 -30C 100k 1M Frequency f (Hz) Fig. 28 - Film Capacitor (0.1 F) Temp. characteristic 10 Gain AV (dB) -30C : 0.9 to 1.1 +25C : 1.0 +80C : 0.9 to 1.1 AV 0 0 -30C, +25C, +80C -10 -30C, -90 +25C +80C -20 1k DS04-27204-6E 90 Phase (deg) 20 10k Frequency f (Hz) 100k 1M 23 MB3775 EFFECT OF EQUIVALENT SERIES RESISTANCE OF SMOOTHING CAPACITOR The equivalent series resistance (ESR) of the smoothing capacitor in the DC/DC converter greatly affects the loop phase characteristic. A smoothing capacitor with a low ESR reduces system stability by increasing the phase shift in the high-frequency region (see Fig. 30). Therefore, a smoothing capacitor with a high ESR will improve system stability. Be careful when using low ESR semiconductor electrolytic capacitors (OS-CONTM) and tantalum capacitors. Note: OS-CON is the trademark of Sanyo Electric Co., Ltd. Fig. 29 - Step Down DC/DC Converter Basic Circuit L Tr RC VIN D RL C Fig. 30 - Gain vs. Frequency Fig. 31 - Phase vs. Frequency 20 0 -20 (2) -40 -60 10 (1) : RC = 0 (2) : RC = 31 m 100 1k 10k (2) -90 -180 (1) Frequency f (Hz) 24 Phase (deg) Gain A V (dB) 0 100k 10 (1) : RC = 0 (2) : RC = 31 m 100 (1) 1k 10k 100k Frequency f (Hz) DS04-27204-6E MB3775 Reference data If an aluminum electrolytic smoothing capacitor (RC 1.0 ) is replaced with a low ESR semiconductor electrolytic capacitor (OS-CONTM: RC 0.2 ), the phase shift is reduced by half (see Fig. 33 and 34). Fig. 32 - DC/DC Converter AV vs. characteristic Test Circuit VOUT V0+ AV vs. characteristic Between this point. + IN + FB VIN - IN - R2 ~ R1 0.1 F VREF Error Amp Fig. 33 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 VCC=10 V RL=25 CP=0.1 F Gain A V (dB) AV 180 V0+ 20 90 +62 0 Phase (deg) 40 0 -20 + AI Capacitor 220 F(16 V) 1.0 : fosc=1 kHz RC - -90 -40 10 100 1k Frequency f (Hz) 10k 100k GND -180 Fig. 34 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 20 180 90 +27 0 0 -90 -20 -40 10 Phase (deg) 40 Gain A V (dB) VCC=10 V RL=25 CP=0.1 F AV 100 1k 10k 100k V0+ OS-CONTM 22 F(16V) - RC 0.2 : fosc=1 kHz + GND -180 Frequency f (Hz) DS04-27204-6E 25 MB3775 MEASURES FOR ENSURING SYSTEM STABILITY WHEN A LOW ESR SMOOTHING CAPACITOR IS USED When a low ESR smoothing capacitor is used in the DC/DC converter, only the L and C are apparent even in the high-frequency region, and the phase is delayed by almost 180. Consequently, the system phase margin and stability are reduced. On the other hand, a low ESR capacitor is needed to reduce the amount of output ripple. This is contrary to the system stability explained above. To solve this problem, phase compensation can be used. This method increases the phase margin by advancing the phase when the phase margin is reduced by a low ESR capacitor. The three suggestions listed below are recommended for DC/DC converters using the MB3775. (1) As shown in Fig. 35, a capacitor is connected in parallel with the output feedback resistor to advance the phase. Use the formula below as a guideline for the capacitance. C1 1 2fR2 Unstable Frequency (See Fig. 32) Fig. 35 - External circuit example1 to advance the phase C1 V0+ R2 + IN + - IN R1 FB - CP VREF Fig. 36 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 20 0 -20 -40 10 26 180 AV 100 90 VCC = 10 V RL = 25 CP = 0.1 F Smoothing Capacitor 22 F OS-CON C1 = 4700 pF R1 = 1.8 k R2 = 5.6 +66 0 Phase (deg) Gain AV (dB) 40 -90 1k Frequency f (Hz) 10k 100k -180 DS04-27204-6E MB3775 (2) As shown in Figure 37, a resistor (RP) is connected between the FB pins (pins 5 and 12) and CP of the error amplifier to advance the phase. The more RP is increased, the more the phase is advanced. However, the gain in the high-frequency range is also increased, which causes instability. Therefore, select the optimum resistance (see Fig. 38). Fig. 37 - External circuit example 2 to advance the phase V0+ R2 + IN + - IN R1 - FB RP CP VREF Fig. 38 - DC/DC Converter +5 V Gain/Phase vs. Frequency 60 40 180 20 0 -20 -40 10 DS04-27204-6E VCC = 10 V RL = 25 CP = 0.1 F Smoothing Capacitor 22 F OS-CON RP = 470 R1 = 1.8 k R2 = 5.6 100 +45 90 0 Phase (deg) Gain A V (dB) AV -90 1k Frequency f (Hz) 10k -180 100k 27 MB3775 (3) As shown in Fig. 39, the phase is advanced by using both example 1 and 2 (Fig. 35 and 37). Fig. 39 - External circuit example 3 to advance the phase C1 V0+ R2 + IN + - IN R1 FB - RP CP VREF ERROR AMPLIFIER INPUT RIPPLE VOLTAGE The boost circuit for charging the phase compensating capacitor CP is connected to the error amplifier as shown in Figure 40 to protect against output voltage overload at power-on. A =15 : mV offset voltage is provided for the negative input side so that the boost circuit only operates at poweron. When a capacitor is connected in parallel with the output feedback resistor, because the output ripple is too large or for advanced phase compensation, the boost circuit starts operating, which may degrade regulation if the differential input voltage of the error amplifier exceeds =15 mV. Be careful with the differential input voltage of the error amplifier. Fig. 40 - Error Amp /Boost Equivalent circuit VCC V0 + + Advanced phase compensation capacitor Boost circuit - R4 15 mV [+ IN] + [- IN] R1 38 k x 120 - Error Amp R2 470 R3 [FB] CP VREF 28 DS04-27204-6E MB3775 NOTES ON USE * Take account of common impedance when designing the earth line on a printed wiring board. * Take measures against static electricity. - For semiconductors, use antistatic or conductive containers. - When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container. - The work table, tools and measuring instruments must be grounded. - The worker must put on a grounding device containing 250 k to 1 M resistors in series. * Do not apply a negative voltage - Applying a negative voltage of -0.3 V or less to an LSI may generate a parasitic transistor, resulting in malfunction. DS04-27204-6E 29 MB3775 ORDERING INFORMATION Part number MB3775PF MB3775PFV 30 Package Remarks 16-pin plastic SOP (FPT-16P-M06) 16-pin plastic SSOP (FPT-16P-M05) DS04-27204-6E MB3775 RoHS COMPLIANCE INFORMATION OF LEAD (PB) FREE VERSION The LSI products of FUJITSU SEMICONDUCTOR with "E1" are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE) . The product that conforms to this standard is added "E1" at the end of the part number. MARKING FORMAT (LEAD FREE VERSION) MB3775 XXXX XXX E1 SOP-16 INDEX Lead Free version 3775 Lead Free version E1XXXX XXX SSOP-16 INDEX DS04-27204-6E 31 MB3775 LABELING SAMPLE (LEAD FREE VERSION) Lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 The part number of a lead-free product has the trailing characters "E1". 32 "ASSEMBLED IN CHINA" is printed on the label of a product assembled in China. DS04-27204-6E MB3775 MB3775PF, MB3775PFV RECOMMENDED CONDITIONS of MOISTURE SENSITIVITY LEVEL [FUJITSU SEMICONDUCTOR Recommended Mounting Conditions] Item Condition Mounting Method IR (infrared reflow), warm air reflow Mounting times 2 times Please use it within two years after Before opening manufacture. From opening to the 2nd reflow Less than 8 days Storage period Please process within 8 days after baking When the storage period after opening was (125 C 3 C, 24hrs + 2H/-0H) exceeded Baking can be performed up to two times. Storage conditions 5 C to 30 C, 70%RH or less (the lowest possible humidity) [Parameters for Each Mounting Method] IR (infrared reflow) 260C 255C 170C ~ 190C (b) RT H rank : 260 C Max (a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d') (e) Cooling (a) (c) (d) (e) (d') : Average 1 C/s to 4 C/s : Temperature 170 C to 190 C, 60s to 180s : Average 1 C/s to 4 C/s : Temperature 260 C Max; 255 C or more, 10s or less : Temperature 230 C or more, 40s or less or Temperature 225 C or more, 60s or less or Temperature 220 C or more, 80s or less : Natural cooling or forced cooling Note : Temperature : the top of the package body DS04-27204-6E 33 MB3775 Manual soldering (partial heating method) Item Before opening Condition Within two years after manufacture. Within two years after manufacture. Storage period Between opening and mounting (No need to control moisture during the storage period because of the partial heating method. ) Storage conditions 5 C to 30 C, 70%RH or less (the lowest possible humidity) Mounting Temperature at the tip of a soldering iron: 400 C max conditions Time: Five seconds or below per pin* * : Make sure that the tip of a soldering iron does not come in contact with the package body. 34 DS04-27204-6E MB3775 PACKAGE DIMENSION 16-pin plastic SOP Lead pitch 1.27 mm Package width x package length 5.3 x 10.15 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 2.25 mm MAX Weight 0.20 g Code (Reference) P-SOP16-5.3x10.15-1.27 (FPT-16P-M06) 16-pin plastic SOP (FPT-16P-M06) Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +0.25 +.010 +0.03 *110.15 -0.20 .400 -.008 0.17 -0.04 +.001 16 .007 -.002 9 *2 5.300.30 7.800.40 (.209.012) (.307.016) INDEX Details of "A" part +0.25 2.00 -0.15 +.010 .079 -.006 1 "A" 8 1.27(.050) 0.470.08 (.019.003) 0.13(.005) (Mounting height) 0.25(.010) 0~8 M 0.500.20 (.020.008) 0.600.15 (.024.006) +0.10 0.10 -0.05 +.004 .004 -.002 (Stand off) 0.10(.004) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F16015S-c-4-9 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS04-27204-6E 35 MB3775 (Continued) 16-pin plastic SSOP (FPT-16P-M05) 16-pin plastic SSOP (FPT-16P-M05) Lead pitch 0.65 mm Package width x package length 4.40 x 5.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.45mm MAX Weight 0.07g Code (Reference) P-SSOP16-4.4x5.0-0.65 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 5.000.10(.197.004) 16 0.170.03 (.007.001) 9 *2 4.400.10 6.400.20 (.173.004) (.252.008) INDEX Details of "A" part +0.20 1.25 -0.10 +.008 .049 -.004 LEAD No. 1 8 0.65(.026) "A" 0.240.08 (.009.003) 0.10(.004) C 36 (Mounting height) 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8 0.13(.005) M 0~8 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.10 (Stand off) (.004.004) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. DS04-27204-6E MB3775 MEMO DS04-27204-6E 37 MB3775 MEMO 38 DS04-27204-6E MB3775 MEMO DS04-27204-6E 39 MB3775 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department