FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©1994-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
ASSP
BIPOLAR
SWITCHING REGULATOR
CONTROLLER
MB3775
■LOW VOLTAGE DUAL PWM SWITCHING REGULATOR CONTROLLER
The MB3775 is a dual pulse-width-modulation control circuit. It contains the basic circuits required for two PWM
control circuits. Complete synchronization is obtained by using the same oscillator output waveform.
This IC can provide following types of output voltage: step down, step up, and inverter. Power consumption is low,
thus the MB3775 is ideal for use in high-efficiency portable equipment.
■FEATURES
• Wide supply voltage range: 3.6 V to 18 V
• Low current consumption: 1.3 mA typical
• Wide oscillation frequency range: 1 kHz to 500 kHz
• On-chip timer latch short protection circuit
• On-chip under voltage lockout protection
• On-chip reference voltage: 1.28 V
• Variable dead time provides control over total operating range.
• Two types of packages (SOP-16pin : 1 type, SSOP-16pin : 1 type)
■APPLICATIONS
• LCD monitor/panel
• Surveillance camera etc.
DS04-27204-6E
MB3775
2DS04-27204-6E
■PIN ASSIGNMENT
(TOP VIEW)
E/GND VCC
OUT2
VREF
D.T.C.2
FB2
-IN2
+IN2
SCP
1
9
+IN1
CT
RT
-IN1
FB1
OUT1
D.T.C.1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
(FPT-16P-M06)
(FPT-16P-M05)
MB3775
DS04-27204-6E 3
■PIN DESCRIPTION
No. Pin Function
1CTOscillator timing capacitor pin (150 pF to 15,000 pF) .
2R
TOscillator timing resistor pin (5.1 kΩ to 100 kΩ) .
3+IN1 Error amplifier 1 non-inverted input pin.
4−IN1 Error amplifier 1 inverted input pin.
5FB1
Error amplifier 1 output pin.
A resistor and a capacitor are connected between this pin and the −IN1 pin to adjust gain and
frequency.
6DTC1
OUT1 dead-time control pin.
Dead-time control is adjusted by an external resistive divider connected to the VREF pin.
A capacitor connected between this pin and GND enables soft-start operation.
7OUT1
Open collector output pin.
Output transistor has common ground independent of signal ground.
This output can source or sink up to 50 mA.
8 E/GND Ground pin.
9V
CC Power supply pin (3.6 V to 18 V)
10 OUT2
Open collector output pin.
Output transistor has common ground independent of signal ground.
This output can source or sink up to 50 mA.
11 DTC2 Sets the dead-time of OUT2.
The use of this pin is the same as that of DTC1.
12 FB2
Error amplifier 2 output pin.
A resistor and a capacitor are connected between this pin and the -IN2 pin to adjust gain and
frequency.
13 −IN2 Error amplifier 2 inverted input pin.
14 + IN2 Error amplifier 2 non-inverted input pin.
15 SCP
The time constant setting capacitor connection pin of the timer latch short-circuit
protection circuit.
Connects a capacitor between this pin and GND.
For details, see “■ HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT-CIRCUIT
PROTECTION CIRCUIT”.
16 VREF 1.28 V reference voltage output pin which can be obtained up to 1 mA.
This pin is used to set the reference input and idle period of the error amplifiers.
MB3775
4DS04-27204-6E
■BLOCK DIAGRAM
−
+
−
++
−
+
+
−
+
1.8 V
1.1 V
2.5 V
1.9 V
1.3 V
2.5 V
1 μA
OUT 1
OUT 2
PWM Comp.1
PWM Comp.2
U.V.L.O.
Latch
D.T.C.Comp.
Error Amp 2
Error Amp 1
S.C.P.Comp.
RSR
1.28 V
0.9 V 0.9 V
GND
V REF = 1.28 V
V CC
+
−
−
+
−
−
14
9
16
3
4
5
12
13
15
611
10
7
2
1
8
Reference
Voltage
Triangular
Waveform
MB3775
DS04-27204-6E 5
■OPERATION DESCRIPTION
1. Reference voltage
The reference voltage circuit generates a stable, temperature-compensated 2.5 V reference from Vcc pin (pin
9) for use by internal circuits.
A reference voltage of temperature compensated 1/2 VREF can be obtained to external circuit by VREF pin (pin 16).
2. Oscillator
A triangular waveform of any frequency is obtained by connecting an external capacitor and resistor to the CT
pin (pin 1) and RT pin (pin 2).
The amplitude of this waveform is from 1.3 V to 1.9 V. The oscillator is internally connected to the non-inverting
inputs of the PWM comparators. The oscillator waveform is available at the CT pin (pin 1).
3. Error amplifiers
The error amplifier detects the output voltage of the switching regulator.
The common-mode input voltage range is −0.2 V to 1.45 V, so the input reference voltage can be set the VREF
pin (pin 16) and GND pin levels. Error amplifiers can be used as either inverting and non-inverting amplifiers.
The voltage gain is fixed. Phase compensation is possible by connecting a capacitor to the FB pins (pins 5 and
12) of the error amplifiers.
The error amplifier output are internally connected to the inverting inputs of the PWM comparators and also to
the short protection circuit.
4. Timer latch short protection circuit
The timer latch short protection circuit detects the output levels of the error amplifiers. If one or both error amplifier
outputs are 1.1 V or lower, the timer circuit begins charging the externally connected protection enable capacitor.
If the output level of the error amplifier does not drop below the normal voltage range before the capacitor voltage
reaches the transistor base-emitter voltage VBE ( := 0.65 V), the latch circuit turns the output drive transistor off
and sets the dead time to 100 %.
5. Under voltage lockout protection circuit
An ambiguous transition state at power-on or a momentary fluctuation in the supply line may result in loss of
control and may adversely affect or even destroy the system. The under voltage lockout protection circuit com-
pares the internal reference voltage level with the supply voltage level. If the supply voltage level falls below the
reference level the latch circuit is reset the output drive transistor is turned off and the dead time is set to 100%.
The protection enable pin (pin 15) is pulled “Low”.
6. PWM comparator
Each PWM comparator has two inverting inputs and one non-inverting input. This voltage-to-pulse-width con-
verter controls the output pulse width according to the input voltage.
The PWM comparator turns the output drive transistor on when the oscillator triangular waveform is higher than
the error amplifier output and the dead time control pin voltage.
7. Output drive transistor
The open-collector output-drive transistors provide common-emitter output of 18 V dielectric capability. The
output drive transistors can source up to 50 mA of drive current to the switching power transistor.
MB3775
6DS04-27204-6E
■ABSOLUTE MAXIMUM RATING
*: The packages are mounted on the epoxy board (4 cm x 4 cm x 1.5 mm).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Parameter Symbol Condition Rating Unit
Min Max
Power Supply Voltage VCC ⎯⎯20 V
Error Amp Input Voltage VI⎯−0.3 +10 V
Collector Output Voltage VO⎯⎯20 V
Collector Output Current IO⎯⎯75 mA
Power Dissipation PD
Ta ≤ +25 °C(SOP) ⎯*620 mW
Ta ≤ +25 °C(SSOP) ⎯*430 mW
Operating Ambient Temperature Ta ⎯−30 +85 °C
Storage temperature Tstg ⎯−55 +125 °C
Parameter Symbol Value Unit
Min Typ Max
Power Supply Voltage VCC 3.6 6.0 18 V
Error Amp Input Voltage VI−0.2 ⎯ +1.45 V
Collector Output Voltage VO⎯⎯18 V
Collector Output Current IO0.3 ⎯50 mA
Phase Compensation Capacitor CP⎯0.1 ⎯μF
Timing Capacitor CT150 ⎯15000 pF
Timing Resistor RT5.1 ⎯100 kΩ
Oscillator Frequency fOSC 1⎯500 kHz
Reference Voltage Output Current IREF −3−1⎯mA
Operating Ambient Temperature Ta −30 +25 +85 °C
MB3775
DS04-27204-6E 7
■ELECTRICAL CHARACTERISTICS
(Ta = +25 °C, VCC = 6 V)
(Continued)
Parameter Condition Symbol Value Unit
Min Typ Max
Reference
Section
Output Voltage IOR = −1 mA VREF 1.26 1.28 1.30 V
Output Temp. Stability Ta = −30 °C to +85 °CVRTC −2±0.2+2 %
Input Stability VCC = 3.6 V to 18 V Line ⎯210mV
Load Stability IOR = −0.1 mA to −1 mA Load ⎯17.5mV
Short Circuit Output
Current VREF = 0 V IOS ⎯–30 –10 mA
Under
Voltage
Lockout
Protection
Section
Threshold Voltage IOR = −0.1 mA VtH ⎯2.72 ⎯V
IOR = −0.1 mA VtL ⎯2.60 ⎯V
Hysteresis Width IOR = −0.1 mA VHYS 80 120 ⎯mV
Reset Voltage (VCC)⎯VR1.5 1.9 ⎯V
Protection
Circuit
Section
Input Threshold Voltage ⎯VtPC 0.60 0.65 0.7 V
Input Stand by Voltage No pull up VSTB ⎯50 100 mV
Input Latch Voltage No pull up VI⎯50 100 mV
Input Source Current ⎯Ibpc −1.4 −1.0 −0.6 μA
Comparator Threshold
Voltage Pin 5, Pin 12 VtC ⎯1.1 ⎯V
Triangular
Waveform
Oscillator
Section
Oscillator Frequency CT = 330 pF, RT = 15 kΩfOSC ⎯200 ⎯kHz
Frequency Deviation CT = 330 pF, RT = 15 kΩfdev ⎯10 ⎯%
Frequency Stability (VCC)VCC = 3.6 V to 18 V fdV ⎯1⎯%
Frequency Stability (Ta)Ta = −30 °C to +85 °C fdT −4–+4%
Dead-Time
Control
Section
Input Threshold Voltage
(fOSC = 10 kHz)
Duty Cycle = 0 % Vt0 ⎯1.0 VREF
−0.15 V
Duty Cycle = 100 % Vt100 0.2 0.4 ⎯V
Input Bias Current ⎯Ibdt ⎯−0.2 –1 μA
Latch Mode Source
Current Vdt = 0.7 V Idt ⎯−150 −80 μA
Latch Input Voltage Idt = −40 μAVdt
VREF
−0.1 ⎯⎯ V
MB3775
8DS04-27204-6E
(Continued)
(Ta = +25 °C, VCC = 6 V)
Parameter Condition Symbol Value Unit
Min Typ Max
Error Amp
Section
Input Offset Voltage VO = 1.6 V VIO −10 ⎯+10 mV
Input Offset Current VO = 1.6 V IIO −100 ⎯+100 nA
Input Bias Current VO = 1.6 V IB−500 −100 ⎯nA
Common Mode Input
Voltage Range VCC = 3.6 V to 18 V VICR −0.2 ⎯+1.45 V
Voltage Gain AV84 120 ⎯V/V
Frequency Band Width AV = −3 dB BW ⎯3⎯MHz
Common Mode
Rejection Ratio CMRR 60 80 ⎯dB
Max Output Voltage
Width
VOM+ 2.2 2.4 ⎯V
VOM- –0.70.9V
Output Sink Current VO = 1.6 V IOM+ 24 50 ⎯μA
Output Source Current VO = 1.6 V IOM- ⎯−1.2 −0.7 mA
PWM Com-
parator
Section
Input Threshold Voltage
(fOSC=10 kHz)
Duty Cycle = 0 % Vt0 ⎯1.9 2.1 V
Duty Cycle = 100 % Vt100 1.05 1.3 ⎯V
Input Sink Current Pin 5, Pin 12 = 1.6 V IIN+ 24 50 ⎯μA
Input Source Current Pin 5, Pin 12 = 1.6 V IIN- ⎯−1.2 −0.7 mA
Output
Section
Output Leak Current VO = 18 V Leak ⎯⎯10 µA
Output Saturation
Voltage IO = 50 mA VSAT ⎯1.1 1.4 V
Stand by Current Output “OFF” ICCS ⎯1.3 1.8 mA
Average Supply Current RT = 15 kΩICCa ⎯1.7 2.4 mA
MB3775
DS04-27204-6E 9
■TEST CIRCUIT
■TIMING CHART (Internal Waveform)
SW
TEST
INPUT
OUTPUT 1
OUTPUT 2
TEST
INPUT
330 pF
0.1μF
123 456 78
16 15 14 13 12 11 10 9
MB3775
CPE
VCC=6 V
15 kΩ
4.7 kΩ
4.7 kΩ
1.9 V
1.5 V
1.3 V
1.1 V
“High”
“Low”
“High”
“Low”
0.6 V
0 V
“High”
“Low”
3.6 V
0 V
2.8 V (Typ Value)
tPE
DEAD TIME 100%
LOCK-OUT CANCEL
Protection Enable Time tPE := 0.6 x 106 x CPE (s)
LOCK-OUT
Error Amp output
Triangular waveform oscillator output
Dead Time PWM
input voltage
Short circuit protection
comparator Reference
PWM comparator
Output Transistor
collector waveform
SCP Pin
Short circuit protection
comparator output
Power supply voltage
(VCC : Min Value)
input
output
waveform
MB3775
10 DS04-27204-6E
■APPLICATION CIRCUIT
(Continued)
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 μF
33 kΩ
1 μF
33 kΩ
1 μF
330 Ω
9.1 kΩ
330 Ω
33 kΩ
120 μH
220 μF220 μF
470 Ω
120 μH
5.6 kΩ
1.9 kΩ
0.1 μF
0.1 μF
220 μF
56 μH
VIN (10 V)
V0- (−5 V) GND V0+ (+5 V)
+−
+−
−+
−+
−+
470 Ω
+−
+−
−+
−+
−+
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 μF
33 kΩ
1 μF
33 kΩ
1 μF
330 Ω
9.1 kΩ
330 Ω
33 kΩ
120 μH
220 μF220 μF
100 Ω
120 μH
16 kΩ
1.9 kΩ
0.1 μF
0.1 μF
220 μF
56 μH
VIN (5 V)
V0- (−5 V) GND V0+ (+12 V)
3.9 kΩ
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
Fig. 1 - Chopper Type Step Down/Inverting
Fig. 2 - Chopper Type Step Up/Inverting
MB3775
DS04-27204-6E 11
(Continued)
+−
+−
−+
−+
−+
−
+
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
820 pF
10 kΩ
2.3 kΩ
33 kΩ
0.1 μF
33 kΩ
1 μF
33 kΩ
1 μF
9.1 kΩ
33 kΩ
120 μH
220 μF220 μF
1.9 kΩ
0.1 μF
0.1 μF
220 μF
56 μH
VIN (5 V)
V0- (−5 V) GND V0+ (+12 V)
16 kΩ
150 Ω
120 μH
470 Ω
330 pF
33 kΩ
33 kΩ
220 Ω
470 Ω
470 Ω
470 Ω
1 μF
33 kΩ
1.9 kΩ
0.1 μF
0.1 μF
56 μH
VIN (10 V)
V02-
(−12 V)
−+
220 μF
V01-
(−5 V)
GND V02+
(+5 V)
V01+
(+12 V)
−+
220 μF
−+
220 μF
−+
220 μF
−+
220 μF
820 pF
10 kΩ
33 kΩ
220 Ω
1 nF
1.8 kΩ
0.1 μF
5.6 kΩ
MB3775
116
215
314
413
5
6
7
8
12
11
10
9
Fig. 3 - Chopper Type Step Up/Inverting (For High Speed)
Fig. 4 - Multi Output Type (Apply Transformer)
MB3775
12 DS04-27204-6E
■HOW TO SET OUTPUT VOLTAGE
The output voltage is set using the connection shown in Fig. 5 and 6.
The error amplifiers are supplied to the internal reference voltage circuit as are the other internal circuits. The
common-mode input voltage range is from −0.2 V to +1.45 V.
When the amplifiers are operated non-inverting, tie the inverting pin to VREF ( := 1.28 V). When the amplifiers are
operated inverting, tie the non-inverting pin to ground.
R2
R1
VREF
+
−
PIN 5 or PIN 12
V0+ [V0+ = VREF X (1 + R2/R1)]
Fig. 5 -Connection of Error Amp
Output Voltage V0 is plus
R2
R1
VREF
+
−
PIN 5 or PIN 12
V0- [V0- = −VREF X (R2/R1)]
Fig. 6 -Connection of Error Amp
Output Voltage V0 is minus
MB3775
DS04-27204-6E 13
■HOW TO SET TIME CONSTANT FOR TIMER LATCH SHORT PROTECTION CIRCUIT
TIMING CHART shows the configuration of the protection latch circuit.
Error amplifier outputs, are internally connected to the non-inverting inputs of the short-circuit protection com-
parator and are compared with the reference voltage (1.1 V) connected to the inverting input.
When the load condition of the switching regulator is stable, the error amplifier has no output fluctuation. Thus,
short-circuit protection control is also kept in balance, and the protection enable pin (pin 15) voltage is kept at
about 50 mV.
If the load condition drastically changes due to a load short-circuit and if low-level signals (1.1 V or lower) are
input to the non-inverting inputs of the short-circuit protection comparator from the error amplifiers, the short-
circuit protection comparator outputs a “Low” level to turn transistor Q1 off. The protection enable pin voltage is
discharged, and then the short-circuit protection comparator charges the externally connected protection enable
capacitor CPE according to the following formula:
VPE = 50 mV + tPE x 10-6/CPE
0.65 = 50 mV + tPE x 10-6/CPE
CPE = tPE/0.6 (μF)
When the protection enable capacitor charges to about 0.65 V, the protection latch is set to enable the under
voltage lockout protection circuit and to turn the output drive transistor off. The dead time is set to 100 %.
Once the under voltage lockout protection circuit is enabled, the protection enable is released; however, the
protection latch is not reset if the power is not turned off.
The non-inverting inputs of the D.T.C. comparator are connected to the D.T.C. pins (pins 6 and 11) through the
power supply (about 0.9 V) and are compared with a reference voltage (about 1.8 V) connected to the inverting
input.
To prevent malfunction of the short protection circuit in soft-start mode (using D.T.C. pins), the D.T.C. comparator
outputs a “High” level to turn Q2 on until the D.T.C. pins (pins 6 and 11) voltage drops to about 0.9 V.
Error Amp1
Error Amp2
1.1 V
S.C.P.Comp.
R1
Q1Q2Q3
CPE
15
11
6
SR
Latch U.V.L.O.
1 μA
2.5 V
D.T.C.1
D.T.C.2
D.T.C.Comp.
+
+
−
1.8 V
0.9 V
0.9 V
+
+
−
Fig. 7 - Protection Latch Circuit
SCP
MB3775
14 DS04-27204-6E
■SETTING THE IDLE PERIOD
When voltage step-up, fly-back step-up or inverted output are set, the voltage at the FB pin may go lower than
the triangular wave voltage due to load fluctuation, etc. In this case the output transistor will be in full-on state
(ON duty 100%). This can be prevented by setting the maximum duty for the output transistor. This is done by
setting the DTC1 pin (pin 6) voltage using resistance division of the VREF voltage as illustrated below.
When the DTC1 pin voltage is lower than the triangular waveform voltage, the output transistor is turned on. If
the triangular waveform amplitude := 0.6 V, the lower limit voltage of the triangular waveform := 1.3 V and the
offset voltage is 0.9 V, the formula for the maximum duty would be as follows (Other channels are this conditions) :
Also, if no output duty setting is required, the voltage should be set greater than the lower limit voltage of the
triangular waveform, which is 1.3 V (Vdt = 0.4 V).
• Setting the idle time at DTC1 (DTC2 is similar)
Duty (ON) Max (%) := 1.9 V − (Vdt + 0.9 V) × 100 := 1.0 V − Vdt × 100, Vdt (V) = Rb × VREF
0.6 V 0.6 V (Ra + Rb)
VREF
Ra
Rb Vdt
DTC1
16
6
MB3775
DS04-27204-6E 15
・VCC and VO
Set the DTC voltage using the following Duty Max vs. Vdt characteristics so that this duty is set to the maximum
duty or less.
Duty Max vs. Vdt characteristics (applies to Vdt 1 and Vdt 2)
• Step down DUTY[%] = VO × 100
Vcc
• Step up DUTY[%] = VO − Vcc × 100
VO
• Inverter DUTY[%] = VO × 100
VO − Vcc
100
80
60
40
20
0
0 0.2 0.4 0.6 0.81.0
Duty Max [%]
Vdt [V]
MB3775
16 DS04-27204-6E
■SETTING THE SOFT START TIME
When power is switched on, the current begins charging the capacitor (CDTC1) connected the DTC1 pin (pin 6).
The soft start process operates by comparing the soft start setting voltage, which is proportional to the DTC1
pin voltage, with the triangular waveform, and varying the ON-duty of the OUT pin (pin 7).
The soft start time until the ON duty reaches 50% is determined by the following equation:
Soft start time (time until output ON duty = 50%) .
ts (s) := − CDTC1 × Ra × Rb / (Ra + Rb) × ln (1 − 0.7 (Ra + Rb) / (1.28 Ra) )
For example, if Ra = 10 kΩ and Rb = 4.7 kΩ, the result is:
ts (s) := 0.005 × CDTC1 (μF)
• Soft Start on DCT1 pin (DTC2 is similar)
VREF
Ra
Rb
CDTC1
DTC1 6
16
MB3775
DS04-27204-6E 17
■SYNCHRONIZATION OF ICs
To synchronize MB3775 ICs, first, the specified capacitor and resistor are connected to the CT and RT pins (pins
1 and 2) of the master IC to start self oscillation. Next, 2 V is applied to the RT pin (pin 2) of the slave ICs to
disable the charge/discharge circuit for triangular wave oscillation. Finally, the CT pin (pin 1) of the master and
slave ICs are connected.
Instead of applying VRT to the RT pin (pin 2), these pins can be pulled up by a resistor (see resistance indicated
by the dashed line in Fig. 8). Select the pull-up resistance Rpull from the formula given below.
VCC
0.5 x N ≥ Rpull
Rpull: Pull up Resistor (kΩ)
VCC: Power Supply Voltage (V)
N: Number of Slave ICs
MB3775
MB3775
MB3775
2 V
VRT
Rpull CTRT
VCC
Fig. 8 - Connection of Master, Slave
(MASTER)
(SLAVE)
(SLAVE)
MB3775
18 DS04-27204-6E
■TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
2.0
1.5
1.0
0.5
05101520 05101520
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
05101520
1.29
1.28
1.26
−30 +0 +30 +60 +90
1.25
3.0
2.0
1.0
0
100 1k 10k 100k 1M
3.5
3.0
2.5
2.0
1.5
1.0
0.5
050 100 150 350200 250 300
Fig. 9 - Reference voltage vs. Power supply voltage Fig. 10 - Average supply current vs. Power supply voltage
Fig. 12 - Reference voltage vs. Operating ambient temperature
Fig. 13 - Collector saturation voltage vs. Sink current Fig. 14 - Error Amp Max output voltage vs. Frequency
Power supply voltage VCC (V) Power supply voltage VCC (V)
Power supply voltage VCC (V) Operating ambient temperature Ta ( °C)
Sink current lO (mA) Frequency f (Hz)
1.27
Fig. 11 - Stand by current vs. Power supply voltage
Reference voltage V REF(V)
Average supply current I (mA)
Stand by current ICCS (mA)
(V)
Error Amp Max output voltage VOM (V) Reference voltage VREF (V) CCa
Collector saturation voltage VSAT
MB3775
DS04-27204-6E 19
(Continued)
1M
100k
10k
1k
1001k 10k 100k 1M 10M 101102103104105
103
102
101
100
10-1
1011021031041051k 10k 100k 1M 10M
2.2
2.0
1.8
1.4
1.0
1.6
1.2
60
40
20
−20
−60
0
−40
180
90
−90
0
−180
90
60
40
20
−20
−60
0
−40
60
40
20
−20
−60
0
−40
100102103107
105
101104106
100102103107
105
101104106
180
90
−90
0
−180
180
90
−90
0
−180
CFB = 1 μF CFB = 0.1 μF
Fig. 15 - Oscillation Frequency vs. Timing resistor Fig. 16 - Triangular waveform cycle vs. Timing capacitor
Fig. 17 - Triangular waveform Max Amplitude voltage vs. Timing capacitor Fig. 18 - Gain/Phase vs. Frequency
Fig. 19 - Gain/Phase vs. Frequency (Actual Data) Fig. 20 - Gain/Phase vs. Frequency (Actual Data)
CT = 150 pF
CT = 1500 pF
CT = 15000 pF
Timing resistance=15 kΩ
VCC = 6 V
Timing resistance = 15 kΩ
VCC = 6 V
Gain AV
Timing resistor RT (Ω)Timing capacitor CT (pF)
Timing capacitor CT (pF) Frequency f (Hz)
Frequency f (Hz) Frequency f (Hz)
Phase φ
Gain AV
Phase φ
Gain AV
Phase φ
Triangular waveform Max Amplitude voltage (V)
Gain AV(dB)
Triangular waveform cycle ( μs)
Phase φ (deg)
Phase φ (deg)
Gain AV(dB)
Phase φ (deg)
Gain AV(dB)
Oscillation Frequency fOSC (Hz)
MB3775
20 DS04-27204-6E
(Continued)
V
60
40
20
−20
−60
0
−40
100102103107
105
101104106
180
90
−90
0
−180
Fig. 21 - Gain/Phase vs. Frequency (Actual Data)
Frequency f (Hz)
Gain AV
Phase φ
Gain A (dB)
Phase φ (deg)
CFB=0.01 μF
MB3775
DS04-27204-6E 21
■HOW TO SET THE ERROR AMPLIFIER FREQUENCY CHARACTERISTIC
Figure 22 shows the equivalent circuit of the error amplifier.
The frequency characteristic of the error amplifier is set by R1, R2, and CP. The high-frequency gain is set by the
ratio of resistors R1 and R2 in the IC (set value 0 dB).
When CP = 0.1 μF, the gain at 20 kHz ≤ f ≤ 5 MHz is about 0 dB. The roll-off frequency is adjusted by changing
external phase compensating capacitor CP (see Fig. 24).
When high frequency gain is needed or the phase must be advanced at a low frequency, connect a resistor RP
between the FB pins (pins 5 and 12) and CP as shown in Figure 23 (see Fig. 25).
Note: As shown above, the frequency characteristic of the error amplifier is set by the external phase compensating
capacitor CP.
When a ceramic chip capacitor must be used to meet the requirements of a small system, be careful of its
temperature characteristic. (−30 °C 1/5 and +80 °C 1/3 for the frequency characteristic, so a sufficient
phase margin must be allowed for at room temperature.) Ceramic chip capacitors with a low temperature
characteristic (B characteristic) or film capacitors are recommended (see Fig. 26 to 28).
R1 38 kΩ
PWM COMP
[− IN]
[+ IN]
[FB]
CP
R2 470 Ω
−
+
x 120
Error Amp
Fig. 22 - Error Amp Equivalent Circuit
PWM COMP
[− IN]
[+ IN]
[FB]
CP
−
+
x 120
RP
Error Amp
Fig. 23 - Error Amp Equivalent Circuit (Insert RP)
R1 38 kΩ
R2 470 Ω
=
..
=
..
MB3775
22 DS04-27204-6E
Gain AV(dB) Gain AV(dB)
60
20
−20
−40
−60
60
40
20
0
−20
−40
−60
10 100 1k 10k 100k 1M 10M 100M
100 1k 10k 100k 1M 10M 100M10
180
90
0
−90
−180
180
90
0
−90
−180
RP=0 Ω
RP=0 Ω
CP = 0.1 μF
CP = 0.1 μF
AV
AV
CP = 0.1 μF
(Large)
(Large)
(Large)
(Large)
(Small)
(Small)
ϕ
ϕ
Frequency f (Hz)
0
40
Fig. 24 - Error Amp Frequency characteristics
Frequency f (Hz)
Fig. 25 - Error Amp Frequency characteristics
Phase φ (deg)
Phase φ (deg)
MB3775
DS04-27204-6E 23
Gain AV(dB) Gain AV(dB) Gain AV(dB)
20
10
0
−10
−20
20
10
0
−10
−20
20
10
0
−10
−20
1k 10k 100k 1M
1k 10k 100k
1k 10k 100k 1M
90
0
90
−90
90
0
−90
φ
φ
AV
AV
AV
−30°C
+80°C
+25°C
+80°C
+25°C
−30°C, +25°C, +80°C
−30°C,
+25°C
+80°C
1M
Frequency f (Hz)
Frequency f (Hz)
Frequency f (Hz)
−90
−30°C
+25°C
+80°C
0
−30°C
+25°C
Fig. 26 - Ceramic Chip Capacitor (0.1 μF)
Fig. 27 - Tantal Capacitor (0.33 μF)
Fig. 28 - Film Capacitor (0.1 μF)
−30°C : 0.19
+25°C:1.0
+80°C : 0.32
−30°C : 0.95 to 1.05
+25°C:1.0
+80°C : 0.95 to 1.05
−30°C : 0.9 to 1.1
+25°C:1.0
+80°C : 0.9 to 1.1
−30°C
Phase φ (deg)
Phase φ (deg)Phase φ (deg)
φ
+80°C
Temp. characteristic
Te m p. : R a t i o
Temp. characteristic
Temp. characteristic
Te m p. : R a t i o
MB3775
24 DS04-27204-6E
■EFFECT OF EQUIVALENT SERIES RESISTANCE OF SMOOTHING CAPACITOR
The equivalent series resistance (ESR) of the smoothing capacitor in the DC/DC converter greatly affects the
loop phase characteristic.
A smoothing capacitor with a low ESR reduces system stability by increasing the phase shift in the high-frequency
region (see Fig. 30). Therefore, a smoothing capacitor with a high ESR will improve system stability. Be careful
when using low ESR semiconductor electrolytic capacitors (OS-CONTM) and tantalum capacitors.
Note: OS-CON is the trademark of Sanyo Electric Co., Ltd.
Tr
VIN DRL
RC
C
L
Fig. 29 - Step Down DC/DC Converter Basic Circuit
20
0
−20
−40
−60
10 100 1k 10k 100k 10 100 1k 10k 100k
−90
0
−180
: RC = 0 Ω
: RC = 31 mΩ
Frequency f (Hz) Frequency f (Hz)
Fig. 30 - Gain vs. Frequency Fig. 31 - Phase vs. Frequency
(1)
(2)
(2)
(1)
(1)
(2)
: RC = 0 Ω
: RC = 31 mΩ
(1)
(2)
Gain A V (dB)
Phase φ (deg)
MB3775
DS04-27204-6E 25
Reference data
If an aluminum electrolytic smoothing capacitor (RC1.0 Ω) is replaced with a low ESR semiconductor electro-
lytic capacitor (OS-CONTM: RC 0.2 Ω), the phase shift is reduced by half (see Fig. 33 and 34).
R1
− IN
−
+
~
R2
+ IN
VOUT V0+
VREF
VIN
FB
0.1 μF
Error Amp
Fig. 32 - DC/DC Converter AV vs. φ characteristic Test Circuit
AV vs. φ characteristic
Between this point.
V
60
20
0
−20
−40
60
20
0
−20
−40
10 100 1k 10k 100k
10 100 1k 10k
+
−
+
−
OS-CONTM
22 μF(16V)
RC0.2 Ω : fosc=1 kHz
AI Capacitor
220 μF(16 V)
RC1.0 Ω : fosc=1 kHz
GND
GND
V0+
V0+
AV
AV
φ
φ
100k
180
90
0
−90
−180
180
90
0
−90
−180
40
Frequency f (Hz)
Frequency f (Hz)
40
Fig. 33 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Fig. 34 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain A (dB)
Phase φ (deg)
Gain AV
(dB)
Phase φ (deg)
VCC=10 V
RL=25 Ω
CP=0.1 μF
VCC=10 V
RL=25 Ω
CP=0.1 μF
+62°
+27°
MB3775
26 DS04-27204-6E
■MEASURES FOR ENSURING SYSTEM STABILITY WHEN A LOW ESR SMOOTHING CA-
PACITOR IS USED
When a low ESR smoothing capacitor is used in the DC/DC converter, only the L and C are apparent even in
the high-frequency region, and the phase is delayed by almost 180°. Consequently, the system phase margin
and stability are reduced. On the other hand, a low ESR capacitor is needed to reduce the amount of output
ripple. This is contrary to the system stability explained above.
To solve this problem, phase compensation can be used. This method increases the phase margin by advancing
the phase when the phase margin is reduced by a low ESR capacitor.
The three suggestions listed below are recommended for DC/DC converters using the MB3775.
(1) As shown in Fig. 35, a capacitor is connected in parallel with the output feedback resistor to advance the
phase. Use the formula below as a guideline for the capacitance.
C11
2πfR2
Unstable Frequency (See Fig. 32)
R1
CP
R2
+ IN
+
−
V0+
VREF
FB
− IN
C1
Fig. 35 - External circuit example1 to advance the phase
60
40
20
0
−20
−40
10 100 1k 10k 100k
180
90
0
−90
−180
+66°
φ
AV
VCC = 10 V
RL = 25 Ω
CP = 0.1 μF
Smoothing Capacitor
22 μF OS-CON
C1 = 4700 pF
R1 = 1.8 kΩ
R2 = 5.6 Ω
Frequency f (Hz)
Fig. 36 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain AV
(dB)
Phase φ (deg)
MB3775
DS04-27204-6E 27
(2) As shown in Figure 37, a resistor (RP) is connected between the FB pins (pins 5 and 12) and CP of the error
amplifier to advance the phase. The more RP is increased, the more the phase is advanced. However, the
gain in the high-frequency range is also increased, which causes instability. Therefore, select the optimum
resistance (see Fig. 38).
R1
CP
R2
+ IN
+
−
V0+
VREF
FB
− IN
RP
Fig. 37 - External circuit example 2 to advance the phase
VCC = 10 V
RL = 25 Ω
CP = 0.1 μF
Smoothing Capacitor
22 μF OS-CON
RP = 470 Ω
R1 = 1.8 kΩ
R2 = 5.6 Ω
φ
60
40
20
0
−20
−40
10 100 1k 10k 100k
180
90
0
−90
−180
AV
Frequency f (Hz)
Fig. 38 - DC/DC Converter +5 V Gain/Phase vs. Frequency
Gain A V (dB)
Phase φ (deg)
+45°
MB3775
28 DS04-27204-6E
(3) As shown in Fig. 39, the phase is advanced by using both example 1 and 2 (Fig. 35 and 37).
■ERROR AMPLIFIER INPUT RIPPLE VOLTAGE
The boost circuit for charging the phase compensating capacitor CP is connected to the error amplifier as shown
in Figure 40 to protect against output voltage overload at power-on.
A :=15 mV offset voltage is provided for the negative input side so that the boost circuit only operates at power-
on. When a capacitor is connected in parallel with the output feedback resistor, because the output ripple is too
large or for advanced phase compensation, the boost circuit starts operating, which may degrade regulation if
the differential input voltage of the error amplifier exceeds =15 mV. Be careful with the differential input voltage
of the error amplifier.
R1
R2
+ IN
+
−
V0+
VREF
FB
− IN
C1
CP
RP
Fig. 39 - External circuit example 3 to advance the phase
R3
[+ IN]
+
−
VREF
[FB]
[− IN]
CP
+
−
× 120
15 mV
R4
VCC
V0 +
Fig. 40 - Error Amp /Boost Equivalent circuit
Advanced phase
compensation
capacitor
Boost circuit
Error Amp
R1 38 kΩ
R2 470 Ω
MB3775
DS04-27204-6E 29
■NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
MB3775
30 DS04-27204-6E
■ORDERING INFORMATION
Part number Package Remarks
MB3775PF 16-pin plastic SOP
(FPT-16P-M06)
MB3775PFV 16-pin plastic SSOP
(FPT-16P-M05)
MB3775
DS04-27204-6E 31
■RoHS COMPLIANCE INFORMATION OF LEAD (PB) FREE VERSION
The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has ob-
served the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB), and
polybrominated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
■MARKING FORMAT (LEAD FREE VERSION)
INDEX
MB3775
XXXX XXX
E1
INDEX
3775
E1XXXX
XXX
Lead Free version
Lead Free version
SOP-16
SSOP-16
MB3775
32 DS04-27204-6E
■LABELING SAMPLE (LEAD FREE VERSION)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead-free mark
JEITA logo JEDEC logo
The part number of a lead-free product has
the trailing characters “E1”.
“ASSEMBLED IN CHINA” is printed on the label
of a product assembled in China.
MB3775
DS04-27204-6E 33
■MB3775PF, MB3775PFV RECOMMENDED CONDITIONS of MOISTURE SENSITIVITY
LEVEL
[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]
[Parameters for Each Mounting Method]
IR (infrared reflow)
Item Condition
Mounting Method IR (infrared reflow), warm air reflow
Mounting times 2 times
Storage period
Before opening Please use it within two years after
manufacture.
From opening to the 2nd reflow Less than 8 days
When the storage period after opening was
exceeded
Please process within 8 days after baking
(125 °C ± 3 °C, 24hrs + 2H/-0H)
Baking can be performed up to two times.
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260°C
(e)
(d')
(d)
255°C
170°C
190°C
RT (b)
(a)
(c)
~
Note : Temperature : the top of the package body
(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10s or less
(d’) : Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB3775
34 DS04-27204-6E
Manual soldering (partial heating method)
* : Make sure that the tip of a soldering iron does not come in contact with the package body.
Item Condition
Storage period
Before opening Within two years after manufacture.
Between opening and mounting
Within two years after manufacture.
(No need to control moisture during the storage
period because of the partial heating method. )
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
Mounting
conditions
Temperature at the tip of a soldering iron: 400 °C max
Time: Five seconds or below per pin*
MB3775
DS04-27204-6E 35
■PACKAGE DIMENSION
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
16-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.3 × 10.15 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.25 mm MAX
Weight 0.20 g
Code
(Reference) P-SOP16-5.3×10.15-1.27
16-pin plastic SOP
(FPT-16P-M06)
(FPT-16P-M06)
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F16015S-c-4-9
0.13(.005)
M
Details of "A" part
7.80±0.405.30±0.30
(.209±.012) (.307±.016)
–.008
+.010
–0.20
+0.25
10.15
INDEX
1.27(.050)
0.10(.004)
18
916
0.47±0.08
(.019±.003)
–0.04
+0.03
0.17
.007 +.001
–.002
"A" 0.25(.010)
(Stand off)
0~8°
(Mounting height)
2.00 +0.25
–0.15
.079 +.010
–.006
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10 +0.10
–0.05
–.002
+.004
.004
.400
*
1
*
2
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3775
36 DS04-27204-6E
(Continued)
16-pin plastic SSOP Lead pitch 0.65 mm
Package width
×
package length
4.40 × 5.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.45mm MAX
Weight 0.07g
Code
(Reference) P-SSOP16-4.4×5.0-0.65
16-pin plastic SSOP
(FPT-16P-M05)
(FPT-16P-M05)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8
5.00±0.10(.197±.004)
4.40±0.10 6.40±0.20
(.252±.008)(.173±.004)
.049
–.004
+.008
–0.10
+0.20
1.25 (Mounting height)
0.10(.004)
0.65(.026) 0.24±0.08
(.009±.003)
18
16 9
"A"
0.10±0.10 (Stand off)
0.17±0.03
(.007±.001)
M
0.13(.005)
(.004±.004)
Details of "A" part
0~8°
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
0.25(.010)
LEAD No.
INDEX
*1
*2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3775
DS04-27204-6E 37
MEMO
MB3775
38 DS04-27204-6E
MEMO
MB3775
DS04-27204-6E 39
MEMO
MB3775
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
