Am29PDL128G80PEIN - Advanced Micro Devices

ADVANCE INFORMATION

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 25685 Rev: BAmendment/0

Issue Date: April 26, 2002

Refer to AMD

’

sWebs

te (www.amd.com) for the latest

nformat

on.

Am29PDL128G

128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous

Operation Flash Memory with VersatileIOTM C ontro l

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■128Mbit Page Mode device

— Wor d (1 6- bit) or dou ble wor d ( 32-bit) m ode s el ect able vi a

WORD# input

— Page size of 8 words/4 double words: Fast page read access

from random locations within the page

■Single power supply operation

— Full V oltag e r ange: 2. 7 to 3.6 vo l t r ea d, er ase, and prog r am

operations for battery-powered applications

■Simult aneous Read/W rite Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Zero latency switching from write to read operations

■FlexBank Arch it ectu r e

— 4 separat e ban k s, with u p t o t wo sim ultaneous oper ations

per device

— Organized as two 16 Mbit banks (Bank 1 & 4) and two 48

Mbit banks (Bank 2 & 3)

■VersatileI/OTM (VIO) Control

— Output voltage generated and input voltages tolerated on the

devic e is deter mined by th e voltage on the V IO pin

■SecSi (Secure d Silicon) Sector reg ion

— 128 words (64 double words) accessible through a

command se qu ence

■Both top and bottom boot blocks in one device

■Manufact ured on 0.17 µm process technology

■20-year da ta retention at 125°C

■Minimum 1 million write cycle guarantee per sector

PERFORMANCE CHARACTERISTICS

■High Performanc e

—Pa ge acce ss t imes as fast as 25 n s

—Ra ndom acce ss t imes as fast as 70 n s

■Power consumption (typical values at 10 MHz)

—38 mA active read current

—17 mA program/erase current

—1.5 µA typical standby mode current

SOFT WARE FEATURES

■Software command-set compati b le with JEDEC 42.4

standard

—Backward compatible with Am29F and Am29LV families

■CFI (Common Flash Interface) complaint

—Provides device-specific information to the system, allowing

host software to easily reconfigure for different Flash devices

■Erase Suspend / Erase Resume

—Suspends an erase operation to allow read or program

operations in other sectors of same bank

■Unlock Bypass Program comm and

—Reduces overall programming time when issuing multiple

program command sequences

HARDWARE FEATURES

■Ready/Busy# pin (RY/BY#)

—Pro vide s a ha r dw a r e me t hod of de t ec t ing program or er as e

cycl e compl et io n

■Hardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

■WP# (Write Protect) input

—At VIL, protects the two top and two bottom sectors ,

regardless of sector protect/unprotect status

—At VIH, allows removal of sector protection

—An internal pull up to Vcc is provided

■Persist ent Sector Protect ion

—A command sector protec tion method to lock combinations

of indi vidual s ectors and s ecto r groups t o pr event pro gram or

erase operations within that sector

—Sector s can be lo cked a nd unlocked in- syst em at VCC level

■Password Sector Prote c t ion

—A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

pr event prog ram or erase ope rat ions withi n tha t sect or usin g

a user - d ef ined 64-b it pas sword

■ACC (Acceleration) input provides faster programming

times in a factory setti ng

■Package options

—80-ball Fortifie d BGA

2 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29 PD L12 8G is a 1 28 Mb it, 3 .0 v olt-onl y P age Mo de

and Simultaneous Read/Write Flash memory device orga-

nized as 8 Mw or ds or 4 M d ouble w ords (O ne wor d is equ al

to two by tes). The de vice is offered in an 80-b all Fortified

BGA package. The word-wide data (x16) appears on

DQ15-DQ0; the double wor d mode data (x32) appears on

DQ31-DQ0. This device can be programmed in-system or in

standard EPROM programmers. A 12.0 V VPP is not re -

quired for write or erase operations.

The device offers fast page access times of 25 and 30 ns,

with corresponding random access times of 70 and 80 ns,

respectively, allowing high speed microprocessors to oper-

ate w itho ut w ait s tate s. To el imi nate bu s co nten tion the d e-

vice has separ ate chip enable ( CE#), wr ite enab le (W E#)

and output enable (OE#) controls.

Simultaneous Read/Write Operation with

Zero Latency

The Sim ultan eou s Read /Writ e arc hitec ture pro vide s simul-

taneous operation by divid ing the mem ory space into 4

banks, which can be considered to be four separate memory

arrays as far as certain operations are concerned. The de-

vice can improve overall system perform ance by a llowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with 2 simultaneous operations operating at any

one time). This releases the system from waiting for the

comp le tion of a program or er ase operati on, greatl y improv-

ing system perfor mance.

The d evi ce ca n be o r ga nize d i n bo th t op and b ot tom s ect or

configurations (see Table 1).

Page Mode Features

The device is AC timing, input/output, and pac kage compat-

ible with 8 Mbit x16 page mode mask ROM. The page size

is 8 words or 4 doubl e words.

After initial page access is accomplished, the page mode op-

eration provides fast read ac cess speed of random locations

within that page.

Standard Flash Memory Feat ures

The device requires a single 3.0 v olt power supply (2.7 V

to 3.6 V) for bo th read and write fu nctio ns. Inte rnall y gener -

ated and regulated v oltages are prov ided for the progr am

and erase operations.

The device is entirely command set compatible with the

JEDEC 4 2.4 single-power-suppl y Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an in ternal state-machine that controls the erase and

progra mming circuitry. Write cycl es also internally latch ad-

dress es and data needed for the programming a nd erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

Device pro grammi ng occurs by e xecutin g the progr am com -

mand sequ ence. The Unlock Byp ass mode facilitates faster

programming times by requiring only two write cycles to pro-

gram data inst ead of fou r. Device e rasu re o ccu rs by exec u t-

ing the erase command seque nce.

The host s yste m can detect wh ether a prog ram or erase op-

eration is complete by reading the DQ7 (Data# Polling) an d

DQ6 (toggle) status bits. After a prog ram or erase cycle ha s

been comp leted, the de vice is ready to read array data or

accept another command.

The sector erase architecture allows memory sectors to be

erased and r eprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the fac tory.

Hard ware dat a protect ion measur es include a low VCC de-

tector that automatically inhibits write operations during

power transitions. The hardware secto r protection featu re

disables both program and erase operations in any combi-

nation of sectors of memory . This can be achieved in-system

or via progr amming equipment.

Th e Erase Suspen d/Eras e Res ume fe ature enables the

use r to put era se on hol d fo r any perio d of ti me to read d ata

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command se quence to enter and exit this region.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sl eep mode. T he sy stem ca n

also plac e the device into th e st andby m ode. Power con-

sumption is greatly reduc ed in both these modes.

AMD’s Flash technology combined years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

Table 1. Bank/Sector Sizes

Bank Number of

Sectors

Sector Size

(Word/Dbl.

Word) Bank Size

184/2

16 Mbit

31 32/16

2 96 32/16 48 Mbit

3 96 32/16 48 Mbit

484/2

16 Mbit

31 32/16

April 26,  2002 Am29PDL128G 3
ADVANCE INFORMATION 
TABLE OF CONTENTS
Table 1. Bank/Sector Sizes ...............................................................2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .  5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
Simultaneous Operat ion Block Diagra m . . .  . . . .  6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . .  7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .  9
Device Bus Operations . . . . . . . . . . . . . . . . . . . .  10
Table 1. Am29PDL128G Device Bus Operations  ...........................10
Word/Double Word Configuration...........................................  10
Requirements for Reading Array Data  ................................... 10
Random Read (Non-Page Read)  ........................................... 10
Page Mode Read .................................................................... 11
Table 2. Page Select, Double Word Mode ......................................11
Table 3. Page Select, Word Mode  ..................................................11
Simultaneous Operation  ......................................................... 11
Table 4. Bank Select .......................................................................11
Writing Commands/Command Sequences  ............................ 11
Accelerated Program Operation  ............................................. 12
Autoselect Functions  .............................................................. 12
Standby Mode ........................................................................  12
Automatic Sleep Mode  ........................................................... 12
RESET#: Hardware Reset Pin  ............................................... 12
Output Disable Mode .............................................................. 12
Table 5. Sector Address Table ........................................................13
Table 6.  SecSi Sector Addresses................................................20
Autoselect Mode.....................................................................  20
Table 7. Autoselect Codes (High Voltage Method)  ........................20
Table 8. Sector Block Addresses for Protection/Unprotection  ........21
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . .  23
Persistent Sector Protection  ................................................... 24
Persistent Protection Bit (PPB) ............................................... 24
Persistent Protection Bit Lock (PPB Lock)  ............................. 24
Dynamic Protection Bit (DPB)  ................................................ 24
Table 9. Sector Protection Schemes ...............................................25
Persistent Sector Protection Mode Locking Bit  ...................... 25
Password Protection Mode ..................................................... 25
Password and Password Mode Locking Bit  ........................... 25
64-bit Password ...................................................................... 26
Write Protect (WP#) ................................................................ 26
Persistent Protection Bit Lock ................................................. 26
High Voltage Sector Protection  .............................................. 26
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 27
Temporary Sector Unprotect  .................................................. 28
Figure 2. Temporary Sector Unprotect Operation........................... 28
SecSi™ (Secured Silicon) Sector 
Flash Memory Region ............................................................ 28
SecSi Sector Protection Bit  .................................................... 29
Utilizing Password and SecSi Sector Concurrently  ................ 29
Hardware Data Protection  ...................................................... 29
Low VCC Write Inhibit  ............................................................ 29
Write Pulse “Glitch” Protection  ............................................... 29
Logical Inhibit .......................................................................... 29
Power-Up Write Inhibit ............................................................ 29
Common Flash Memory Interface (CFI). . . . . . .  30
Table 10. CFI Query Identification String ............................  30
Table 11. System Interface String................................................... 31
Table 12. Device Geometry Definition.................................  32
Table 13. Primary Vendor-Specific Extended Query...........  33
Co m m a nd D e finitions. . . . . . . . . . . . . . .  . . . . . . . 34
Reading Array Data  ................................................................ 34
Reset Command ..................................................................... 34
Autoselect Command Sequence  ............................................ 34
Enter SecSi Sector/Exit SecSi Sector
Command Sequence .............................................................. 34
Double Word/Word Program Command Sequence ................35
Unlock Bypass Command Sequence  ..................................... 35
Figure 3. Program Operation .........................................................  36
Chip Erase Command Sequence  ........................................... 36
Sector Erase Command Sequence  ........................................ 36
Erase Suspend/Erase Resume Commands  ........................... 37
Figure 4. Erase Operation..............................................................  37
Password Program Command ................................................ 37
Password Verify Command  .................................................... 38
Password Protection Mode Locking Bit Program Command .. 38
Persistent Sector Protection Mode Locking Bit Program 
Command ............................................................................... 38
SecSi Sector Protection Bit Program Command  .................... 38
PPB Lock Bit Set Command ................................................... 38
DPB Write Command  ............................................................. 39
Password Unlock Command  .................................................. 39
PPB Program Command  ........................................................ 39
All PPB Erase Command ........................................................ 39
DPB Write Command  ............................................................. 39
PPB Lock Bit Set Command ................................................... 40
PPB Lock Bit Status Command  .............................................. 40
Sector Protection Status Command  ....................................... 40
Command Definitions Tables..................................................  41
Table 14. Memory Array Command Definitions (x32 Mode)  .......... 41
Table 15. Sector Protection Command Definitions (x32 Mode) ..... 42
Table 16. Memory Array Command Definitions (x16 Mode)  .......... 43
Table 17. Sector Protection Command Definitions (x16 Mode) ..... 44
Wr ite O pe r a t i on S ta t u s. . . . . . . . . . . . . . . . . . . . . 4 5
DQ7: Data# Polling ................................................................. 45
Figure 5. Data# Polling Algorithm ..................................................  45
RY/BY#: Ready/Busy#............................................................  46
DQ6: Toggle Bit I  .................................................................... 46
Figure 6. Toggle Bit Algorithm........................................................  46
DQ2: Toggle Bit II  ................................................................... 47
Reading Toggle Bits DQ6/DQ2 ............................................... 47
DQ5: Exceeded Timing Limits  ................................................ 47
DQ3: Sector Erase Timer  ....................................................... 47
Table 18. Write Operation Status ................................................... 48
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 49
Figure 7. Maximum Negative Overshoot Waveform ......................  49
Figure 8. Maximum Positive Overshoot Waveform........................  49
DC Cha ra c teristics . . . . . . . . . . . . . . . . . . . . . . . . 50
Test  C onditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9.  Test Setup......................................................................  51
Figure 10. Input Waveforms and Measurement Levels .................  51
AC Cha ra c teristics . . . . . . . . . . . . . . . . . . . . . . . . 52
Read-Only Operations  ........................................................... 52

4 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Figure 11. Read Operation Timings................................................ 52
Figure 12. Page Read Operation Timings....................................... 53
Hardware Reset (RESET#)  .................................................... 54
Figure 13. Reset Timings................................................................ 54
Word/Double Word Configuration (WORD#) .......................... 55
Figure 14. WORD# Timings for Read Operations........................... 55
Figure 15. WORD# Timings for Write Operations........................... 55
Erase and Program Operations .............................................. 56
Figure 16. Program Operation Timings........................................... 57
Figure 17. Accelerated Program Timing Diagram........................... 57
Figure 18. Chip/Sector Erase Operation Timings ........................... 58
Figure 19. Back-to-back Read/Write Cycle Timings ....................... 59
Figure 20. Data# Polling Timings (During Embedded Algorithms).. 59
Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 60
Figure 22. DQ2 vs. DQ6.................................................................. 60
Temporary Sector Unprotect  .................................................. 61
Figure 23. Temporary Sector Unprotect Timing Diagram ..............  61
Figure 24. Sector/Sector Block Protect and 
Unprotect Timing Diagram .............................................................  62
Alternate CE# Controlled Erase and Program Operations  ..... 63
Figure 25. Alternate CE# Controlled Write (Erase/Program) 
Operation Timings..........................................................................  64
Erase And Programming Performance. . . . . . . . 65
La t c h up Ch a r a c t e r is tic s. . . . . . . . . . . . .  . . . . . . . 65
TS O P  Pin C a pa c i t a nc e . . . . . . . . . . . . . .  . . . . . . . 65
Dat a  Ret e ntion. . . . . . . . . .  . . . . . . . . . . . . . . . . . . 65
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 66
LAB080—80-Ball Fortified Ball Grid Array 
10 x 15 mm package .............................................................. 66
Revis ion Summ a r y . . . . . .  . . . . . . . . . . . . . . . . . . 67

April 26, 2002 Am29PDL128G 5

ADVANCE INFORMATION

PRODUCT SELECTOR GUIDE

Note: See AC Characteristics section for ful l specifications.

BLOCK DIAGRAM

Notes:

1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is

A21-A-1.

2. RY/BY# is an open drain output.

Part Number Am29PDL128G

Sp eed Option Voltage Range: VCC = 3.0–3.6 V 70R

Voltage Range: VCC = 2.7–3.6 V 70 80 90

Max Access Time, ns (tACC)708090

Max CE# Access, ns (tCE)708090

Max P age Access, ns (tPACC)253035

Max OE# Access, ns (tOE)253040

VCC

VSS

State

Control

Command

Generator

VCC Detector Timer

Erase Voltage

Generator

Input/Output

Buffers

Sector

Switches

Chip Enable

Output Enable

Logic

Y-Gating

Cell Matrix

Address Latch

Y-Decoder

X-Decoder

Data Latch

RESET#

RY/BY# (Note 2)

STB

A21–A2

A1–A0

(A-1)

A3, A4

CE#

OE#

WE#

DQ31–DQ0

VIO

6 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

SIMULTANEOUS OPERATION BLOCK DIAGRAM

VCC

VSS

Bank 1 Address

Bank 2 Address

A21–A0

RESET#

WE#

CE#

DQ0–DQ15

DW/W#

WP#

ACC

STATE

CONTROL

COMMAND

RY/BY#

Bank 1

X-Decoder

OE# DW/W#

DQ31–DQ0

Status

Control

A21–A0

A21–A0A21–A0

DQ31–DQ0

Mux

Bank 2

X-Decoder

Y-gate

Bank 3

X-Decoder

Bank 4

X-Decoder

Y-gate

Bank 3 Address

Bank 4 Address

April 26, 2002 Am29PDL128G 7

ADVANCE INFORMATION

CONNECTION DIAGRAMS

Special Hand ling Ins truc tions for BGA

Packages

Special handling is required f or Flash Memory product s

in BGA packages.

Flash memory devices in BGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The p ac kage an d /or da ta i nte gr i ty m ay be c omp ro mi sed

if the package body is exposed to temperatures above

150°C for pr olonged peri ods of time.

B2 D2 E2 F2 G2 H2 J2

B3 D3 E3 F3 G3 H3 J3

B4 D4 E4 F4 G4 H4 J4

B5 D5 E5 F5 G5 H5 J5

B6 D6 E6 F6 G6 H6 J6

B7 D7 E7 F7 G7 H7 J7

DQ24 A19VIO

DQ26DQ13VSS

DQ15CE#

DQ8 A16DQ25DQ27DQ12DQ14DQ31/A-1A20

A14 A13DQ10RFUACCDQ29WE#WP#

A12 RFUVSS

RFURESET#DQ18A1A0

VSS A10DQ22DQ20DQ4VSS

DQ16A3

DQ23 A7

A17

A15

RFU

A11

A9DQ6DQ21DQ3VIO

DQ1VCC

B1 D1 E1 F1 G1 H1 J1

DQ7 A6VIO

DQ5DQ19DQ2DQ17DQ0

B8 D8

WORD#

A21

RFU

RY/BY#

C8 E8 F8 G8 H8 J8

DQ9 VCC

A18VSS

DQ11DQ28VIO

DQ30VSS

OE#

80-Ball Fortified BGA

Top Vie w, Balls Facing Down

8 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

PIN DESCRIPTION

A21–A0 = 22 Addresses

DQ30–DQ0 = 31 Data Inputs/Outputs

DQ31/A-1 = DQ31 (Data Input/Output, double

word mode), A-1 (LSB Address In-

put, word mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP# = Hardware Write Protect Input

ACC = Acceleration Input

RESET# = Hardware Reset Pin, Active Low

WORD# = Word Enable Input

At VIL, selects 16-bit mode,

At VIH, selects 32-bit mode

RY /BY # = Ready/Busy Output

VCC = 3.0 Volt-only Single Power Supply

(see Product Selecto r Guide for

speed options and voltage supply

tolerances)

VIO = Output Buffer Power Supply

VSS = Devi ce Ground

NC = Pin Not Connected Internally

RFU = Reserved for Futu re Use

LOGIC SYMBOL

22 32 or 16

DQ31–DQ0

(A-1)

A21–A0

CE#

OE#

WE#

RESET#

WORD#

RY/BY#

ACC

WP#

VIO

April 26, 2002 Am29PDL128G 9

ADVANCE INFORMATION

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The or der number (Valid Combination) is

formed by a combination of the following:

Valid Combinat ions

V al id Combinations list con figurations planned to be sup ported in

volume for this device. Consult the local AMD sales offi ce to con-

firm availability of specific valid combinations and to check on

newly released combi nat i ons.

Am29PDL128G 70 PE I OPTIONAL PROCESSING

Blank = Standard Processing

N = 16-byte ESN devices

(Cont act an AMD represent ative for more information)

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

PE = 80-Ball Fortified Ball Grid Array (FBGA)

1 mm pitch, 10 x 15 mm package (LAB080)

SPEED OPTIO N

See Product Selecto r Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29PDL128G

128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for BGA Packages

Order Number Package Marking

Am29PDL128G70R PEI PDL128G70R I

Am29PDL128G70 PDL128G70V

Am29PDL128G80 PEI,

PEE PDL128G80V I, E

Am29PDL128G90 PDL128G90V

10 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

DEVICE BUS OPERATIONS

This section describes the r equirements and use of

the device bus operation s, which are initiated through

the internal command register. The command register

itself does not occupy any addressable m emory loca -

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

regis ter serve as inputs to t he intern al state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts an d cont rol levels they requir e, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29PDL128G Device Bus Operation s

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’ t Care, SA = Sector Addres s,

AIN = Address In, DIN = Data In, DOUT = Data O ut

Notes:

1. Addres ses are A21–A0 in double word mode (WORD# = VIH), A21–A- 1 in word mode (WORD# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Pr ote ct i on ” s e c t ion .

W ord/Dou ble Word Configuration

The WORD# pin controls whether the device data I/O

pins operate in the word or double word configuration.

If the WORD# pin is set at VIH, the device is in double

word configuration, DQ31 –DQ0 are active and con-

trolled by CE# and OE#.

If the WORD# pin is set at VIL, the device is in word

configuration, and only data I/O pins DQ15–DQ 0 ar e

active and controlled by CE# and OE#. The data I/O

pins DQ 30–DQ16 are tri-stated, and the DQ31 pin is

used as an input for the least significant address bit

(LSB) function, which is named A-1.

Requirements for Reading Array Data

To r ead array data from t he output s, the sys tem mu st

driv e the C E# a nd OE# pins to VIL. C E # is the po wer

control and s elects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at VIH. The WORD# pin determines

whether the device outputs array data in words or dou-

ble words.

The internal stat e machine is set for reading ar ray data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

ma nd is nec ess ary in this mode to obta in array dat a.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Refer to the AC Read-Only Operations table for timing

specifications and to Figure 11 for the timing diagram .

ICC1 in the DC Characteristics table represents the ac-

tive cur rent specification for reading array data.

Random Read (Non-Page Read)

Add ress ac cess t ime (tACC) is equal to the d elay fro m

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable ad-

dresses an d stable CE# to valid d ata at the output in-

puts. The output enable access tim e is the delay from

the falling edge of the O E# to v alid data a t the out put

Operation CE# OE# WE# RESET# WP# Addresses

(Note 1)

DQ31–DQ16

DQ15–

DQ0

WORD#

= VIH

WORD#

= VIL

Read L L H H X AIN DOUT DQ30–DQ16 =

High-Z , DQ31 = A-1 DOUT

Write L H L H X AIN DIN DIN

Standby VCC ±

0.3 V XXVCC ±

0.3 V X X High-Z High-Z High-Z

Output Disable L H H H X X High-Z High-Z High-Z

Reset X X X L X X High-Z High-Z High-Z

Temporary Sector

Unprotec t (High Voltage) XXX V

ID XA

IN DIN XD

April 26, 2002 Am29PDL128G 11

ADVANCE INFORMATION

inputs ( assuming the a ddresses have been st able for

at least tACC–tOE time).

Page Mode Read

The dev ice is cap ab le of f as t page mo de read and is

compati ble with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for r ando m lo cat ions with in a pa ge. The pa ge s ize of

the device is 8 words, or 4 double words, with the ap-

propriate page being selected by the higher address

bits A21–A2 and the LSB bits A1–A0 (in the double

word mo de) and A1 t o A -1 (in th e wo rd mo de) deter -

mining the specific word/double word within that page.

This is an asy nchronous opera tion w ith the micropro -

cessor s upplyin g the spec ific word or doub le word lo -

cation.

The random or initial page access is equal to tACC or

tCE and subsequent page read accesses (as long as

the locations specified by the microprocessor falls

wit hin th a t pag e) i s eq ui vale nt t o tPACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is tACC or tCE. Here again, CE# selects

the device and OE# is the output control and should

be used to gate data to the output inputs if the device

is selec ted. Fast page mode access es are obtained by

keeping A 21–A2 constant and changing A1 to A0 to

select the specific double word, or changing A1 to A-1

to select the specific word, within that page.

Ta b le 2. Pa ge Sel e c t , D o uble Wor d M od e

Table 3. Page Select, Word Mode

Simultaneous Operation

Th e dev ice i s capab le of read ing da ta fr om o ne bank

of memory while a program or erase operation is in

progress in another bank of memory (s imultaneous

operation), in addition to the conventional features

(r ead, prog ram, er ase-su spend rea d, and er ase-su s-

pend program). The bank selected can be selected by

bank addresses (A21–A19) with zero latency.

The simultaneous operation can execute multi-func-

tion mode in the same bank.

Table 4. Bank Select

W r iti ng Comma nds/Command Sequence s

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the WORD# pin determines

whether the device ac cepts program data in double

words or words. Refer to “W ord/Double Word Configu-

ration” for more information.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once a bank enters the Un-

lock Bypass mode, onl y two write cycle s are requi red

to program a double word or word, instead of four. The

“Double Word/Word Program Command Sequence”

section has details on programming data to the device

using both standard and Unloc k Bypass command se-

quences.

An erase operation can erase one sector, multipl e sec-

tors, or the entire devic e. Table 5 indic ates the address

spac e that e ach sector occupi es. A “b ank add ress” is

the address b its required to uniquely select a bank .

Similarly, a “se ctor address” refers to the address bits

required to uniquely select a sector. The “Command

Definitions” s ection has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Word A1 A0

Double Word 0 0 0

Double Word 1 0 1

Double Word 2 1 0

Double Word 3 1 1

Word A1 A0 A-1

Word 0 0 0 0

Word 1 0 0 1

Word 2 0 1 0

Word 3 0 1 1

Word 4 1 0 0

Word 5 1 0 1

Word 6 1 1 0

Word 7 1 1 1

Bank A21–A19

Bank 1 000

Ban k 2 001, 010, 011

Ban k 3 100, 101, 110

Bank 4 111

12 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory. 
If the sy stem asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and us es the hi gher vo ltage  on  th e pin to red uce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration.  Note  that  VHH must not be asserted on ACC
for operations other than accelerated programm ing, or
device damage may result. 
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters  the autoselect mode. The
system  can then  read autoselect codes from t he inter-
nal register (which is separate from the memory array)
on D Q15 –DQ0. Standard read cycle timings apply in
this mode. Ref er to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this m ode, cur rent cons umption i s greatly  reduce d,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and RESET# p ins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage ran ge than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either  of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is  complet ed.
ICC3 in th e DC Characteristics table represents the
CMOS standby current specification. 
Automatic Sleep Mode
The aut om atic sleep mode minimiz es  Flash device  en-
erg y cons umptio n. The de vice au tomat icall y e nables
this m ode when addre sses remain sta ble for tACC +
30 ns. The automa tic sleep mode is indepe ndent of
the CE#, WE#, and OE#  control signals. Standard ad-
dress access timings provide new data when ad-
dresses  are changed. While in sleep mode, output
data is latched  and always available to the sy stem .
Note that dur ing automat ic sleep mode, O E# must be
at VIH  before the de vice re duces cur rent to the  stated
slee p mod e spe cifica tion. I CC5 in the DC  Char acteri s-
tics table represents the automatic sleep mo de cu rrent
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting t he dev ice to reading array data. When the RE-
SE T# pin  is dr iven l ow fo r at le ast a p eriod  of t RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/wr ite comm ands for  the du ration of t he RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that  was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration  of the RESET#
pulse. When RESET# is held at VSS±0.3 V,  t he device
draws CMOS s t andby  c ur r ent (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current wil l
be greater.
The RESET# pin may be  tied to the system reset cir-
cuitry. A sy stem reset would thus also r eset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RE SET#  is asser ted duri ng a pr ogram  or era se op-
eration,  the RY/BY # pin remains  a “0” (bus y) until the
int ernal res et op eration  is comp lete, wh ich r equires  a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is c omplete. If RESET# is
asserted when a program or eras e oper ation is not ex-
ecuting (R Y/BY# pin is “1”), the reset operation is com-
pleted within a time of tREADY (not during Embedded
Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables  for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins (except for RY/BY#) are
placed in the high impedance state.

April 26, 2002 Am29PDL128G 13

ADVANCE INFORMATION

Table 5. Sector Address Table

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

Bank 1

SA0 00000000000 4/2 00000h–00FFFh 000000h–0007FFh

SA1 00000000001 4/2 01000h–01FFFh 000800h–000FFFh

SA2 00000000010 4/2 02000h–02FFFh 001000h–0017FFh

SA3 00000000011 4/2 03000h–03FFFh 001800h–001FFFh

SA4 00000000100 4/2 04000h–04FFFh 002000h–0027FFh

SA5 00000000101 4/2 05000h–05FFFh 002800h–002FFFh

SA6 00000000110 4/2 06000h–06FFFh 003000h–0037FFh

SA7 00000000111 4/2 07000h–07FFFh 003800h–003FFFh

SA8 00000001XXX 32/16 08000h–0FFFFh 004000h–007FFFh

SA9 00000010XXX 32/16 10000h–17FFFh 008000h–00BFFFh

SA10 00000011XXX 32/16 18000h–1FFFFh 00C000h–00FFFFh

SA11 00000100XXX 32/16 20000h–27FFFh 010000h–013FFFh

SA12 00000101XXX 32/16 28000h–2FFFFh 014000h–017FFFh

SA13 00000110XXX 32/16 30000h–37FFFh 018000h–01BFFFh

SA14 00000111XXX 32/16 38000h–3FFFFh 01C000h–01FFFFh

SA15 00001000XXX 32/16 40000h–47FFFh 020000h–023FFFh

SA16 00001001XXX 32/16 48000h–4FFFFh 024000h–027FFFh

SA17 00001010XXX 32/16 50000h–57FFFh 028000h–02BFFFh

SA18 00001011XXX 32/16 58000h–5FFFFh 02C000h–02FFFFh

SA19 00001100XXX 32/16 60000h–67FFFh 030000h–033FFFh

SA20 00001101XXX 32/16 68000h–6FFFFh 034000h–037FFFh

SA21 00001110XXX 32/16 70000h–77FFFh 038000h–03BFFFh

SA22 00001111XXX 32/16 78000h–7FFFFh 03C000h–03FFFFh

SA23 00010000XXX 32/16 80000h–87FFFh 040000h–043FFFh

SA24 00010001XXX 32/16 88000h–8FFFFh 044000h–047FFFh

SA25 00010010XXX 32/16 90000h–97FFFh 048000h–04BFFFh

SA26 00010011XXX 32/16 98000h–9FFFFh 04C000h–04FFFFh

SA27 00010100XXX 32/16 A0000h–A7FFFh 050000h–053FFFh

SA28 00010101XXX 32/16 A8000h–AFFFFh 054000h–057FFFh

SA29 00010110XXX 32/16 B0000h–B7FFFh 058000h–05BFFFh

SA30 00010111XXX 32/16 B8000h–BFFFFh 05C000h–05FFFFh

SA31 00011000XXX 32/16 C0000h–C7FFFh 060000h–063FFFh

SA32 00011001XXX 32/16 C8000h–CFFFFh 064000h–067FFFh

SA33 00011010XXX 32/16 D0000h–D7FFFh 068000h–06BFFFh

SA34 00011011XXX 32/16 D8000h–DFFFFh 06C000h–06FFFFh

SA35 00011100XXX 32/16 E0000h–E7FFFh 070000h–073FFFh

SA36 00011101XXX 32/16 E8000h–EFFFFh 074000h–077FFFh

SA37 00011110XXX 32/16 F0000h–F7FFFh 078000h–07BFFFh

SA38 00011111XXX 32/16 F8000h–FFFFFh 07C000–07FFFFh

14 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Bank 2

SA39 00100000XXX 32/16 100000h–107FFFh 080000h–083FFFh

SA40 00100001XXX 32/16 108000h–10FFFFh 084000h–087FFFh

SA41 00100010XXX 32/16 110000h–117FFFh 088000h–08BFFFh

SA42 00100011XXX 32/16 118000h–11FFFFh 08C000h–08FFFFh

SA43 00100100XXX 32/16 120000h–127FFFh 090000h–093FFFh

SA44 00100101XXX 32/16 128000h–12FFFFh 094000h–097FFFh

SA45 00100110XXX 32/16 130000h–137FFFh 098000h–09BFFFh

SA46 00100111XXX 32/16 138000h–13FFFFh 09C000h–09FFFFh

SA47 00101000XXX 32/16 140000h–147FFFh 0A0000h–0A3FFFh

SA48 00101001XXX 32/16 148000h–14FFFFh 0A4000h–0A7FFFh

SA49 00101010XXX 32/16 150000h–157FFFh 0A8000h–0ABFFFh

SA50 00101011XXX 32/16 158000h–15FFFFh 0AC000h–0AFFFFh

SA51 00101100XXX 32/16 160000h–167FFFh 0B0000h–0B3FFFh

SA52 00101101XXX 32/16 168000h–16FFFFh 0B4000h–0B7FFFh

SA53 00101110XXX 32/16 170000h–177FFFh 0B8000h–0BBFFFh

SA54 00101111XXX 32/16 178000h–17FFFFh 0BC000h–0BFFFFh

SA55 00110000XXX 32/16 180000h–187FFFh 0C0000h–0C3FFFh

SA56 00110001XXX 32/16 188000h–18FFFFh 0C4000h–0C7FFFh

SA57 00110010XXX 32/16 190000h–197FFFh 0C8000h–0CBFFFh

SA58 00110011XXX 32/16 198000h–19FFFFh 0CC000h–0CFFFFh

SA59 00110100XXX 32/16 1A0000h–1A7FFFh 0D0000h–0D3FFFh

SA60 00110101XXX 32/16 1A8000h–1AFFFFh 0D4000h–0D7FFFh

SA61 00110110XXX 32/16 1B0000h–1B7FFFh 0D8000h–0DBFFFh

SA62 00110111XXX 32/16 1B8000h–1BFFFFh 0DC000h–0DFFFFh

SA63 00111000XXX 32/16 1C0000h–1C7FFFh 0E0000h–0E3FFFh

SA64 00111001XXX 32/16 1C8000h–1CFFFFh 0E4000h–0E7FFFh

SA65 00111010XXX 32/16 1D0000h–1D7FFFh 0E8000h–0EBFFFh

SA66 00111011XXX 32/16 1D8000h–1DFFFFh 0EC000h–0EFFFFh

SA67 00111100XXX 32/16 1E0000h–1E7FFFh 0F0000h–0F3FFFh

SA68 00111101XXX 32/16 1E8000h–1EFFFFh 0F4000h–0F7FFFh

SA69 00111110XXX 32/16 1F0000h–1F7FFFh 0F8000h–0FBFFFh

SA70 00111111XXX 32/16 1F8000h–1FFFFFh 0FC000h–0FFFFFh

SA71 01000000XXX 32/16 200000h–207FFFh 100000h–103FFFh

SA72 01000001XXX 32/16 208000h–20FFFFh 104000h–107FFFh

SA73 01000010XXX 32/16 210000h–217FFFh 108000h–10BFFFh

SA74 01000011XXX 32/16 218000h–21FFFFh 10C000h–10FFFFh

SA75 01000100XXX 32/16 220000h–227FFFh 110000h–113FFFh

SA76 01000101XXX 32/16 228000h–22FFFFh 114000h–117FFFh

SA77 01000110XXX 32/16 230000h–237FFFh 118000h–11BFFFh

SA78 01000111XXX 32/16 238000h–23FFFFh 11C000h–11FFFFh

SA79 01001000XXX 32/16 240000h–247FFFh 120000h–123FFFh

SA80 01001001XXX 32/16 248000h–24FFFFh 124000h–127FFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

April 26, 2002 Am29PDL128G 15

ADVANCE INFORMATION

Ba nk 2 (continued)

SA81 01001010XXX 32/16 250000h–257FFFh 128000h–12BFFFh

SA82 01001011XXX 32/16 258000h–25FFFFh 12C000h–12FFFFh

SA83 01001100XXX 32/16 260000h–267FFFh 130000h–133FFFh

SA84 01001101XXX 32/16 268000h–26FFFFh 134000h–137FFFh

SA85 01001110XXX 32/16 270000h–277FFFh 138000h–13BFFFh

SA86 01001111XXX 32/16 278000h–27FFFFh 13C000h–13FFFFh

SA87 01010000XXX 32/16 280000h–287FFFh 140000h–143FFFh

SA88 01010001XXX 32/16 288000h–28FFFFh 144000h–147FFFh

SA89 01010010XXX 32/16 290000h–297FFFh 148000h–14BFFFh

SA90 01010011XXX 32/16 298000h–29FFFFh 14C000h–14FFFFh

SA91 01010100XXX 32/16 2A0000h–2A7FFFh 150000h–153FFFh

SA92 01010101XXX 32/16 2A8000h–2AFFFFh 154000h–157FFFh

SA93 01010110XXX 32/16 2B0000h–2B7FFFh 158000h–15BFFFh

SA94 01010111XXX 32/16 2B8000h–2BFFFFh 15C000h–15FFFFh

SA95 01011000XXX 32/16 2C0000h–2C7FFFh 160000h–163FFFh

SA96 01011001XXX 32/16 2C8000h–2CFFFFh 164000h–167FFFh

SA97 01011010XXX 32/16 2D0000h–2D7FFFh 168000h–16BFFFh

SA98 01011011XXX 32/16 2D8000h–2DFFFFh 16C000h–16FFFFh

SA99 01011100XXX 32/16 2E0000h–2E7FFFh 170000h–173FFFh

SA100 01011101XXX 32/16 2E8000h–2EFFFFh 174000h–177FFFh

SA101 01011110XXX 32/16 2F0000h–2F7FFFh 178000h–17BFFFh

SA102 01011111XXX 32/16 2F8000h–2FFFFFh 17C000h–17FFFFh

SA103 01100000XXX 32/16 300000h–307FFFh 180000h–183FFFh

SA104 01100001XXX 32/16 308000h–30FFFFh 184000h–187FFFh

SA105 01100010XXX 32/16 310000h–317FFFh 188000h–18BFFFh

SA106 01100011XXX 32/16 318000h–31FFFFh 18C000h–18FFFFh

SA107 01100100XXX 32/16 320000h–327FFFh 190000h–193FFFh

SA108 01100101XXX 32/16 328000h–32FFFFh 194000h–197FFFh

SA109 01100110XXX 32/16 330000h–337FFFh 198000h–19BFFFh

SA110 01100111XXX 32/16 338000h–33FFFFh 19C000h–19FFFFh

SA111 01101000XXX 32/16 340000h–347FFFh 1A0000h–1A3FFFh

SA112 01101001XXX 32/16 348000h–34FFFFh 1A4000h–1A7FFFh

SA113 01101010XXX 32/16 350000h–357FFFh 1A8000h–1ABFFFh

SA114 01101011XXX 32/16 358000h–35FFFFh 1AC000h–1AFFFFh

SA115 01101100XXX 32/16 360000h–367FFFh 1B0000h–1B3FFFh

SA116 01101101XXX 32/16 368000h–36FFFFh 1B4000h–1B7FFFh

SA117 01101110XXX 32/16 370000h–377FFFh 1B8000h–1BBFFFh

SA118 01101111XXX 32/16 378000h–37FFFFh 1BC000h–1BFFFFh

SA119 01110000XXX 32/16 380000h–387FFFh 1C0000h–1C3FFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

16 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Bank 2 (continued)

SA120 01110001XXX 32/16 388000h–38FFFFh 1C4000h–1C7FFFh

SA121 01110010XXX 32/16 390000h–397FFFh 1C8000h–1CBFFFh

SA122 01110011XXX 32/16 398000h–39FFFFh 1CC000h–1CFFFFh

SA123 01110100XXX 32/16 3A0000h–3A7FFFh 1D0000h–1D3FFFh

SA124 01110101XXX 32/16 3A8000h–3AFFFFh 1D4000h–1D7FFFh

SA125 01110110XXX 32/16 3B0000h–3B7FFFh 1D8000h–1DBFFFh

SA126 01110111XXX 32/16 3B8000h–3BFFFFh 1DC000h–1DFFFFh

SA127 01111000XXX 32/16 3C0000h–3C7FFFh 1E0000h–1E3FFFh

SA128 01111001XXX 32/16 3C8000h–3CFFFFh 1E4000h–1E7FFFh

SA129 01111010XXX 32/16 3D0000h–3D7FFFh 1E8000h–1EBFFFh

SA130 01111011XXX 32/16 3D8000h–3DFFFFh 1EC000h–1EFFFFh

SA131 01111100XXX 32/16 3E0000h–3E7FFFh 1F0000h–1F3FFFh

SA132 01111101XXX 32/16 3E8000h–3EFFFFh 1F4000h–1F7FFFh

SA133 01111110XXX 32/16 3F0000h–3F7FFFh 1F8000h–1FBFFFh

SA134 01111111XXX 32/16 3F8000h–3FFFFFh 1FC000h–1FFFFFh

Bank 3

SA135 10000000XXX 32/16 400000h–407FFFh 200000h–203FFFh

SA136 10000001XXX 32/16 408000h–40FFFFh 204000h–207FFFh

SA137 10000010XXX 32/16 410000h–417FFFh 208000h–20BFFFh

SA138 10000011XXX 32/16 418000h–41FFFFh 20C000h–20FFFFh

SA139 10000100XXX 32/16 420000h–427FFFh 210000h–213FFFh

SA140 10000101XXX 32/16 428000h–42FFFFh 214000h–217FFFh

SA141 10000110XXX 32/16 430000h–437FFFh 218000h–21BFFFh

SA142 10000111XXX 32/16 438000h–43FFFFh 21C000h–21FFFFh

SA143 10001000XXX 32/16 440000h–447FFFh 220000h–223FFFh

SA144 10001001XXX 32/16 448000h–44FFFFh 224000h–227FFFh

SA145 10001010XXX 32/16 450000h–457FFFh 228000h–22BFFFh

SA146 10001011XXX 32/16 458000h–45FFFFh 22C000h–22FFFFh

SA147 10001100XXX 32/16 460000h–467FFFh 230000h–233FFFh

SA148 10001101XXX 32/16 468000h–46FFFFh 234000h–237FFFh

SA149 10001110XXX 32/16 470000h–477FFFh 238000h–23BFFFh

SA150 10001111XXX 32/16 478000h–47FFFFh 23C000h–23FFFFh

SA151 10010000XXX 32/16 480000h–487FFFh 240000h–243FFFh

SA152 10010001XXX 32/16 488000h–48FFFFh 244000h–247FFFh

SA153 10010010XXX 32/16 490000h–497FFFh 248000h–24BFFFh

SA154 10010011XXX 32/16 498000h–49FFFFh 24C000h–24FFFFh

SA155 10010100XXX 32/16 4A0000h–4A7FFFh 250000h–253FFFh

SA156 10010101XXX 32/16 4A8000h–4AFFFFh 254000h–257FFFh

SA157 10010110XXX 32/16 4B0000h–4B7FFFh 258000h–25BFFFh

SA158 10010111XXX 32/16 A48000h–4BFFFFh 25C000h–25FFFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

April 26, 2002 Am29PDL128G 17

ADVANCE INFORMATION

Ba nk 3 (continued)

SA159 10011000XXX 32/16 4C0000h–4C7FFFh 260000h–263FFFh

SA160 10011001XXX 32/16 4C8000h–4CFFFFh 264000h–267FFFh

SA161 10011010XXX 32/16 4D0000h–4D7FFFh 268000h–26BFFFh

SA162 10011011XXX 32/16 4D8000h–4DFFFFh 26C000h–26FFFFh

SA163 10011100XXX 32/16 4E0000h–4E7FFFh 270000h–273FFFh

SA164 10011101XXX 32/16 4E8000h–4EFFFFh 274000h–277FFFh

SA165 10011110XXX 32/16 4F0000h–4F7FFFh 278000h–27BFFFh

SA166 10011111XXX 32/16 4F8000h–4FFFFFh 27C000h–27FFFFh

SA167 10100000XXX 32/16 500000h–507FFFh 280000h–283FFFh

SA168 10100001XXX 32/16 508000h–50FFFFh 284000h–287FFFh

SA169 10100010XXX 32/16 510000h–517FFFh 288000h–28BFFFh

SA170 10100011XXX 32/16 518000h–51FFFFh 28C000h–28FFFFh

SA171 10100100XXX 32/16 520000h–527FFFh 290000h–293FFFh

SA172 10100101XXX 32/16 528000h–52FFFFh 294000h–297FFFh

SA173 10100110XXX 32/16 530000h–537FFFh 298000h–29BFFFh

SA174 10100111XXX 32/16 538000h–53FFFFh 29C000h–29FFFFh

SA175 10101000XXX 32/16 540000h–547FFFh 2A0000h–2A3FFFh

SA176 10101001XXX 32/16 548000h–54FFFFh 2A4000h–2A7FFFh

SA177 10101010XXX 32/16 550000h–557FFFh 2A8000h–2ABFFFh

SA178 10101011XXX 32/16 558000h–55FFFFh 2AC000h–2AFFFFh

SA179 10101100XXX 32/16 560000h–567FFFh 2B0000h–2B3FFFh

SA180 10101101XXX 32/16 568000h–56FFFFh 2B4000h–2B7FFFh

SA181 10101110XXX 32/16 570000h–577FFFh 2B8000h–2BBFFFh

SA182 10101111XXX 32/16 578000h–57FFFFh 2BC000h–2BFFFFh

SA183 10110000XXX 32/16 580000h–587FFFh 2C0000h–2C3FFFh

SA184 10110001XXX 32/16 588000h–58FFFFh 2C4000h–2C7FFFh

SA185 10110010XXX 32/16 590000h–597FFFh 2C8000h–2CBFFFh

SA186 10110011XXX 32/16 598000h–59FFFFh 2CC000h–2CFFFFh

SA187 10110100XXX 32/16 5A0000h–5A7FFFh 2D0000h–2D3FFFh

SA188 10110101XXX 32/16 5A8000h–5AFFFFh 2D4000h–2D7FFFh

SA189 10110110XXX 32/16 5B0000h–5B7FFFh 2D8000h–2DBFFFh

SA190 10110111XXX 32/16 5B8000h–5BFFFFh 2DC000h–2DFFFFh

SA191 10111000XXX 32/16 5C0000h–5C7FFFh 2E0000h–2E3FFFh

SA192 10111001XXX 32/16 5C8000h–5CFFFFh 2E4000h–2E7FFFh

SA193 10111010XXX 32/16 5D0000h–5D7FFFh 2E8000h–2EBFFFh

SA194 10111011XXX 32/16 5D8000h–5DFFFFh 2EC000h–2EFFFFh

SA195 10111100XXX 32/16 5E0000h–5E7FFFh 2F0000h–2F3FFFh

SA196 10111101XXX 32/16 5E8000h–5EFFFFh 2F4000h–2F7FFFh

SA197 10111110XXX 32/16 5F0000h–5F7FFFh 2F8000h–2FBFFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

18 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Bank 3 (continued)

SA198 10111111XXX 32/16 5F8000h–5FFFFFh 2FC000h–2FFFFFh

SA199 11000000XXX 32/16 600000h–607FFFh 300000h–303FFFh

SA200 11000001XXX 32/16 608000h–60FFFFh 304000h–307FFFh

SA201 11000010XXX 32/16 610000h–617FFFh 308000h–30BFFFh

SA202 11000011XXX 32/16 618000h–61FFFFh 30C000h–30FFFFh

SA203 11000100XXX 32/16 620000h–627FFFh 310000h–313FFFh

SA204 11000101XXX 32/16 628000h–62FFFFh 314000h–317FFFh

SA205 11000110XXX 32/16 630000h–637FFFh 318000h–31BFFFh

SA206 11000111XXX 32/16 638000h–63FFFFh 31C000h–31FFFFh

SA207 11001000XXX 32/16 640000h–647FFFh 320000h–323FFFh

SA208 11001001XXX 32/16 648000h–64FFFFh 324000h–327FFFh

SA209 11001010XXX 32/16 650000h–657FFFh 328000h–32BFFFh

SA210 11001011XXX 32/16 658000h–65FFFFh 32C000h–32FFFFh

SA211 11001100XXX 32/16 660000h–667FFFh 330000h–333FFFh

SA212 11001101XXX 32/16 668000h–66FFFFh 334000h–337FFFh

SA213 11001110XXX 32/16 670000h–677FFFh 338000h–33BFFFh

SA214 11001111XXX 32/16 678000h–67FFFFh 33C000h–33FFFFh

SA215 11010000XXX 32/16 680000h–687FFFh 340000h–343FFFh

SA216 11010001XXX 32/16 688000h–68FFFFh 344000h–347FFFh

SA217 11010010XXX 32/16 690000h–697FFFh 348000h–34BFFFh

SA218 11010011XXX 32/16 698000h–69FFFFh 34C000h–34FFFFh

SA219 11010100XXX 32/16 6A0000h–6A7FFFh 350000h–353FFFh

SA220 11010101XXX 32/16 6A8000h–6AFFFFh 354000h–357FFFh

SA221 11010110XXX 32/16 6B0000h–6B7FFFh 358000h–35BFFFh

SA222 11010111XXX 32/16 6B8000h–6BFFFFh 35C000h–35FFFFh

SA223 11011000XXX 32/16 6C0000h–6C7FFFh 360000h–363FFFh

SA224 11011001XXX 32/16 6C8000h–6CFFFFh 364000h–367FFFh

SA225 11011010XXX 32/16 6D0000h–6D7FFFh 368000h–36BFFFh

SA226 11011011XXX 32/16 6D8000h–6DFFFFh 36C000h–36FFFFh

SA227 11011100XXX 32/16 6E0000h–6E7FFFh 370000h–373FFFh

SA228 11011101XXX 32/16 6E8000h–6EFFFFh 374000h–377FFFh

SA229 11011110XXX 32/16 6F0000h–6F7FFFh 378000h–37BFFFh

SA230 11011111XXX 32/16 6F8000h–6FFFFFh 37C000h–37FFFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

April 26, 2002 Am29PDL128G 19

ADVANCE INFORMATION

Note: T he addr es s r ange is A2 1: A-1 in word mod e (WORD#= VIL) or A21:A0 in d ouble wo rd mode ( WORD#=VIH). Ad dre ss bit s A2 1:A 11 uniq uel y

sele ct a sector ; a ddress b its A 21: A 19 un ique l y sele ct a ban k.

Bank 4

SA231 11100000XXX 32/16 700000h–707FFFh 380000h–383FFFh

SA232 11100001XXX 32/16 708000h–70FFFFh 384000h–387FFFh

SA233 11100010XXX 32/16 710000h–717FFFh 388000h–38BFFFh

SA234 11100011XXX 32/16 718000h–71FFFFh 38C000h–38FFFFh

SA235 11100100XXX 32/16 720000h–727FFFh 390000h–393FFFh

SA236 11100101XXX 32/16 728000h–72FFFFh 394000h–397FFFh

SA237 11100110XXX 32/16 730000h–737FFFh 398000h–39BFFFh

SA238 11100111XXX 32/16 738000h–73FFFFh 39C000h–39FFFFh

SA239 11101000XXX 32/16 740000h–747FFFh 3A0000h–3A3FFFh

SA240 11101001XXX 32/16 748000h–74FFFFh 3A4000h–3A7FFFh

SA241 11101010XXX 32/16 750000h–757FFFh 3A8000h–3ABFFFh

SA242 11101011XXX 32/16 758000h–75FFFFh 3AC000h–3AFFFFh

SA243 11101100XXX 32/16 760000h–767FFFh 3B0000h–3B3FFFh

SA244 11101101XXX 32/16 768000h–76FFFFh 3B4000h–3B7FFFh

SA245 11101110XXX 32/16 770000h–777FFFh 3B8000h–3BBFFFh

SA246 11101111XXX 32/16 778000h–77FFFFh 3BC000h–3BFFFFh

SA247 11110000XXX 32/16 780000h–787FFFh 3C0000h–3C3FFFh

SA248 11110001XXX 32/16 788000h–78FFFFh 3C4000h–3C7FFFh

SA249 11110010XXX 32/16 790000h–797FFFh 3C8000h–3CBFFFh

SA250 11110011XXX 32/16 798000h–79FFFFh 3CC000h–3CFFFFh

SA251 11110100XXX 32/16 7A0000h–7A7FFFh 3D0000h–3D3FFFh

SA252 11110101XXX 32/16 7A8000h–7AFFFFh 3D4000h–3D7FFFh

SA253 11110110XXX 32/16 7B0000h–7B7FFFh 3D8000h–3DBFFFh

SA254 11110111XXX 32/16 7B8000h–7BFFFFh 3DC000h–3DFFFFh

SA255 11111000XXX 32/16 7C0000h–7C7FFFh 3E0000h–3E3FFFh

SA256 11111001XXX 32/16 7C8000h–7CFFFFh 3E4000h–3E7FFFh

SA257 11111010XXX 32/16 7D0000h–7D7FFFh 3E8000h–3EBFFFh

SA258 11111011XXX 32/16 7D8000h–7DFFFFh 3EC000h–3EFFFFh

SA259 11111100XXX 32/16 7E0000h–7E7FFFh 3F0000h–3F3FFFh

SA260 11111101XXX 32/16 7E8000h–7EFFFFh 3F4000h–3F7FFFh

SA261 11111110XXX 32/16 7F0000h–7F7FFFh 3F8000h–3FBFFFh

SA262 11111111000 4/2 7F8000h–7F8FFFh 3FC000h–3FC7FFh

SA263 11111111001 4/2 7F9000h–7F9FFFh 3FC800h–3FCFFFh

SA264 11111111010 4/2 7FA000h–7FAFFFh 3FD000h–3FD7FFh

SA265 11111111011 4/2 7FB000h–7FBFFFh 3FD800h–3FDFFFh

SA266 11111111100 4/2 7FC000h–7FCFFFh 3FE000h–3FE7FFh

SA267 11111111101 4/2 7FD000h–7FDFFFh 3FE800h–3FEFFFh

SA268 11111111110 4/2 7FE000h–7FEFFFh 3FF000h–3FF7FFh

SA269 11111111111 4/2 7FF000h–7FFFFFh 3FF800h–3FFFFFh

Table 5. S ector Address Table (Continued)

Bank Sector Sector Address

(A21-A11)

Sector Size

(Kwords/

Kdoublewords) Address Range

(x16) Address Range

(x32)

20 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Table 6.  SecSi Sector Addresses
Autosele ct Mo de
The autoselect mode provides manufacturer and de-
vic e identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect code s can also be
accessed in-system through the c ommand register.
When  using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
must be as shown in Table 7. In addition, when verify-
ing sector protection, the sec tor address must appear
on the appropriate highest order address  bits (see
Table  5). Table  7 sho ws the r emain ing address bits
that are don’t care.  When all necessary bi ts have been
set as  req uired, t he pr ogr am ming  equipm ent may then
read the corresponding identifier code on DQ7–DQ0.
Howev er, the autos elect co des can als o be acc essed
in-system through the command register, for  ins tances
when the device is erased or programmed in a system
without access to high voltage on the A9 pin. The
command sequence is illustrated in Tables 14 and  16.
Note that if a Bank Address (BA) on address bits A21,
A20, and A19 is asserted during the third write cycle of
the autoselect com man d, the h ost sy stem  can  read
autoselect data that bank and then immediately read
array data from the other bank, without exiting the au-
toselect mode.
To access the autoselec t codes  in-system, the host
system can issue the autoselect command via the
command register, as shown in Tables 14 and 16. Th i s
method does not require VID. Refe r to the Autoselect
Command Sequence section for more information.
Table 7. Autoselect Codes (High Voltage Method)  
Legend: L = Logic Low = V IL, H = Logi c Hi gh = VIH,  BA = Bank Address, SA = Se ctor Ad dress,  X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences.
Device Sector Size (x32)
Address Range (x16)
Address Range
Am29PDL128G 128 words/6 4 doubl e 
words  000000h–00003Fh 000000h–00007Fh
Description CE# OE# WE#
A21
to 
A11 A10 A9 A8 A7 A6
A5
to
A4 A3 A2 A1 A0
DQ31 to DQ8
(Word/Double 
Word) DQ7
to  DQ0
Manu f ac t urer I D: 
AMD LLHXX
VID XXLXLLLL 000000h 01h
De vi ce ID
Read 
Cycle 1
LLHXX
VID XL
L
L
LLLH 22h/
222222h 7Eh
Read 
Cycle 2 L HHHL 22h/
222222h 0Dh
Read 
Cycle 3 L HHHH 22h/
222222h 00h
Sector  Prot ect i on 
Verification LLHSAX
VID XLLLLLHL 00h/
000000h 01h (protected),
00h (unprotected)
SecSi Indicator Bit 
(DQ7) LLHXX
VID XXLXLLHH 00h/
000000h
80h 
(factory locked),
00h (not factory 
locked)

April 26, 2002 Am29PDL128G 21

ADVANCE INFORMATION

Table 8. Sector Block Addresses for Protection/Unprotection

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

SGA0 00000000000 SA0

SGA1 00000000001 SA1

SGA2 00000000010 SA2

SGA3 00000000011 SA3

SGA4 00000000100 SA4

SGA5 00000000101 SA5

SGA6 00000000110 SA6

SGA7 00000000111 SA7

SGA8 000000

X X X SA8 to SA1010

SGA9 0 0 0 0 0 1 X X X X X SA11 to SA14

SGA10 0 0 0 0 1 0 X X X X X SA15 to SA18

SGA11 0 0 0 0 1 1 X X X X X SA19 to SA22

SGA12 0 0 0 1 0 0 X X X X X SA23 to SA26

SGA13 0 0 0 1 0 1 X X X X X SA27 to SA30

SGA14 0 0 0 1 1 0 X X X X X SA31 to SA34

SGA15 0 0 0 1 1 1 X X X X X SA35 to SA38

SGA16 0 0 1 0 0 0 X X X X X SA39 to SA42

SGA17 0 0 1 0 0 1 X X X X X SA43 to SA46

SGA18 0 0 1 0 1 0 X X X X X SA47 to SA50

SGA19 0 0 1 0 1 1 X X X X X SA51 to SA54

SGA20 0 0 1 1 0 0 X X X X X SA55 to SA58

SGA21 0 0 1 1 0 1 X X X X X SA59 to SA62

SGA22 0 0 1 1 1 0 X X X X X SA63 to SA66

SGA23 0 0 1 1 1 1 X X X X X SA67 to SA70

SGA24 0 1 0 0 0 0 X X X X X SA71 to SA74

SGA25 0 1 0 0 0 1 X X X X X SA75 to SA78

SGA26 0 1 0 0 1 0 X X X X X SA79 to SA82

SGA27 0 1 0 0 1 1 X X X X X SA83 to SA86

SGA28 0 1 0 1 0 0 X X X X X SA87 to SA90

SGA29 0 1 0 1 0 1 X X X X X SA91 to SA94

SGA30 0 1 0 1 1 0 X X X X X SA95 to SA98

SGA31 0 1 0 1 1 1 X X X X X SA99 to SA102

22 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

SGA32 0 1 1 0 0 0 X X X X X SA103 to SA106

SGA33 0 1 1 0 0 1 X X X X X SA107 to SA110

SGA34 011010XXXXX SA111 to SA114

SGA35 0 1 1 0 1 1 X X X X X SA115 to SA118

SGA36 0 1 1 1 0 0 X X X X X SA119 to SA122

SGA37 0 1 1 1 0 1 X X X X X SA123 to SA126

SGA38 0 1 1 1 1 0 X X X X X SA127 to SA130

SGA39 0 1 1 1 1 1 X X X X X SA131 to SA134

SGA40 1 0 0 0 0 0 X X X X X SA135 to SA138

SGA41 1 0 0 0 0 1 X X X X X SA139 to SA142

SGA42 1 0 0 0 1 0 X X X X X SA143 to SA146

SGA43 1 0 0 0 1 1 X X X X X SA147 to SA150

SGA44 1 0 0 1 0 0 X X X X X SA151 to SA154

SGA45 1 0 0 1 0 1 X X X X X SA155 to SA158

SGA46 1 0 0 1 1 0 X X X X X SA159 to SA162

SGA47 1 0 0 1 1 1 X X X X X SA163 to SA166

SGA48 1 0 1 0 0 0 X X X X X SA167 to SA170

SGA49 1 0 1 0 0 1 X X X X X SA171 to SA174

SGA50 1 0 1 0 1 0 X X X X X SA175 to SA178

SGA51 1 0 1 0 1 1 X X X X X SA179 to SA182

SGA52 1 0 1 1 0 0 X X X X X SA183 to SA186

SGA53 1 0 1 1 0 1 X X X X X SA187 to SA190

SGA54 1 0 1 1 1 0 X X X X X SA191 to SA194

SGA55 1 0 1 1 1 1 X X X X X SA195 to SA198

SGA56 1 1 0 0 0 0 X X X X X SA199 to SA202

SGA57 1 1 0 0 0 1 X X X X X SA203 to SA206

SGA58 1 1 0 0 1 0 X X X X X SA207 to SA210

SGA59 1 1 0 0 1 1 X X X X X SA211 to SA214

SGA60 1 1 0 1 0 0 X X X X X SA215 to SA218

SGA61 1 1 0 1 0 1 X X X X X SA219 to SA222

SGA62 1 1 0 1 1 0 X X X X X SA223 to SA226

SGA63 1 1 0 1 1 1 X X X X X SA227 to SA230

SGA64 1 1 1 0 0 0 X X X X X SA231 to SA234

SGA65 1 1 1 0 0 1 X X X X X SA235 to SA238

Table 8. Sector Block Addresses for Protection/Unprot ect ion (Continued )

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

April 26, 2002 Am29PDL128G 23

ADVANCE INFORMATION

SECTOR PROTECTION

The Am29PD L128G fea tures sev eral levels of sector

protection, which can disable both the program and

erase operation s in certain sector s or sector groups:

Persistent Sector Protection

A comman d sector protection metho d that replaces

the old 12 V controlled protection method.

Password Sector Protection

A highly sophisticated protection method that requires

a passw ord before chan ges to cer tain sect ors or sec-

tor groups are permitted

WP# Hardware Protection

A write protect pin that c an prev ent prog ram or erase

operations in sectors 0, 1, 268, and 269.

All pa rts default to o perate in the Per sist ent Sector

Protection mode. The customer must then choose if

the Pers istent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that defin e which sect or protectio n

method will be used. If the customer decides to con-

tinue using the Persistent Sector Protection method,

they must set the Persistent Sector Protection

Mode Locking Bit. This will per manently set the part

to operate only using Persistent Sector Protection. If

the custom er decides to use the passwor d me thod,

they must set the Password Mode Locki ng Bit. Thi s

will permanently set the part to operate only using

password sector protection.

It is important to remember that setting either the Per-

sistent Se ctor Protectio n Mode Loc king Bit or the

Password Mode Locking Bit permanently selects

the protection mode . It is no t p ossible t o sw itch be-

tween the two methods once a locking bit has been

set. It i s im portan t that one mod e is e xplic itly s e-

lected when the device is first programmed, rather

than relyin g on the defaul t mode alone. T his is so

that it is not pos sible for a system program or virus to

later set the Password Mode Locking Bit, which would

caus e an unexpecte d shift from the def ault Persiste nt

Sec tor Prot ection Mode into the Passwo rd Protect ion

Mode.

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

The dev ice is ship ped with all sectors unprotec ted.

AMD offers the option o f programming and prot ecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Serv ic e. Co nta ct an

AMD representative for details.

SGA66 1 1 1 0 1 0 X X X X X SA239 to SA242

SGA67 1 1 1 0 1 1 X X X X X SA243 to SA246

SGA68 1 1 1 1 0 0 X X X X X SA247 to SA250

SGA69 1 1 1 1 0 1 X X X X X SA251 to SA254

SGA70 1 1 1 1 1 0 X X X X X SA255 to SA258

SGA71 111111

X X X SA259 to SA26 101

SGA72 11111111000 SA262

SGA73 11111111001 SA263

SGA74 11111111010 SA264

SGA75 11111111011 SA265

SGA76 11111111100 SA266

SGA77 11111111101 SA267

SGA78 11111111110 SA268

SGA79 11111111111 SA269

Table 8. Sector Block Addresses for Protection/Unprot ect ion (Continued )

Sector

Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Sectors

24 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

It is possible to determine whether a sector is pro-

tected or unprotected. See Autoselect Mode for de-

tails.

Persistent Sector Protection

The Persistent Sector Protection method rep laces the

old 12 V controlled protection method while at the

same time enha ncing flex ibility by provid ing three dif-

ferent sector protection states:

■Persistently Locked—A sector is protected and

cannot be changed.

■Dynamicall y Locked—The sector is prot ected and

can be changed by a simple command

■Unlocked—The sector is unprotected and can be

changed by a simple command

In order to achieve these states, three types of “bits”

are going to be used:

Persisten t Protectio n Bit (PP B)

A s ingle Per sist ent (n on-v olat ile) Prot ecti on B it i s as -

signed to a maximum four sectors (see the sector ad-

dress tables for specific sector protection groupings).

All 8 Kbyte boot-block sectors have individual sector

Persistent Protection Bits (PPBs) for greater flexibility.

Each PPB is indi vidual ly modifi able thr ough the PPB

Write Command.

Note: If a PPB requires erasure, all of the sector PPBs

must first be preprogrammed prior to PP B erasing. All

PPBs era se in parallel, un like programming w here in-

dividual PPBs are programmable. It is the responsibil-

ity of the user to perform the preprogramming

operation. Otherwise, an a lready er ased se ctor PPBs

has the potential of being over-eras ed. There is n o

hardware mechanism to prevent sector PPBs

over-erasure.

Persistent Protection Bit Lock (PPB Lock)

A global volatile bit. When set to “1”, the PPBs cannot

be changed. When cleared (“0”), the PPBs are

changeable. There is only one PPB Lock bit per de-

vice. The PPB Lock is cleared after power-up or hard-

ware reset. There is no command s equence to unlock

the PPB Lock.

Dynamic Protection Bit (DPB)

A volatile protec tion bit is ass igned for each sector.

After po wer- up or ha rd ware re set, th e contents of al l

DPBs is “0”. Each DPB is individually modifiable

through the DPB Write Command.

When the parts are first shipped, the PPBs are

cleared, the DPBs are cleared, and PPB Lock is de-

faulted to power up in the cleared state – meaning the

PPBs are changeable.

Wh en the d evic e is fir st powe red o n the DPB s pow er

up cleared (sectors not protected). The Protection

Stat e for eac h sect or is det ermined by the lo gical OR

of the PPB and the DPB related to that sector. For the

sectors that have the PPBs cleared, the DPBs control

whet her or not the s ector is prot ected or unp rotected.

By issuing the DPB Write command sequences, the

DPB s w ill be s et or clear ed, t hus p lacing each sect or

in the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked stat es. They

are called dynamic states because it is very easy to

sw itch b ack and fo rth b etw een t he prote cte d an d un-

protec ted conditions. Th is a llows software to eas ily

pro tect sec tors agains t in advert ent chang es yet does

not prevent the easy removal of protection when

changes are needed. The DPBs maybe set or cleared

as often as needed.

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycl es becau se they are Non-Volatile.

In dividu al PPB s ar e se t with a co mmand bu t mus t all

be cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

The PPB Lock bit adds an additional level of protec-

tion. Once all PPBs are programm ed to the desired

setting s, the PPB Loc k may be set to “1”. Setting the

PP B Lock dis ables al l program a nd eras e com mands

to the Non-Volatile PPBs. In effect, the PPB Lock Bit

locks the PPBs into their current state . The only way to

clea r the PPB Lo ck is to g o through a power cy cle .

System boot code can determine i f any c hanges t o the

PPB ar e needed e. g. to allo w new system code to be

down load ed. If no chang es ar e neede d the n the boo t

code can set the PPB Lock to disable any further

changes to the PBB s during system operation.

The WP# protects the top two and bottom two sectors

when at VIL. These sector s gener ally hold s yst em boot

code. The WP# pin can prevent any changes to the

boot code t hat could override the c hoices m ade while

setting up sector protection during system initializa-

tion.

It is possible to have sectors that have been persis-

te ntly loc ked, a nd se ctors that are le ft in th e dyn amic

stat e. T he se ctors in the dyna mic s tate are a ll unp ro-

tected. If there is a need to protect some of them, a

simple DPB Write comm and se quence is a ll that is

necessary. The DPB write command for the dynamic

sectors switch the DPBs to signify protected and un-

protected, respectively. If there is a need to change

the status of the persistently locked sectors, a few

more steps are require d. First, the PP B Lock bit mus t

be disabled by either putting the device through a

power-cycle, or hardware reset. The PPB s can then

be changed to reflect the de sired settings. Setting the

April 26, 2002 Am29PDL128G 25

ADVANCE INFORMATION

PPB lock bit once again will lock the PPBs, and the

device operates normal ly again.

Note: to achi eve the best protection, it’s recommended

to execu te the P PB lock bit set com mand early in th e

boot code, and prot ect the boot code by holding WP #

= VIL.

Table 9. Sector Protection Schemes

Table 9 contains all possible combinati ons of the DPB,

PPB, and PPB lock relating to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the P PB is cleared, the sector can be dy nami-

cally locked or unlocked. The DPB then controls

whether or not the sector is protected or unprotected.

If the user attempts to program or erase a protected

sector, the dev ice ignor es the command and returns to

read mode. A program c ommand to a pro tected sector

enables status polling for approximately 1 µs before

the device retur ns to read mode wit hout having mod i-

fied the contents of the protected sector. An erase

command to a protected sector enables status polling

for approx imately 50 µs after which the dev ic e returns

to read mode without having erased the protec ted sec-

tor.

The programming of the DPB, PPB, and P PB lock for

a given sector can be verified by writing a

DPB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode

Locking Bit

Like the password mode locking bit, a Per sistent Sec-

tor P r otect ion m ode locking bit ex is ts to guarantee t hat

the device remain in softw are sector protection. Onc e

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

Password Protection Mode

The Password Sector Protection Mode method allows

an ev en higher level of sec urity than th e Persistent

Sector P rotection Mode . There a re two main d iffer-

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

■When the device is first powered on, or comes out

of a reset cycle, the PPB Lock bit set to the locked

state, rather than cleared to the unlocked state.

■The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

The Passwor d Sect or Protection met hod is o therwise

identical to the Persistent Sector Protect ion method.

A 64-bit password is the only additional tool utilized in

this method.

The password is stored in the first eight bytes of the

SecSi Sector. Once the Password Mode Lock ing Bit is

set, the passwor d is permanent ly s et wit h no mea ns to

read, program, or erase it. The password is used to

clear the P PB Lock bit. The Pass word Unlock com-

man d mus t be writt en to t he flas h, alo ng wit h a pas s-

wor d. The f lash devi ce in terna lly c omp ares the g iven

pass word with the p re-prog rammed pas sword. If they

match, the PPB Lock bit is c leared, and the PPBs can

be altered. If they do not match, the flash device does

not hing. T here is a b uilt-in 2 µs de lay for each “pass-

word check.” This delay is intended to thwart any ef-

forts to run a program that tries all possible

combinations in order to crack the password.

Because the passwor d oc c upies the first eight bytes of

the SecSi Sector, the password must be program med

before either the password protection mode is se-

lected or the SecSi Sector protection bit is pro-

grammed (to use both the SecSi S ector and Password

Pr otectio n at th e same tim e). S ee U tilizing Passwor d

and SecSi Sector Concurrently for more info rmat ion.

Password and Password Mode Locking

Bit

In order to select the Password sector protection

scheme, the cust omer must first pr ogram the pas s-

word. AM D recommen ds that the password be some-

how correlated to the unique Electronic Ser ial Number

(E SN) of the pa rticul ar f lash devic e. Eac h ESN is di f-

ferent for every flash device; therefore each password

sh ould be differ ent fo r e very fla sh dev ice. While pr o-

gra mming in the pas swor d re gion, the custom er may

perform Password Verify operations.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectiv es:

DPB PPB PPB

Lock Sector State

000

Unprotected—PPB and DPB are

changeable

001

010

Protected—PPB and DPB are

changeable

100

110

011

Protected—PPB not

changeable, DPB is changeable

101

111

26 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

1. It permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

2. It also disables all further commands to the pass-

word region. All program, and read operations are

ignored.

Both of these objectives are important, and if not care-

fully con sid ere d, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correc t when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no m eans to verify what the

password is afterwards. If the password is lost after

setting th e Passw ord Mo de Lock ing Bit, t here wi ll be

no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents

readi ng the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not era sable. On ce Passwo rd Mode Loc king Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from program ming, guaranteeing

that no changes to the protection scheme ar e allowed.

64-bit Password

The 64-bit Password is located in its own memory

space and is accessib le throug h the use of the Pass -

word Prog ram an d Veri fy co mma nds ( see “Password

Verify C omma nd”). The password func tion works in

conjunction with the Password Mode Locking Bit,

which when set, prevents the Password Verify com-

mand from reading the contents of the password on

the pins of the device.

Write Protect (WP#)

The W rite Protect feature provides a hardware method

of protect ing sectors 0 , 1, 268, and 269 witho ut using

VID. This function is provided by the WP# pin and over -

rides the previously discussed Sector Protection/Un-

protec tion method.

If the system asserts VIL on t he WP# pin, the device

disab les prog ram and er ase f unctions in sectors 0 , 1,

268, and 269 independent of whether it was previously

protected or unprotected using High Voltage Sector

Protection.

If the system asserts VIH on the WP# pin, the device

reverts to wh ether s ec tors 0, 1, 268, and 269 wer e last

set to be protected or unprotected. That is, sector pro-

tection or unprotection for these sectors depends on

whether they were previously protect ed or unprotected

using High Voltage Sector Protection.

Per s is tent P r otection Bit Loc k

Th e Pe rsiste nt P rote ction Bit (PPB ) L ock is a v olat ile

bit that reflects the stat e of the Password Mode Loc k-

ing Bit after pow er-up reset. If the Password Mo de

Lock Bit is also set after a hardware reset (RES ET#

asserted) or a power-up reset. The ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1” when the

Password Mode Lock Bit is not set.

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hard ware reset. The PP B

Lock Bit is set by issuing the PPB Lock Bit Set com-

ma nd. O nce s et the only mean s for cl earing the PPB

Lock Bit is by issuing a hardware or power-up reset.

Th e Passw ord Un lock com mand is igno red in Persis-

tent Protection Mode.

High Voltage Sector Pr otection

Sector protection and unprotection may also be imple-

mented using programming equipment. The proce-

dure requires high voltage (VID) to be placed on the

RESET# pin. Refer to Figure 1 for d etails on this pr o-

cedure. Note that for sector unprotect, all unprotected

sec tors mus t firs t be prote cted prior to the first sect or

write cycle.

April 26, 2002 Am29PDL128G 27

ADVANCE INFORMATION

Figure 1. In-System Sector Protection/

Sector Unprotection Algorithms

Sector Protect:

Write 60h to sector

address with

A6-A0 =

0111010

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6-A0 =

0111010

Read from

sector address

with A6-A0 =

0111010

START

PLSCNT = 1

RESET# = V

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove V

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6-A0 =

1111010

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6-A0 =

1111010

Read from

sector address

with A6-A0 =

1111010

START

PLSCNT = 1

RESET# = V

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove V

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

28 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Temporary Sector Unpr otect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by s etting the RE-

SET# pin to VID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

secto r addresse s. Once VID is remo ve d from the RE-

SET# pin, all the previously protected sectors are

protected again . Figure 2 sh ows the algorithm , and

Figure 23 shows the timing diagrams, for this feature.

Figure 2. Temporary Sector Unprotect Operation

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The SecS i (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words (64 double

words) in length, and us es a S ecSi Sector Indicator B it

(DQ7) to indicate whether or not the SecSi Sector is

locke d when shipp ed from the factor y. This bit is per-

manently s et at the factory and cannot be changed,

which prevents cloning of a factory locked part. This

ensures the security of the ESN once the product is

shipped to the field.

AMD offers t he device w ith the S ecSi Sector either

factory locked or customer lockable. The fac-

tory-locked v ersion is always protec ted when shipped

from the factory, and has the SecSi Sector Indicator

Bit permanently set to a “1.” The customer-lockable

version is shipp ed with the SecS i Sector unprotected,

allowing customers to utilize the that sector in any

manner they choose. The customer-lockable version

has the SecSi Sector Indica tor Bit permanentl y set to a

“0.” Thus, the SecSi Sector Indicator Bit prevents cus-

tomer-lockable dev ic es from being us ed to replace de-

vice s t hat are factor y loc ked .

The system accesses the SecSi Sector through a

command sequence (see Enter SecSi Sector/Exit

Sec Si Sector Com mand Seq uence). After the system

has written the Enter SecSi Sector command se-

quence, it may read the S ecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the normal address space.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory lo cked device, t he SecSi S ector is pro-

tected whe n the de vice is ship ped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a sec ure ESN. The SecSi Sector is located at ad-

dresses 000000h–00007Fh in word mode (or

000000h–0 0003Fh in do uble word mo de). The device

is av ailable prepro gr ammed with o ne of t he follo wing:

■A random, secure ESN only

■Customer code through the ExpressFlash service

■Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt to have their code programmed by

AMD throug h the AMD E xpressFlas h service. AMD

programs the cus tomer’s cod e, with or without the ran-

dom ESN. Th e de vices ar e then s hipped f rom AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details o n using

AMD’s Express Flash servi ce.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At t he Factory

If the security feature is not required, the SecSi Sector

can be treated a s an additiona l Flash mem ory space .

The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

START

Perfor m Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected (If WP # = VIL, sectors

0, 1, 268, and 269 will remain protected).

2. All previously p rotected sectors are protected once

again.

April 26, 2002 Am29PDL128G 29

ADVANCE INFORMATION

The SecS i Sector area ca n be protected u sing one of

the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 1, ex-

cept that RESET# may be at either VIH or VID. This

allows in-system protection of the SecSi Sector Re-

gion wi thout raisi ng any device pi n to a high voltage.

Note t hat this method i s only appl icable to t he SecSi

Sector.

■Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

Secto r Protecti on section.

Once the Sec Si S ector is lock ed and v erified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing t he

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unloc king the Se cSi Se ctor are a and none o f the bits

in the SecSi Sector memory space can be modified in

any way.

SecSi S ector Protection Bit

The SecSi Sector P rotection Bit prev ents pro gram-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Utilizing Password and SecSi Sector Concurrently

The password must be stored in the first eight bytes of

the SecSi Sector. Once the device is permanently

locked into the Password Protection Mode, the erase,

program, and read operation no longer w ork on those

eight bytes of password in the SecSi Sector. O nce the

SecSi S ector protection bit is pr ogr ammed, no location

in the SecSi Sector may be programmed. To use both

Password Protection and the SecSi Sector concur-

rently, the us er must alwa ys prog ram the password

into the first eight bytes of the SecSi Sector before ei-

ther th e Passwor d Prote ction Mod e is se lected or the

SecSi Sector protection bit is programmed.

Method 1

1. Enter the SecSi Sector by issuing the SecSi Sect or

Entr y command.

2. Program the 64-bit password by issuing the Pass-

word Program and Password Verify commands

3. Lock t he password by issuing t he Password Protec -

tion Mode Locking Bit Program command.

4. Program the SecSi Sector, excluding bytes 0–7.

5. Lock the S ecSi Sec tor by issuing the SecSi Sector

Prot ection Bit Program command.

6. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 2.

Method 2

1. Enter the SecSi Sector by issuing the SecSi Sector

Entry command.

2. Program the entire SecSi Sector, including the first

eight bytes contain the 64-bit password.

3. Lock the password by i ssuing the Password Pr otec-

tion Mode Locking Bit Program command.

4. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

5. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 3.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes. In addition, the following

hardware data protection m easures prevent accident al

erasure or programming, which might otherwise be

caused by spur ious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the devi ce does not ac-

cept any wr ite cycles. This protects data during VCC

power-up and power-down. The command register

and all internal progr am/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until VCC is greater than VLKO. The

syst em must pr ovide the p roper s ignals to the co ntrol

pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch” Pr otect io n

Nois e pu lses of l ess t han 5 ns ( typic al) o n OE# , CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initia te a wr ite cy cle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The intern al state machine is aut omati-

cally reset to the read mode on power-up.

30 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID- independent, and forwar d- an d

backwar d-compa tible for the spec ified flash de vice

families . Flas h vendo rs can s tand ardize t heir existin g

interfaces for long-term compatibility.

This device enters the CFI Query mode when the sys-

tem writes the CFI Qu ery comma nd, 98h , to addre ss

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CF I information at the a ddresses

given in Tables 10–13. To terminate reading C FI data,

the system must write the reset com mand. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

The system ca n also write the CF I query comm and

when the device is in the autoselect mode. The device

ent ers the CFI qu ery mode , and the syst em ca n read

CFI data at the addresses given in Tables 10–13. The

system must write the reset c ommand to return the de-

vice to the autoselect mode.

For further information, pleas e refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/prod-

ucts/n vd/overview/cfi.htm l. Alternatively, contac t an

AMD representative for copies of these documents.

Table 10. CFI Query Identificati on String

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h P rimary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Ad dress for Alternate OEM Extended Table (00h = none exists)

April 26, 2002 Am29PDL128G 31

ADVANCE INFORMATION

Table 11. System Interface String

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

1Bh 36h 0027h VCC M in. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no V PP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical timeout for Min. size buffer wr ite 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N time s typical

25h 4Ah 0004h Max. timeout per individual block erase 2N ti mes typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

32 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Table 12. Device Geometry Definition

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

27h 4Eh 0018h Device Size = 2N byte

28h

29h 50h

52h 0005h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of byte in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0003h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Eras e Block Region 1 Information

(refe r to the CFI s pecification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

00FDh

0000h

0001h

Eras e Block Region 2 Information

(refe r to the CFI s pecification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0007h

0000h

0020h

0000h

Eras e Block Region 3 Information

(refe r to the CFI s pecification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Eras e Block Region 4 Information

(refe r to the CFI s pecification or CFI publication 100)

April 26, 2002 Am29PDL128G 33

ADVANCE INFORMATION

Table 13. Primary Vendor-Specif ic Extended Query

Addresses

(Double Word

Mode) Addresses

(Word Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Ma jor version number, ASCII (reflects modifications to the silicon)

44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 8Ch 0002h Erase Suspend

0 = Not Support ed, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0001h Sector P rotect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0007h Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F 016 mode, 03 = 29F400, 04 = 29LV800

mode

4Ah 94h 00E7h Simul taneous Operation

00 = Not Supported, X = Number o f Sector s exc luding Bank 1

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0002h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 00B5h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 0005h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 0001h Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = Uniform, 8 x 8 Kbit Top and Bottom, 02h =

Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom

50h A0h 0000h Program Suspend

0 = Not supported, 1 = Supported

57h AEh 0004h Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

58h B0h *0027h Bank 1 Region Information

X = Number of Sectors in Bank 1

59h B2h *0060h Bank 2 Region Information

X = Number of Sectors in Bank 2

5Ah B4h *0060h Bank 3 Region Information

X = Number of Sectors in Bank 3

5Bh B6h 0027h Bank 4 Region Information

X = Number of Sectors in Bank 4

34 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences int o the command register initi ates device op-
erations. Tables 14–17 define the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data. 
All a ddre sses  are l atc hed o n th e falli ng  edge  of  WE#
or CE#, whichever  happens later. All data is latched  on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after  device  pow er-up.  No co mma nds are  requir ed t o
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Em bedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read
data from any no n-erase-suspended  sector wit hin the
same bank. The system can read array data us ing the
stand ard  rea d ti ming , e xcept  tha t if  it r ead s at  an  ad-
dress within erase-suspended sectors, the device out-
puts status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with  the same excep-
tion. See the Erase Suspend/Erase Resume Com-
mands section for more info rmat ion.
The system must issue the reset command to return a
bank to the read (or erase-suspend- read) mode if DQ5
goes high during an active program or erase opera-
tion, o r if the  bank  is in the  autosele ct mod e. S ee the
next section, Reset Command, for more inform ation .
See also Requirements for Reading A rray Data in the
Device Bus Operations section for more information.
The Read-Only Operations  table provi des  the read pa-
rameters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence c ycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until th e operation is  complete.
The reset command may be written between the
seque nce cycles  in a pro gram com ma nd seque nce
before programming begins. This resets the bank to
which the s ystem was writing t o the read mode. If the
progra m command sequen ce is writte n to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, how-
ever, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles  in an autoselect command sequence.
Once in the autoselect mode, the reset command
mus t be w ritten t o return t o the  read m ode.  If a b ank
entered the autoselect mode while in the Erase Sus-
pend mo de, w riting the res et com mand  returns  that
bank to the erase-suspend-r ead mode.
If DQ5 goes high during a program  or  er ase op eration,
writing t he reset comman d retur ns  the banks to the
read  mode  (or eras e-sus pend-read  mode  if that  bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequenc e allows the hos t
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within  a bank that is either in the read or
eras e-sus pend-r ead m ode.  The au tose lect c ommand
ma y  not be writt en while  the devic e is  active ly pro-
gramming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the au-
to select  comma nd. Th e b ank the n ent ers t he autos e-
lect mode. The system may read any number of
autoselect codes without reinitiating the com mand se-
quence.
Tables  14 and 16 sh ow the address and data require-
ments. To determine sector protection information, the
system m ust wri te to  the a ppropria te bank addr ess
(B A) and s ector  addres s (SA ). Table 5 shows t he ad -
dress range and bank number associated with each
sector. 
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previou sl y in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector regi on pr ovi des  a secured dat a ar ea
containing a random, eight word/four double word
electroni c serial num ber (ES N) . The system  can ac-
ces s the Se cSi Sector  region b y issuing the  thre e-cy-
cle Enter SecSi Sector command sequence. The
device continues to access the SecSi Sector region

April 26,  2002 Am29PDL128G 35
ADVANCE INFORMATION 
until the system  issues t he four-cycle  Exit SecSi Sec -
tor command sequence. The Exit SecSi Sector com-
mand sequence returns the device to normal
operation. The SecSi Sector is not accessible when
the device is executing an Embedded Program or em-
bedded Erase algorithm. Tables  15 and 17 s how the
addres s and data requirements for both comm and se-
quence s. See al so “SecSi™ (S ecured S ilicon)  Sector
Flash Memory Region” for further information. 
Do uble Word/Wor d Program Command 
Sequence
The system may program the d evice by double word
or word, depending on the state of the WORD# pin.
Programming is a four-bus-cycle operation. The pro-
gram comm and se quence is initiated by writing two
unlock write cycles, followed by  the progr am set-up
command. The p rogram address  and data are written
next, which in  turn initiate t he Embedde d Progr am al-
gorithm. T he system is  not required to p rovide further
controls or timings. The dev ice automatic ally provides
internally generated program pulses and verifies the
prog ra mmed cell m argin. Tables 14 an d 16 sho w the
addres s and  data req uirem ents for  the pr ogram c om-
mand sequence.
When  the Em bedded P rogram  algorithm  is co mplete,
that bank then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of  the program operation by using
DQ7, DQ6, or RY/BY# . Refer to th e Write Operation
Status section for information on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignore d. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated o nce that bank has  returned to the rea d
mode, to ensure data integrity.
Prog rammin g is a llowed  in a ny sequ ence a nd  across
sector boundaries. A bi t can not b e prog ramme d
from  “0” back to a “1.” Attempting to do  so  may
cause t hat bank to set DQ5 = 1, or  c aus e the DQ7 and
DQ6 stat us bi ts to i ndic ate t he oper ation was success-
ful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a
“0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to  pro-
gram  data to a  bank faster tha n using the standa rd
program command sequence. The unlock bypass
command sequence is initiated by first writing  two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. That bank
the n enters  the unloc k bypa ss mode.  A two- cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
man d, A0h; the s econd cycl e contains the  program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock c ycles requ ired in the standar d program
command se quence, resulting in faster total program-
ming time. Tables 14 and 16 show the requirements
for the command sequence.
Dur ing  th e un lo ck by pas s m ode , o nly  the  Un loc k By -
pass Progr am and Un lock Bypass Reset  commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the  ACC pin, the  device auto matically enters th e Un-
lock Bypass mode.  The system may then write the
two-cycle Unlock Bypass program command se-
quen ce. The d evice uses  the hig her voltag e on the
ACC  pin to accelerate the operation. Note that the
ACC pin must not be at VHH any  operatio n other t han
acc elerated  progra mming,  or devi ce damage  may  re-
sult. In addition, the ACC pin must not be left floating
or unconnected; inconsistent behavior of the device
may result.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 16 for timing diagrams.

36 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
com man d se quen ce  is in iti ated b y w rit ing tw o  unlo ck
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip  erase
command, which in turn invokes the Embedded Erase
algor ithm.  The d evic e doe s not require the system  to
preprogram pr ior  to erase . T he E mbedded E r as e algo-
rithm automatically  pr epr ogr ams and verifies the enti re
memory fo r an all zero  data pattern p rior to electrical
erase. The system is not required to provide any con-
trols  or timings during t hese operat ions . Tables 14 and
16 show the address and data requirements for the
chip erase command sequence.
When the Embedded Erase algorithm is complete,
that bank  returns to the read mode and addresses are
no longer latched. The system can det ermine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Write Operation Status sec-
tion for info rmation on these status bits.
Any commands written during t he chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs,  the chip  erase command  sequ ence  sho uld be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Fi gure 4  illus trates  the  algori thm f or the  eras e ope ra-
tion. Refer to the Erase and Program Operations ta-
bles in the AC Ch aracteristics section for para meters,
and Figure 18 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus  cycle operation. The sector
erase comm and sequence is initiated by writing two
unlock cycles, followed by a set-up command. T wo ad-
ditional unlock cycles are written, and are then fol-
lowe d by t he ad dres s of the  secto r to  be er ased,  and
the sector erase command. Tables 14 and 16 s how
the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically  programs an d verifies the en tire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations. 
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector era se buffer
may be done in any sequence, and the number of sec-
tors m ay be from one sector to all sectors. The time
between thes e additional cycles must be less than 80
µs, otherwis e erasure ma y b egin. Any sector era se
address and command following the exceeded
time-out may or may not be accepted. It is recom-
mended that processor interrupts be disabled during
this  time t o ens ure  al l com mand s ar e acce pted . The
interrupts can be re-enabled after the last Sector
Erase command is written. Any  command other than
Sector Erase or Erase Suspend during the
time-out period resets that bank t o the read mod e.
The system mus t rewrite the command sequence and
any additional addresses and commands.
The  system c an monitor  DQ3 to  determine  if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Tim er . ). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading arr ay data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from  the non-erasing bank. The system can  de-
termine the status of the erase operation by reading
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded 
Program
algorithm
 in progress
Note: See Tables 14 and 16 for program  command 
sequence.

April 26,  2002 Am29PDL128G 37
ADVANCE INFORMATION 
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Refer to the Wri te Opera tion S tatus  section for infor-
mation on these status bits.
Once the sec tor er ase operat ion has begu n, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation.  If
that occurs, the sector erase command sequence
should  be reinitiated once that bank  has returned t o
reading array data, to ensure data integrity.
Figu re 4 i llustra tes the  al gorithm  fo r the e rase  oper a-
tion. R efer to the Erase and Program Operations ta-
bles in the AC Charact eristics section for parameters,
and Figure 18 section for timing diagrams.
Erase Suspend/Erase Resume 
Commands
The Erase Suspend command, B0h, allows the sys-
tem to int errupt a sector erase operat ion and then read
data from, or program  data to, any sector not selected
for er asur e. The ba nk  addr es s  is  required  when writing
this comman d. This c ommand is v alid only d uring the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written dur -
ing the chip erase operation or Embedded Program
algorithm. 
Whe n the E ras e S uspen d co mmand  is w ritte n dur ing
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, whe n the Eras e Suspend c ommand  is  written
during the sector erase time-out, the device immedi-
ately terminates the t ime-out period and suspends the
erase opera ti on. Addresses  are  “don’t-cares” when
writing the Era se suspend command.
After th e erase operation has  been suspended,  the
bank  en ters th e erase-s uspen d-read m ode. Th e sys-
tem can read data from or program data to any sector
not selected for erasure. (The device “erase sus-
pends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if  a sector is actively erasing or is erase-suspended.
Refer to the Wri te Opera tion S tatus  section for infor-
mation on these status bits.
After an  eras e-suspe nde d prog ram  operatio n is c om-
plete, the bank returns to the erase-suspend-read
mode.  The system can determine the status of the
progr am ope ration u sing the  DQ7  or DQ6  status  bits,
just as in the standar d Double Word/Word  Program
operation. Refer to the Write Operation Status secti on
for more informa t ion.
In the erase-suspend-read m ode, the system can also
issu e the autoselec t comm and seque nce. The  device
allows reading autoselect codes ev en at addresses
within erasing  sectors, since the code s are not stored
in the mem ory array. When the dev ice exits the au-
toselect mode, the device reverts to the  Erase Sus-
pen d mode, and is  rea dy fo r anot her valid op erati on.
Refer to the Autoselect Mode and Autoselect Com-
mand Sequence sections for details. 
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-sus-
pend ed  bank  is req uired  wh en wr iting t his  comma nd.
Further writes of the Resume command are ignored.
Another Erase Suspend com mand can be written after
the chip has resumed erasing. 
Figure 4. Erase Operation
Password Program Command
The Password Program Command permits program-
ming the pas sword that is used as part of the hard-
ware protection scheme. The actual password is
64-bits long. Depending upon the state of the WORD#
pin, multiple Password Program  Commands are re-
quired. For a x16 bit data bus, 4 Password Program
commands are required to program the password. For
START
Write Erase 
Command Sequence
(Notes 1, 2)
Data Poll to Erasing 
Bank from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
Notes:
1. See Tables  14 and 16 for erase command sequ ence.
2. See th e section on DQ3 for information on the sector 
erase timer.

38 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

a x32 bit data bus, 2 Password Program commands

are required. The use r must enter the unlock cycle,

password program command (38h) and the program

address/data for each portion of the password when

programming. There is no special addressing order re-

quired for prog ramming the passwor d. Als o, when the

pass wor d is und erg oing prog ram min g, Sim ultan eo us

Operation i s disabled. Read operati ons to any memory

location will return the programming status. Onc e pro-

gramming is complete, the user must issue a

Read/Reset command to return the device to normal

operatio n. On ce th e Pass word is writt en and verifie d,

the Password Mode Locking Bit must be set in order to

prevent verification. The Password Program Com-

mand is onl y ca pable o f progr amm ing “0”s. Program-

ming a “1” after a cell is programmed as a “0” result s in

a time-out by the Embedded Program Algorithm™

with the cell remaining as a “0”. The password is all F’s

when shipped from the factor y. A ll 64-b it passw ord

combinat ions are valid as a password.

Password Program ming is permitted if the S ecSi sec-

tor is enabled.

Password Verify Com ma nd

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user at tem pts to verify the Pa ssword, the devic e wil l

always drive all F’s onto the DQ data bus.

The Password Verify command is permitted if the

SecSi sector is enabled. Also, the device will not oper-

ate in Simultaneous Operation when the Password

Verify command is executed. Only the password is re-

turned regardless of the bank addres s. The lower two

address bits (A0:A-1) are v alid during the P as sword

Verify. Writing the Read/Reset command returns the

device back to normal operation.

Password Protection Mode Locking Bit

Program Command

The Pa sswo rd Pro tec tion Mo de Lo cki ng B it P rog ram

Command programs t he Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the Password. Onc e programmed, t he Password

Pro tection Mo de Loc king Bit c anno t b e era sed ! If t he

Password Protection Mode Locking Bit is verified as

program without margin, the Password Protection

Mode Locking Bit Program command can be executed

to improve the program margin. Once the Password

Protection Mode L ocking Bit is program med, t he Per-

sistent Sector Protection Locking B it program circ uitry

is dis abled, thereby forcing the device to r emain in the

Password Protection mode. Exiting the Mode Locking

Bit Prog ram com mand is acc omplished by w riting the

Read/Reset command.

The Password Protection Mode Locking Bit Program

command is permitted if the SecSi sector is enabled.

Persistent Sector Protection Mode

Locking Bit Program Command

The Persistent Sector Protection Mode Locking Bit

Program Com ma nd programs the Persistent Sector

Protection Mode Locking Bi t, which prevents the Pass-

word M ode Locking B it from ever being prog rammed.

If the Persistent Sector Protection M ode Locking Bit is

verified as programmed without mar gin, the Persistent

Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Per sistent S ector Protect ion mo de of operatio n, on ce

this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by

writing the Read/Reset command.

The Persistent Sector Protection Mode Locking Bit

Pr og ra m co m ma nd i s p er mi tte d i f th e S e cSi se cto r is

enabled.

SecSi Sector Protection Bit Program

Command

The SecSi Sector Protection Bit Program Command

pro gram s the Sec Si Sec tor P rotec tion Bit, wh ich pr e-

vents the SecSi sector mem ory from being cleared. I f

the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Bit Program Command should be reissued to improve

program marg in. Exiting the VCC-level SecSi Sector

Protection Bit Program Command is acc omplished by

writing the Read/Reset command.

The SecSi Sector Protection Bit Program c ommand is

permitted if the S ecSi sector is enabled.

PPB Loc k Bi t Set Comman d

The PPB Lock Bit Set command is used to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command wa s successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the device is taken through a power-on clear or

the Password Unlock command is executed. Upon

setting the PPB Lock Bit, the PPBs are latched into the

DPBs. If the Passwor d Mode Locking Bit is s et, the

PPB Lock Bit status is reflected as set, even after a

power-on reset cycle. In the Persistent Sector Protec-

tion mode, exiting the PPB Lock Bit Set comma nd is

accomplished by writing the Read/Reset command.

The PPB Lock Bit Set command is permitted if the

SecSi sector is enabled.

April 26, 2002 Am29PDL128G 39

ADVANCE INFORMATION

DPB Wr ite Command

The DPB Wr ite command is used to set or clear a DPB

for a given sector. The high order address bits

(A21–A11) are issued at the same time as the code

01h or 0 0 h on DQ 7-D Q0. All ot her DQ d at a bu s pi ns

are ignored during the data write cycle. The DPBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DPBs are cleared at

power-up or hardware reset.Exiting the DPB Write

command is acc omplished by wr iting the Read/ Reset

command.

The DPB Write command is permitted if the SecSi

sector is enabled.

Passw or d Unlo ck Comm an d

The Password Unlock comma nd is used to cle ar the

PPB Lock Bit so that the PP Bs can be u nlocke d for

modific ation, thereby al lowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlo cking func tion to occur.

This com mand cann ot be is sued an y faster than 2 µs

at a time to prevent a hacker from running through the

all 64-b it combinations in an attempt to correctly match

a password. If the command is issued before the 2 µs

execution window for each portion of the unlock, the

command will be ignored.

The Password Unlock function is accomplished by

writing P assword U nlock co mmand an d data to the

device to p erfo rm the cle ari ng of the PPB L ock Bit.

Th e pa ss wor d is 64 bi ts lon g, so the u ser m us t writ e

the Password Unlock command 2 times for a x32 bit

data bus and 4 times for a x16 data bus.

Once the Passwor d Unlock com mand is ente re d, th e

RY/BY# pin goes LOW indic ating that the device is

busy. Ap proxim ate ly 2 µs is r equir ed f or e ach portio n

of the unlock. Once the first portion of the password

unlock completes (RY/BY# is not driven and DQ6

does not toggle when read), the Password Unlock

command is issued again, only this time with the next

part of the password. I f WORD# = 1, the sec ond P as s -

word Unlock command is the final command before

the PPB Lock Bit is cleared (assuming a valid pass-

word). If WORD # = 0, this is the fourth Passwo rd Un-

lock command. In x16 mode, four Password Unlock

commands are required to successfully clear the PPB

Lock Bit. As with the first Password Unlock com mand,

the RY/BY# s ignal goes LOW a nd reading the devic e

results in the DQ6 pin toggling on successive read op-

erations until complete. It is the responsibility of the

microprocessor to keep track of the number of Pass-

word U nlock commands (2 for x32 bus and 4 for x16

bus), the order, and when to read the PP B Lock bit to

confirm successful password unloc k

The Password Unlock command is permitted if the

SecSi sector is enabled.

PPB Program Command

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

gra mm ed (bu t is bulk erased wi th the other PPBs) .

The specific sector address (A21–A11 ) are writte n at

the same time a s the program c omma nd 60h with A6

= 0. If the PPB Lock Bit is set and the corresponding

PPB is set for the sector, the PPB Program command

will not execute and the command will time-out without

programming the PPB.

After programming a PPB, two additional cycles are

need ed to dete rmine wh ether the P PB h as bee n pro-

grammed with margin. If the PPB has been pro-

grammed without margin, the program command

should be reissued to improve the program margin.

The PP B Program com mand is per mitted if the SecSi

secto r is enabl ed. The PPB Program comman d does

not follow the Embedded Program algorithm.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

ing a sp ecific PPB . U nlike the PPB pro gram, no spe -

cific secto r address is required. However, when the

PPB erase command is written (60h) and A6 = 1, all

Sector PPBs are erased in parallel. If the PPB Lock Bit

is set the ALL PPB Erase command will not execute

and the command will time-out without erasing the

PPBs. After erasing the PPBs, two additional cycles

are needed to determine whether the PPB has been

erased wit h margi n. I f the PPBs has been er as ed with-

out margin, the erase command should be reissued to

improve the program margin.

It is the responsibility of the user to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the user attempts to erase a cleared PPB, over-era-

sure may o ccur making it difficult to program the PP B

at a later time. Also note that the total number of PP B

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

The All PPB Erase command is permitted if the SecSi

sector is enabled.

DPB Write Command

The DPB Write command is used for setting the DPB,

which is a volatile bit that is cleared at hardware reset.

There is one DPB per sector. If the PPB is set, the

sector is protected regardless of the v alue of the DPB.

If the PPB is cleared, setting the DPB to a 1 protects

the sec tor from programs or erases. Si nce this is a vol-

atile bit, rem oving power or resetting the device will

clear the DPBs. The bank addres s is latched when the

command is written.

40 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

The DPB Write command is permitted if the SecSi

sector is enabled.

PPB Lock Bit Set Command

The PPB Lock B it set command is used for setting the

PPB lock bit. During P assw ord Protection mode, only

the Password Unlock command can reset the PPB

Lock Bit t o 0. Otherwise, a power-up or hardware res et

reset s the PPB Lock Bit to 0.

PPB Lock Bit Status Command

The programming of the PPB Lock B it can be verified

by writi ng a PPB Lock Bit status veri fy command to the

device.

Sector Protection Status Command

The programming of either the PPB or DPB for a given

sector or sec tor group can be verified by writing a Sec-

tor Protection Status command to the device.

Note that there is no single command to independently

verify the programming of a DPB or PPB for a given

sector group.

April 26,  2002 Am29PDL128G 41
ADVANCE INFORMATION 
Command  Definitions Tables
Legend:
BA = Address of bank switching to autoselect mode,  bypass m ode, or 
erase operation. Determined by A21:A19, see Tables 4 and 5 for 
more detail.
PA = Program Address (A21:A0). Addresses latch on falling edge of 
WE# or CE# pulse, whichever happens later. 
PD = Program Data (DQ 15:DQ0) written to location PA. Data latches 
on rising edge of WE# or CE# pulse, whichever happens first. 
RA = Read Address (A21:A 0). 
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A21:A12) for verifying (in autoselect mode) or 
erasing.
WD = Write Data . S e e  “Configuration Register” definition for specific 
write data. Data latched on rising edge of WE#.
X = Don’t ca re
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecim al.
3. Shaded cells in table denote read cycles. All other cycles are 
write operations.
4. During unlock and command cycles,  when lower addres s bit s are 
555 or 2AAh as shown in table, address bits higher than A11 
(except where BA is required) and data bits higher than DQ7 are 
don’t ca r e s.
5. No unlock or command cycles required when bank is reading 
array data.
6. Reset command is required to return to reading array (or to 
erase-suspend-read mode if previously in Erase Suspend) when 
bank is in autoselect mode, or if DQ 5 goes high (wh ile bank is 
provi ding stat us information).
7. Cycle 4 of autoselect  command sequence is a r ead cycle. Syst em 
must provi de bank address  to obtain  manufacturer I D or devic e ID 
inform ation. See Autoselect Command Sequence section for 
more information.
8. Unlock Bypass command must be executed before writing 
command sequence. Unlock Bypass Reset command must be 
executed to return to normal operation.
9. Com man d is ignored during any embedded program , erase or 
suspended operation.
10. Valid read operati ons include asynchronous and burst read  mode 
operations.
11. Device ID must be read across cycles 4, 5, and 6. 00h in cycle 6 
indicates top boot block, 01h indicates bottom boot block.
12. System may read and program in non-erasing sectors, or enter 
autoselect mode, when in Program/Erase Suspend mode. 
Program/Erase Suspend command is valid only during a sector 
erase operation, and requires bank address.
13. Program/Erase Resume command valid  only during Erase 
Suspend mode, and requires bank address.
14. Command valid when device is ready to read array data or when 
device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during entire operation of command.
17. Command is  ignor ed duri ng any Em bedded Program, Embedded 
Erase, or Suspend operation.
18. Unlock Bypass Entry command is required prior to any Unlock 
Bypass operation. Unlock Bypass Reset command is required to 
return to reading array.
Table 14. Memory Array Command Definitions (x32 Mode)
Comm and (Notes)
Cycles
Bus Cycles (Notes 1–4)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (5) 1 RA RD
Reset (6) 1 XXX F0
Autoselect 
(Note 7) Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01
Device ID (11) 6 555 AA 2AA 55 555 90 (BA)X01 7E (BA)X0E 08 (BA)X0F 00/01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (12) 1 BA B0
Program/Erase Resume (13) 1 BA 30
CFI Query (14, 15) 1 55 98
Accelerated Program (16) 2 XX A0 PA PD
Configuration Register V eri fy (15) 3 555 AA 2AA 55 (BA)555 C6 (BA)XX RD
Configuration Register Write (17) 4 555 AA 2AA 55 555 D0 XX WD
Unlock Bypass Entry (18) 3 555 AA 2AA 55 555 20
Unlock Bypass Program (18) 2 XX A0 PA PD
Unlock Bypass Erase (18) 2 XX 80 XX 10
Unlock Bypass CFI (14, 18) 1 XX 98
Unlock Bypass Reset (18) 2 XX 90 XX 00

42 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Legend:
DPB = Dynamic Protection Bit
SSA = SecSi Sector Address (A6:A0) is (0011010) . 
PD[1:0] = Program  Data. Password written in 2 portions.
PPB = Persistent Protection Bit
PWA = Passw ord Address. A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read D ata DQ0 for protection indicator bit. 
RD(1) = Read Data DQ1 for PPB Lock bit status.
SA = Sector Address where security command applies. Address bits 
A21:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010)
EP = PPB Erase Address (A6:A0) is (1111010)
X = Don’t ca re
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protecti on Mode Locking Bit
1. See Table 1 for description of bus operations.
2. All values are in hexadecim al.
3. Shaded cells in table denote read cycles. All other cycles are 
write operations.
4. During unlock and command cycles,  when lower addres s bit s are 
555 or 2AAh as shown in table, address bits higher than A11 
(except where BA is required) and data bits higher than DQ7 are 
don’t ca r e s.
5. Reset command returns device to reading array.
6. Asynchronous read opera tion.
7. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate 
bit  has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 
6, entire command sequence must be issued and verified again.
8. Data is latched on rising edge of WE#.
9. Entire command sequence must be executed for each portion of 
password.
10. Comman d sequence returns FFh if PPMLB is set.
11. Password is written over four consecutive cycles at addresses 
0-3.
12. A 2 µs timeout is required between any two portions of password.
13. A 100 µs timeout is required between cycles 4 and 5.
14. A 1.2 ms timeout is required between cycles 4 and 5.
15. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been 
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command 
sequence must be issued and verif ied again. Before issuing 
erase command, all PPBs should be programmed to prevent 
PPBs overerasure.
16. DQ1 = 1 if PPB  locked, 0 if unlocked.
Table 15. Sector Protection Command Definitions (x32 Mode)
Comm and (Notes)
Cycles
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXX F0
SecSi Sector Entry 3 555 A A 2AA 55 (BA)555 88
SecSi Sector Exit 4 555 A A 2AA 55 (BA)555 90 XX 00
SecSi Protection Bit  Program (5,  6, 7) 6 555 AA 2AA 55 (BA)555 60 SSA 68 SSA 48 XX RD(0)
Password Program (5, 8, 9) 5 555 AA 2AA 55 555 38 XX[0-1] PD[0-1]
Password Verify (6, 9, 10) 4 555 A A 2AA 55 555 C8 PWA[0-1] PWD[0-1]
Password Unlock (8, 11, 12) 4 555 AA 2AA 55 555 28 PWA[0-1] P WD [0-1]
PPB Program  (5, 6, 7, 13) 6 555 A A 2AA 55 555 60 (SA)W P 68 ( SA)W P 48 (SA)WP RD(0)
All PPB Erase (5, 6, 14, 15) 6 555 AA 2AA 55 555 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0)
PPB Lock Bit Set 3 555 A A 2AA 55 555 78
PPB Lock Bit Status (6, 16) 4 555 A A 2AA 55 555 58 SA RD(1)
DPB Write (8) 4 555 A A 2AA 55 555 48 SA X1
DPB Erase (8) 4 555 A A 2AA 55 555 48 SA X0
DPB or PPB Status (6) 4 555 A A 2AA 55 555 58 SA RD(0)
PPMLB Program (5, 6, 7, 13) 6 555 AA 2AA 55 555 60 PL 68 PL 48 XX RD(0)
PPMLB Status (5) 6 555 AA 2AA 55 555 60 PL RD(0)
SPMLB Program (5, 6, 7, 13) 6 555 AA 2AA 55 555 60 SL 68 SL 48 XX RD(0)
SPMLB Status (5) 6 555 AA 2AA 55 555 60 SL RD(0)

April 26,  2002 Am29PDL128G 43
ADVANCE INFORMATION 
Legend:
BA = Address of bank switching to autoselect mode,  bypass m ode, or 
erase. Determined by A21:A19, see Tables 4 and 5 for more detail.
PA = Program Address (A21:A-1). Addresses latch on falling edge of 
WE# or CE# pulse, whichever happens later. 
PD = Program Data (DQ 15:DQ0) written to location PA. Data latches 
on rising edge of WE# or CE# pulse, whichever happens first. 
RA = Read Address (A21:A-1). 
RD = Read Data (DQ15:DQ0) from location RA.
SA = Sector Address (A21:A12) for verifying (in autoselect mode) or 
erasing.
WD = Write Data . S e e  “Configuration Register” definition for specific 
write data. Data latched on rising edge of WE#.
X = Don’t ca re
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecim al.
3. Shaded cells in table denote read cycles. All other cycles are 
write operations.
4. During unlock and command cycles,  when lower addres s bit s are 
555 or AAAh as shown in table, address bits higher than A11 
(except where BA is required) and data bits higher than DQ7 are 
don’t ca r e s.
5. No unlock or command cycles required when bank is reading 
array data.
6. Reset command is required to return to reading array (or to 
erase-suspend-read mode if previously in Erase Suspend) when 
a bank is in autoselect mode, or if DQ5 goes high (while bank is 
provi ding stat us information).
7. Cycle 4 of autoselect  command sequence is a r ead cycle. Syst em 
must provi de bank address  to obtain  manufacturer I D or devic e ID 
inform ation. See Autoselect Command Sequence section for 
more information.
8. Unlock Bypass command must be executed before writing 
command sequence. Unlock Bypass Reset command must be 
executed to return to normal operation.
9. Com man d is ignored during any embedded program , erase or 
suspended operation.
10. Valid read operati ons include asynchronous and burst read  mode 
operations.
11. Device ID must be read across cycles 4, 5, and 6. 00h in cycle 6 
indicates top boot block, 01h indicates bottom boot block.
12. System may read and program in non-erasing sectors, or enter 
autoselect mode, when in Program/Erase Suspend mode. 
Program/Erase Suspend command valid only during a sector 
erase operation, and requires bank address.
13. Program/Erase Resume command valid  only during Erase 
Suspend mode, and requires bank address.
14. Comman d is valid when device is ready to read array data or 
when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at VID during entire operation of this command.
17. Command ignored during any Embedded Program, Embedded 
Erase, or Suspend operation.
18. Unlock Bypass Entry command required prior to any Unlock 
Bypass operation. Unlock Bypass Reset command is required to 
return to reading array.
Table 16. Memory Array Command Definitions (x16 Mode)
Comm and (Notes)
 Cycles
Bus Cycles (Notes 1–4)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (5) 1 RA RD
Reset (6) 1 XXX F0
Autoselect 
(Note 7) Manufacturer ID 4 AAA AA 555 55 AAA 90 (BA)X00 01
Device ID (11) 6 AAA AA 555 55 AAA 90 (BA)X01 7E (BA)X0E 08 (BA)X0F 00/01
Program 4 AAA AA 555 55 AAA A0 PA PD
Chip Erase 6 AAA AA 555 55 A AA 80 AAA AA 555 55 AAA 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (12) 1 BA B0
Program/Erase Resume (13) 1 BA 30
CFI Query (14, 15) 1 55 98
Accelerated Program (16) 2 XX A0 PA PD
Configuration Register V eri fy (15) 3 AAA AA 555 55 (BA)AAA C6 (BA)XX RD
Configuration Register Write (17) 4 AAA AA 555 55 AAA D0 XX WD
Unlock Bypass Entry (18) 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (18) 2 XX A0 PA PD
Unlock Bypass Erase (18) 2 XX 80 XX 10
Unlock Bypass CFI (14, 18) 1 XX 98
Unlock Bypass Reset (18) 2 XX 90 XX 00

44 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
Legend:
DPB = Dynamic Protection Bit
SSA = SecSi Sector Address (A6:A0) is (0011010) . 
PD[3:0] = Program Data. Password written as four 16-bit sections.
PPB = Persistent Protection Bit
PWA = Passw ord Address. A0:A-1 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read D ata DQ0 for protection indicator bit. 
RD(1) = Read Data DQ1 for PPB Lock bit status.
SA = Sector Address where security command applies. Address bits 
A21:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010)
EP = PPB Erase Address (A6:A0) is (1111010)
X = Don’t ca re
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protecti on Mode Locking Bit
1. See Table 1 for description of bus operations.
2. All values are in hexadecim al.
3. Shaded cells in table denote read cycles. All other cycles are 
write operations.
4. During unlock and command cycles,  when lower addres s bit s are 
555 or AAAh as shown in table, address bits higher than A11 
(except where BA is required) and data bits higher than DQ7 are 
don’t ca r e s.
5. Reset command returns device to reading array.
6. Asynchronous read opera tion.
7. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate 
the bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in 
cycle 6, the program command must be issued and verified again.
8. Data is latched on rising edge of WE#.
9. Entire command sequence must be executed for each portion of 
password.
10. Comman d sequence returns FFh if PPMLB is set.
11. Password is written over four consecutive cycles, at addresses 
0-3. 
12. A 2 µs timeout is required between any two portions of password.
13. A 100 µs timeout is required between cycles 4 and 5.
14. A 1.2 ms timeout is required between cycles 4 and 5.
15. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been 
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command 
must be issued and verified again. Before issuing erase 
command, all PPBs should be programmed in order to prevent 
PPB overerasure.
16. DQ1 = 1 if PPB  locked, 0 if unlocked.
Table 17. Sector Protection Command Definitions (x16 Mode)
Comm and (Notes)
Cycles
Bus Cycles (Notes 1-4)
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset 1 XXX F0
SecSi Sector Entry 3 AAA AA 555 55 (BA)AAA 88
SecSi Sector Exit 4 AAA AA 555 55 (BA)AAA 90 XX 00
SecSi Protection Bit Program (5, 6, 7) 6 AAA AA 555 55 (BA)AAA 60 SSA 68 SSA 48 XX RD(0)
Password Program (5, 8, 9) 5 AAA AA 555 55 AAA 38 XX[0-3] PD[0-3]
Password Verify (6, 9, 10) 4 AAA AA 555 55 AAA C8 PWA[0-3] PWD[0-3]
Password Unlock (8, 11, 12) 4 AA A AA 555 55 AA A 28 PWA[0-3] PWD[0- 3]
PPB Program  (5, 6, 7, 13) 6 AAA AA 555 55 AA A 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)
All PPB Erase (5, 6, 14, 15) 6 AAA AA 555 55 AAA 60 (SA)EP 60 (SA)EP 40 (SA)WP RD(0)
PPB Lock Bit Set 3 AAA AA 555 55 AAA 78
PPB Lock Bit Status (6, 16) 4 AA A AA 555 55 AAA 58 SA RD(1)
DPB Write (8) 4 AAA AA 555 55 AAA 48 SA X1
DPB Erase (8) 4 AAA AA 555 55 AAA 48 SA X0
DPB or PPB Status (6) 4 AAA AA 555 55 AAA 58 SA RD(0)
PPMLB Program (5, 6, 7, 13) 6 AAA AA 555 55 AAA 60 PL 68 PL 48 XX RD(0)
PPMLB Status (5) 6 AAA AA 555 55 AAA 60 PL RD(0)
SPMLB Program (5, 6, 7, 13) 6 AAA AA 555 55 AAA 60 SL 68 SL 48 XX RD(0)
SPMLB Status (5) 6 AAA AA 555 55 AAA 60 SL RD(0)

April 26, 2002 Am29PDL128G 45

ADVANCE INFORMATION

WRITE OPERATION STATUS

The device provides several bits to determine the status of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 18 and the f ollowing subse c tions des c rib e the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a progr am or erase opera tion is

complete or in progress. The device also provides a hard-

war e-based output signal, RY/BY#, to det er m ine whethe r

an Embedded Program or Erase operation is in progress or

has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Em bedded Prog ram or Erase alg orit hm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

Dur ing th e E m bedded P r ogram algorithm, the devic e out-

puts on DQ7 the complement of the datum pr ogr ammed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algor ithm is

comp lete, the dev ic e o ut puts t he d at um pr ogramm ed to

DQ7 . T he sy s tem m us t pr ov ide the p ro gr am addr es s t o

read valid status information on DQ7. If a pr ogram address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximate ly 1 µs, then that ba nk retur ns to the

read mode.

During the Embe dded E rase al gorithm, D ata# P olling

produces a “0” on DQ7. When the Embedded Erase

algorithm is compl ete, or if the ba nk enter s the Er ase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an addres s within any of the

sectors selected for er asure to read valid stat us infor-

mation on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank returns to th e read mo de. If not all selecte d

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors tha t are protected. However, if the sys -

tem reads DQ7 at an address within a protected

secto r, the status may no t be valid .

When the system det ects DQ7 has cha nged from the

complement to true data, it can read valid data at

DQ31–DQ0 (or DQ15 –DQ0 for word mode) on the fol-

lowing read cycles. Just prior to the completion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ31–DQ16

(DQ15–DQ0 for word mode) while Output Enable

(OE#) is asserted low. That is, the device may change

from providing stat us informati on to valid data on DQ7.

Depending on when the system samples the DQ7 out-

put, it may read the status or v alid data. E ve n if the de-

vice has com pleted the program or erase operation

and DQ7 has valid data, the data outputs on

DQ31–DQ0 may be still invalid. Valid data on

DQ31–DQ0 (or DQ15–DQ0 for word mode) will ap-

pear on successive read cycles.

Table 18 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 20

in the AC Characteristics se ction shows the Data#

Polling timing diagram.

Figur e 5. Da ta # P o llin g A lgo ri t h m

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneous ly with DQ5.

46 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
RY/BY#: Ready/Bu sy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress  or complet e. T he RY /BY# status is valid aft er
the rising edge of the final WE# pulse in the command
sequence.  Since RY/BY# is an open-drain output , sev-
eral  RY/BY# pins can be tied t ogether in parall el with a
pull-up resistor to VCC.
If the output is low (Bus y), the device is actively eras -
ing or program ming. (This includes programming  in
the Erase Suspend mode.) If the output is high
(Rea dy) , th e dev ice  is  in the  rea d  mode , th e sta ndby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 18 shows the outputs for RY/BY#. 
DQ6: Toggle Bit I
To ggle  Bit  I on  D Q6 in di cates  whe the r an  Emb ed ded
Program or Erase  algorithm is in progress or com-
plete, or whet her the de vice has ente red  the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, a nd i s  valid  after the  rising  edge  of th e final
WE# pulse in the command sequence (prior  to the
program or  erase operatio n), and  during the  sector
erase time-out .
During an Embedded Program or Erase algo rithm op-
eration, successive r ead cycles to any address  cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complet e, DQ6 stops toggling.
After an erase command  sequence is written,  if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data.  If not all selected sectors are protected, the
Embedded Er ase  algorithm erases the  unprotected
sectors, and ignores the selected sec tors that are pro-
tected. 
The system  can use DQ 6 and DQ2 t ogether to det er-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is,  the Embedded Erase algorithm is in progress),
DQ6 togg les. Whe n the device  enters the E rase Sus -
pend mode, DQ6 stops toggling. However, the system
must  also use DQ 2 to dete rmin e which s ectors  are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs af ter the program
command sequence is written, then returns to reading
array data.
DQ 6 al so to ggl es d urin g th e er ase-s usp end- prog ram
mod e, and stops toggling  once the  Embe dded Pro-
gram algorithm is complete.
Table 18 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 21 in
the “AC Characteristics” section shows the toggle bit
timing d iagrams . Figur e 22 sho ws the difference s be-
tween  DQ2 and DQ6 in  graphical form. See also the
subsection on DQ2: Toggle Bit II.
Figur e  6. To ggle  B it A lgo r it h m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
 = Toggle? No
Program/Erase
Operation Not 
Complete, Write 
Reset Command
Program/Erase
Operation Complete
Toggle Bit
 = Toggle?
Read Byte Twice
(DQ0–DQ7)
Address = VA
Read Byte
(DQ0–DQ7)
Address =VA 
Read Byte
(DQ0–DQ7)
Address =VA 
Note: The system should recheck the toggle bit even if DQ5 
= “1” because the toggle bit may stop toggling as  DQ5 
changes to “1.” See the subsections  on DQ6 and DQ2 for 
more information.

April 26,  2002 Am29PDL128G 47
ADVANCE INFORMATION 
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with  DQ6, indi-
cates whether a particular sector is actively erasing
(that is,  the Embedded Erase algorithm is in progress),
or whether that sector is erase- suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors  that have been selected for era-
sure.  (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is  actively erasing or is er ase-sus-
pended. DQ6, by comparison, indicates whether  the
device is actively erasing, or is in Erase Suspend, but
cannot distinguis h which se ctors are selected  for era-
sure.  Thus, both s tat us  bits ar e r equired for sector and
mode information. Refer to Tabl e 18 to  com par e ou t-
puts for DQ2 and DQ6. 
Figure 6 shows the toggle bit a lgorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm . See a lso th e DQ6:  To ggle Bit I s ubsec tion.
Figure 21 shows  the toggle bit timing diagra m. Figure
22 shows the differences  between DQ2 and DQ6 in
graphic al form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figur e 6 for the  follo wing discussion. W hen-
ever the  system init ially beg ins reading t oggle bit s ta-
tus,  it mu st re ad  DQ3 1–DQ0  (or DQ15–DQ 0 for wor d
mode ) at  lea st twi ce i n a  row  to  deter mine  whe the r a
toggle bit is  toggling. Typically, the system would note
and store the value of the toggle bit after  the first read.
After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle
bit is  not toggling,  the devi ce has  completed  the pro-
gram or erase operation. The system can  read  array
data on DQ31–DQ0 (or D Q15–DQ0 for word mode)
on the following read cycle.
However, if after the initial two read cycles, the system
determines  that the toggle  bit is still tog gling, the s ys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determ ine ag ain whether  the to ggle bit  is tog -
gling , s ince  the t oggl e bit  ma y ha ve s toppe d to gglin g
just as DQ5 w ent high. If the t oggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it  is stil l toggling, the de-
vice did not  completed the operation successfully, and
the system must write the reset command to return to
reading array data. 
The remain ing scenario is  that the sy stem initially de -
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to m onitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as  described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully  completed.
The devic e may  output a  “1” on  DQ5 if t he system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system m ay read DQ 3 to determ ine whet her or not
era sure  has b egun. ( The  secto r era se tim er do es no t
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire tim e-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the  time bet ween addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sec tor Erase Command
Sequence section.
After t he sector erase comm and is writ ten, the  system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device  has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther c ommand s (except Erase S uspen d) are igno red
until the erase operation is complete. If DQ3 is “0,” the
devic e will accept  additional sec tor erase com mands.
To en sure the com mand has  been ac cepted, the  sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. I f DQ3 is high o n the s econd status  check, the
last command might not have been accepted.
Table 18 shows the status of DQ3 relative to the other
status bits.

48 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

Table 18. Writ e Operati on Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exc eeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid addr ess when reading status i nformation. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status DQ7

(Note 2) DQ6 DQ5

(N ote 1) DQ3 DQ2

(N ote 2) RY/BY#

Standard

Mode Embedded Program Algor ithm DQ7# Toggle 0 N/A No toggle 0

Embedded E ras e Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

April 26, 2002 Am29PDL128G 49

ADVANCE INFORMATION

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plast ic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applie d . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(No te 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

ACC ( N o te 2 ) . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot VSS to –2.0 V for periods of up to 20 ns.

Maximu m DC volta ge on input or I/O pins is VCC +0.5 V.

See Figure 7. During voltage transitions, input or I/O pins

may overshoot to VCC +2.0 V for periods up to 20 ns. See

Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and A CC is –0. 5 V. Du ring voltag e tran sitions , A9, OE #,

ACC, and RESET# may overshoot VSS to –2.0 V for

periods of up to 20 ns. See Figure 7. Maximum DC i nput

voltage on pin A9, OE#, and RESET# is +12.5 V which

may overshoot to +14.0 V for periods up to 20 ns.

Maximum DC input voltage on ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than o ne output may be s horted to ground a t a

time. Duration of the short circuit should not be greater

than one second.

Stresses above th ose listed under “Absolute Maximum

Ratings” may c ause pe rman ent da mage to the devi ce. Th is

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 7. M aximum Negative

Overshoot Waveform

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industri al (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

Supply Voltages

VCC for full regulated range . . . . . . . . . .3.0 V to 3.6 V

VCC for full voltage range . . . . . . . . . . . .2.7 V to 3.6 V

VIO (see No te) . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Note: For all AC and DC specifications, VIO = VCC; contact

AMD for other VIO options.

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

50 Am29PDL128G April 26, 2002
ADVANCE INFORMATION 
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 4mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 
200 nA.
5. Not 100% tested.
Parameter 
Symbol Parameter Descriptio n Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILIT A9, OE#, RESET# 
Input Load Current VCC = VCC max; VID= 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH
VCC = VCC max ±1.0 µA
ICC1
VCC Active Inter-page Read Current,
Word/Doub le Word Modes
(Notes 1, 2) CE# = VIL, OE# = VIH
1 MHz 4.5 9
mA5 MHz 20 40
10 MHz 38 45
VCC Active Intra-page Read Current,
Word/Double Word Modes (Note 2) CE# = VIL, OE# = VIH 1 MHz 9 18 mA
5 MHz 37 45
ICC2 VCC Active Write Current ( Notes 2, 3) C E# = VIL, OE# = VIH, WE# = VIL 17 35 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 1.5 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1.5 5 µA
ICC5 Auto matic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 1.5 5 µA
ICC6 VCC Active Re ad-While-Program 
Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 30 45 mA
Dbl. Word 30 45
ICC7 VCC Active Read-While-Erase 
Curr ent (Notes 1, 2) CE# = VIL, OE# = VIH Word 21 45 mA
Dbl. Word 21 45
ICC8 VCC Active Program-W hile-Erase-
Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA
IACC ACC Accelerated Program Current,
Double Word or Word CE# = VIL, OE# = VIH ACC pin 5 10 mA
VCC pin 15 30 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VHH Voltage for ACC Program 
Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
VID Voltage for Autoselect and 
Temporary Se ctor Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VIO V
VOH2 IOH = –100 µA, VCC = VCC min V
IO–0.4
VLKO Low  VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

April 26, 2002 Am29PDL128G 51

ADVANCE INFORMATION

TEST CONDITIONS

Table 19. Test S pecifications

KEY T O SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

Figure 9. Test Setup

Test Condition 70R, 70, 80, 90 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 pF

Input Rise and Fal l Times 5 ns

Input P u lse Levels 0.0–3.0 V

Input timing measur ement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitte d Chang ing, State Unknown

Does Not Apply Center L ine is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

Figure 10. Input Waveforms and Measurement Levels

52 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 1 9 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to

the data bus driven to VCC/2 is taken as tDF.

Parameter

Description Test Setup

Speed Options

JEDEC Std. 70R, 70 80 90 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 70 80 90 ns

tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 70 8090ns

tELQV tCE Chip Ena b le to Output Delay OE# = VIL Max 70 8090ns

tPACC Page Access Time Max 25 30 35 ns

tGLQV tOE Output Enable to Output Delay Max 25 30 40 ns

tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Ma x 25 30 30 ns

tGHQZ tDF Output Enable to O utput High Z (Notes 1, 3) Max 25 30 30 ns

tAXQX tOH Output Hol d Time From Addresses, CE# or OE#,

Whichever Occurs First Min 4 5 5 ns

tOEH Output Enable Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

Figure 11. Read Operation Timings

April 26, 2002 Am29PDL128G 53

ADVANCE INFORMATION

AC CHARACTERISTICS

Figure 12. P age Read Operation Timings

A21

CE#

OE#

A-1

Data Bus

Same Page

Aa Ab Ac Ad

Qa Qb Qc Qd

tACC tPACC tPACC tPACC

54 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed Options UnitJEDEC Std

tReady RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 13. Reset Timings

April 26, 2002 Am29PDL128G 55

ADVANCE INFORMATION

AC CHARACTERISTICS

W ord/Dou ble Word Configuration ( WORD#)

Param eter Speed Options

JEDEC Std Description 70R, 70 80 90 Unit

tELFL/tELFH CE# to WORD# Switching Low or High Max 5 ns

tFLQZ WORD# Switching Low to O utput HIGH Z Max 30 30 30 ns

tFHQV WORD# Sw itching High to Output Active Min 70 80 90 ns

Data

Switching from

word mode to

double word mode

Switching from

double word mode

to word mode

tELFL

tELFH

tFLQZ

tFHQV

Address

Input

Address

Input

Output

OutputOutput

Output

Output Output

DQ30–DQ16

DQ31/A-1

DQ15–DQ0

WORD#

OE#

CE#

Figure 14. WORD# Timings for Read Operations

Note: Refer to t he Erase/Program Operations table for tAS and tAH spec ifications.

Figure 15. WORD# Timings for Write Operations

CE#

WE#

WORD#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

56 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And P rogramming Perform ance” section for more information.

Parameter Spe e d Op t ion s

JEDEC Std. Description 70R, 70 80 90 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns

tAVWL tAS Addre ss Setup Time Min 0 ns

tASO Address Setup Time to OE# low during toggle bit polling Min 15 n s

tWLAX tAH Addre ss Hold Time Min 45 ns

tAHT Address Hold Time From CE# or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 45 45 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggl e bit polling Min 20 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE # Ho ld Time Mi n 0 ns

tWLWH tWP Write Pulse Width Min 35 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 8.6 µs

Double Word Typ 12.6

tWHWH1 tWHWH1 Ac celerated Programming Operation,

Double Word or Word (Note 2) Typ 4 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Write Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

April 26, 2002 Am29PDL128G 57

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

tCH

otes:

. PA = program address, PD = program data, DOUT is the true data at the program address.

. Illustration shows device in word mode.

Figure 16. Program Operation Timi ng s

WP#/ACC tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 17. Accelerated Program Timing Diagram

58 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Status DOUT

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

otes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “W rite Operation Status ”.

. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operatio n T imi ngs

April 26, 2002 Am29PDL128G 59

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data

Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

Figure 19. Back-to-back Read/Write Cycle Timings

WE#

CE#

OE#

High Z

DQ7

DQ6–DQ0

RY/BY#

BUSY

Complement True

Addresses VA

OEH

VA VA

Status Data

Complement

Status Data True

Valid Data

ACC

Note: VA = Valid address. Illustration show s first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

60 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. T he system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

April 26, 2002 Am29PDL128G 61

ADVANCE INFORMATION

AC CHARACTERISTICS

Temporary Sector Unpr otect

Note: Not 100% tested.

Parameter

All S pe e d Op t ion sJEDEC Std Description Unit

tVIDR VID Rise and Fa ll Time (See Note) Min 500 ns

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRSP RESET# Setup Tim e for Tempo rary Sector

Unprotect Min 4 µs

tRRB RESET# Hold Time from RY/BY# High for

Temporary Se ctor Unprotect Min 4 µs

RESET#

tVIDR

VID

VIL or VIH

VID

VIL or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

Figure 23. Tem porary Sector Unprotect Timing Diagram

62 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect/Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotec t, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector/Sector Block Protect and

Unprotect Timi ng Diagram

April 26, 2002 Am29PDL128G 63

ADVANCE INFORMATION

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And P rogramming Perform ance” section for more information.

Parameter Speed Options

JEDEC Std. Description 70R, 70 80 90 Unit

tAVAV tWC Write Cycle Tim e (Note 1) Min 70 80 90 ns

tAVWL tAS Addr ess Setup Tim e Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 ns

tDVEH tDS Data Setup Time Min 35 45 45 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# P ulse Wid th Min 35 ns

tEHEL tCPH CE# P ulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Word Typ 8.6 µs

Double Word Typ 12.6

tWHWH1 tWHWH1 Accelerated Programming Operatio n,

Double Word or Word (Note 2) Typ 4 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec

64 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or era se operation.

2. PA = prog ra m a dd re s s , SA = s e ct or addres s, PD = pro gram da t a.

3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

4. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Writ e (Erase/ Program) Operati on Timings

April 26, 2002 Am29PDL128G 65

ADVANCE INFORMATION

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000 ,000 cycl es. Additiona lly,

programming typicals assume checkerboard pattern.

2. Under worst case conditio ns of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhe ad is the time required to exe cute the two- or fo ur-bus- cycle sequence for the program command. See Tables

14–17 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25 °C, f = 1.0 MHz.

DATA RETENTION

Paramete r Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.2 TBD sec Excludes 00h programming

prior to eras ure (Note 4)

Chip Erase Time 54 sec

Double Word Program Time 12.6 TBD µs

Excludes system level

overhead (Note 5)

Word Program Time 8.6 TBD µs

Accelerated Double Word Program Time 4 TBD

Accelerated Word Program Time 4 TBD µs

Chip Program Time

(Note 3) Double Word Mode 50.4 200 sec

Word Mode TBD TBD

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A 9 , OE#, and RESET#) –1.0 V 13 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Curre nt –100 mA +10 0 mA

Parameter

Symbol Parameter Description Test Set up Typ Max Unit

CIN Input Capac itanc e V IN = 0 6 7.5 pF

COUT Output Cap ac itanc e VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 8 10 pF

Parameter Descrip tion Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10Years

125°C20Years

66 Am29PDL128G April 26, 2002

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

LAB080—80-Ball Fortified Ball Grid Array

10 x 15 mm package

0.50 BSC.

N/A

15.00 mm x 10.00 mm

PACKAGE

LAB 080

NOM.

---

1.40

---

MAX.

10.00 BSC.

15.00 BSC.

---

MIN.

0.60

0.40

9.00 BSC.

7.00 BSC.

0.60 0.70

1.00 BSC.

0.50 1.00 BSC.

JEDEC

PACKAGE

SYMBOL

φb

NOTE

PACKAGE OUTLINE TYPE

DEPOPULATED SOLDER BALLS

MATRIX SIZE E DIRECTION

MATRIX FOOTPRINT

BALL PITCH - D DIRECTION

BALL PITCH - E DIRECTION

BODY SIZE

STANDOFF

BODY SIZE

BODY THICKNESS

PROFILE HEIGHT

BALL DIAMETER

MATRIX SIZE D DIRECTION

BALL COUNT

MATRIX FOOTPRINT

SOLDER BALL PLACEMENT

SD/SE

SIDE VIEW SEATING PLANE C

C0.25

C0.15

1.00 ± 0.5

TOP VIEW 2X

0.20

CORNER

A1 CORNER ID.

(INK OR LASER)

φ 0.50

1.00 ± 0.5

0.20

2X C

BOTTOM VIEW

CORNER

ABCDEFGHJK

CAB

NXφb

φ0.25

φ0.10 M

NOTES UNLESS OTHERWISE SPECIFIED:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 .

2. ALL DIMENSIONS ARE IN MILLIMETERS .

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010

(EXCEPT AS NOTED).

4. e REPRESENTS THE SOLDER BALL GRID PITCH .

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"

DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE

IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER

BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C .

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER

OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D

OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

April 26, 2002 Am29PDL128G 67

ADVANCE INFORMATION

REVISION SUMMARY

Revision A (October 29, 2001)

Init ial r eleas e.

Revision A+1 (November 13, 2001)

Simultan eous Operation Block Diagram

Added drawing.

Table 13, Primary V endor-Specific Extended Query

Corrected data for 4Dh and 4Eh addresses (dou-

ble- word mode).

Physical Dimensions

Added LAB080 package drawing.

Revision A+2 (February 8, 2002)

Global

Added 90 n s speed op tion. At this speed, tDF is 30 ns

and t OH is 5 ns . Fo r all spee ds, chan ged ty pica l wor d

prog ram ming time to 8.6 µs , and typ ical doub le wo rd

programming time to 12.6 µs.

Simultan eous Operation Block Diagram

Deleted BYTE# input.

Revision B (April 26, 2002)

Global

Added 70R (regulated voltage range) to speed op-

tions.

Ordering Information

Added “V” to package marking.

Device Bus Operations

Corrected sector size references in sector address ta-

ble.

Pas sword P rotection Mode s ect ion: Clar ified tha t first

8 bytes of SecSi Sector should be reserved for the

password. Added description of using password and

SecSi Sector concurrently.

SecSi Sector Flash Memory Region

Added section on using password and SecSi Sector

concurrently.

Table 13, Primary Vendor-Specific Exten ded Query

Corrected data for addresses 4D and 4E h.

Command Definitions

Deleted PPB Status Command section.

Password Program Command section: Modi fied firs t

paragraph.

Password Unlock Command section: Modified second

paragraph.

PPB Lock Bit Set Command section: Modified entire

section.

Substantial modifications were made to the command

definitions tables and notes, including the following:

deleted the PPB Status command sequence; added

bank address requirements to SecSi Sector com-

mand ; separated m emory array and s ector prot ection

command sequences for easier reference.

DC Characteristics

In Note 1 of the CMOS Compatible table, changed typ-

ical ICC current from 2 to 4mA/MHz. Changed ICC1 typi-

cal and maximum read current s , added cur r ent s for 10

MHz oper ation. A dded specif ications for i ntra-page

read current. Changed ICC6 typical current to 30 mA.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.