9 kHz to 7 GHz, Bidirectional RMS and VSWR Detector ADL5920 Data Sheet GND4 GND3 GND2 GND1 30 29 28 27 24 1 ADL5920 31 26 BIDIRECTIONAL BRIDGE 32 VNEG1 2 23 VNEG2 CHPR+ 3 21 CHPF+ CHPR- 4 22 CHPF- 16 CRMSF 18 VRMSF 12 DECL 10 VOCM 19 VREF 15 VTGT 20 TADJI 5 PWDN/ TADJS FORWARD PATH RMS DETECTOR REVERSE PATH RMS DETECTOR CRMSR 9 VRMSR 7 VTEMP 6 VREF 2.5V TEMPERATURE SENSOR 8 13 11 14 17 VPOS1 VPOS2 VDIFF- VDIFF+ VPOS3 APPLICATIONS Industrial metering Broadband inline power and return loss measurement Transmit power control and automatic level control in wireless transmitters, signal generators, network analyzers, and wireless communications testers Condition based monitoring of system modules, cables, and connectors RFOUT 25 16085-001 RFIN GND5 FUNCTIONAL BLOCK DIAGRAM Wideband matched 9 kHz to 7 GHz operation Forward and reverse power and return loss measurement 49 dB 1.0 dB input range with -19 dBm minimum input level, 1.0 dB at 1 GHz Linear in dB rms (crest factor insensitive) outputs Insertion loss: 1.1 dB at 1 GHz and 1.9 dB at 6 GHz Input and output return loss and VSWR 1 GHz: 22 dB/1.16:1 3 GHz: 14 dB/1.5:1 6 GHz: 12 dB/1.7:1 Output IP3: 70.5 dBm at 1 GHz Directivity 20 dB at 1 GHz 13 dB at 3 GHz 5 dB at 6 GHz Maximum input power 30 dBm for open or shorted termination 33 dBm for matched termination GND6 FEATURES Figure 1. GENERAL DESCRIPTION The ADL5920 is an ultrawideband, bidirectional detector that simultaneously measures forward and reverse rms power levels in a signal path, along with the return loss. (relative to the dc voltage at RFIN and RFOUT). The internal detector circuitry is also dc-coupled to the bidirectional bridge to support measurements down to 9 kHz. The forward and reverse power traveling through the integrated bidirectional bridge is measured using two 50 dB linear in dB rms detectors. The detector output voltages, available at the VRMSF and VRMSR pins, are proportional to the forward and reflected power in dBm. A third, differential, output produces a voltage proportional to the return loss (reflection coefficient) in dB, closely related to the voltage standing wave ratio (VSWR). The common-mode level of this output is externally adjustable through the VOCM pin. The maximum input signal on each of the RF ports (RFIN and RFOOUT) is 30 dBm for open and shorted terminations and 33 dBm for a matched termination. The primary transmission line of the bidirectional bridge, from RFIN to RFOUT (or vice versa) is dc-coupled and allows small amounts of dc bias current through the bridge. When dc-coupled to source and load, the positive and negative supply pins of the ADL5920 must be connected to +5 V and -2.5 V, respectively Rev. B The ADL5920 draws 160 mA from a 5 V supply and has a low power, power-down mode controlled through the PWDN/TADJS pin. The device is supplied in a 32-lead, 5 mm x 5 mm LFCSP and is specified for ambient operating temperatures in the -40C to +85C range. Multifunction pin names may be referenced by their relevant function only. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5920 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Basic Connections ...................................................................... 18 Applications ....................................................................................... 1 CHPR, CHPF Capacitors .......................................................... 18 Functional Block Diagram .............................................................. 1 VREF Interface ........................................................................... 19 General Description ......................................................................... 1 VDIFF Output Interface ............................................................ 19 Revision History ............................................................................... 2 Temperature Drift Compensation ........................................... 19 Specifications..................................................................................... 3 Setting VTGT.............................................................................. 19 Absolute Maximum Ratings ............................................................ 8 Choosing Values for CRMSF and CRMSR ............................. 20 Thermal Resistance ...................................................................... 8 RF Power and Return Loss Calculation .................................. 21 ESD Caution .................................................................................. 8 DC-Coupled Operation............................................................. 22 Pin Configuration and Function Descriptions ............................. 9 Evaluation Board ............................................................................ 23 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 26 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 26 Applications Information .............................................................. 18 REVISION HISTORY 12/2019--Rev. A to Rev. B Changes to Applications Section and Figure 1 ............................. 1 Changes to Figure 38 ...................................................................... 18 Changes to RF Power and Return Loss Calculation Section .... 21 Changes to Figure 43 ...................................................................... 22 3/2019--Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 26 1/2019--Revision 0: Initial Version Rev. B | Page 2 of 26 Data Sheet ADL5920 SPECIFICATIONS VPOS1, VPOS2, VPOS3 = 5 V, VNEG = 0 V, TA = 25C, output impedance (ZO) = 50 , unless otherwise noted (see Figure 38). Table 1. Parameter 1 OVERALL FUNCTION Frequency Range Input and Output Impedance Maximum Input Power (PIN) 10 MHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 100 MHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Test Conditions/Comments Min Typ 0.009 RFIN, RFOUT require 50 terminations Open or short termination Matched termination VRMSF, VRMSR, TADJI voltage (VTADJI) = 0 V, TADJS voltage (VTADJS) = 0 V 50 load on RFOUT 0.1 F capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, continuous wave (CW) input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Deviation from output at TA = 25C -40C, PIN = -10 dBm -40C, PIN = 20 dBm 85C, PIN = -10 dBm 85C, PIN = 20 dBm 70C, PIN = -10 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0 V 50 load on RFOUT 0.1 F capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Deviation from output at TA = 25C -40C, PIN = -10 dBm -40C, PIN = 20 dBm 85C, PIN = -10 dBm 85C, PIN = 20 dBm 70C, PIN = -10 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR Rev. B | Page 3 of 26 50 30 33 Max Unit 7000 MHz dBm dBm 0.9 43 1.02:1 43 50 30 dB dB -20 dBm -0.46 -0.4 -0.02 0.18 -0.03 0.2 61 -29.7 dB dB dB dB dB dB mV/dB dBm 0.9 37 1.03:1 43 49 30 dB dB dB dB dBm -19 dBm -0.43 -0.46 0.04 0.26 0.04 0.28 61 -29.8 dB dB dB dB dB dB mV/dB dBm dB dB dBm ADL5920 Parameter 1 1 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity Output Third-Order Intercept (IP3) 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 2 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 3 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Data Sheet Test Conditions/Comments VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0 V 50 load on RFOUT 0.1 F capacitors on CHPR+/CHPR- and CHPF+/CHPF- 27 dBm per tone at RFIN, RFOUT terminated with 50 , 1 MHz tone spacing VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Deviation from output at TA = 25C -40C, PIN = -10 dBm -40C, PIN = 20 dBm 85C, PIN = -10 dBm 85C, PIN = 20 dBm 70C, PIN = -10 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Deviation from output at TA = 25C -40C, PIN = -10 dBm -40C, PIN = 20 dBm 85C, PIN = -10 dBm 85C, PIN = 20 dBm 70C, PIN = -10 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Minimum Input Level, 1.0 dB Rev. B | Page 4 of 26 Min Typ Max Unit 1.1 22 1.16:1 20 70.5 dB dB 49 30 dB dBm -19 dBm -0.41 -0.32 -0.5 -0.11 -0.24 0.15 61 -27 dB dB dB dB dB dB mV/dB dBm 1.3 17 1.30:1 16 45 28 dB dB dB dB dBm -17 dBm -0.44 -0.73 -0.98 -0.58 -0.36 0.04 60.6 -26 dB dB dB dB dB dB mV/dB dBm 1.5 14 1.5:1 13 43 26 dB dB dB dB dBm -17 dBm dB dBm Data Sheet Parameter 1 Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 4 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 5 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept ADL5920 Test Conditions/Comments Deviation from output at TA = 25C -40C, PIN = -10 dBm -40C, PIN = 20 dBm 85C, PIN = -10 dBm 85C, PIN = 20 dBm 70C, PIN = -10 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0 V, VTADJS = 0.2 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +30 dBm to -15 dBm Deviation from output at TA = 25C -40C, PIN = 0 dBm -40C, PIN = 20 dBm 85C, PIN = 0 dBm 85C, PIN = 20 dBm 70C, PIN = 0 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0.2 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +15 dBm to -10 dBm Deviation from output at TA = 25C -40C, PIN = 0 dBm -40C, PIN = 20 dBm 85C, PIN = 0 dBm 85C, PIN = 20 dBm 70C, PIN = 0 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR Rev. B | Page 5 of 26 Min Typ Max Unit -0.38 -0.71 -1.83 -1.48 -0.85 -0.37 59.4 -25.5 dB dB dB dB dB dB mV/dB dBm 1.7 12.5 1.7:1 7 41 25 dB dB dB dB dBm -16 dBm -0.07 -0.53 -1.95 -2.9 -0.81 -1.0 59 -24.6 dB dB dB dB dB dB mV/dB dBm 1.7 11 1.9:1 6 37 24 dB dB -13 dBm -0.86 -1.46 -1.9 -2.94 -0.5 -1.09 59.2 -22.3 dB dB dB dB dB dB mV/dB dBm dB dB dBm ADL5920 Parameter 1 6 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept 7 GHz Insertion Loss Return Loss (RFIN, RFOUT) VSWR (RFIN, RFOUT) Directivity 1.0 dB Input Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept OUTPUT INTERFACE Short-Circuit Current Sourcing Sinking Small Signal Output Impedance Rise Time Fall Time OUTPUT INTERFACE Common-Mode Output Voltage Small Signal Output Impedance Current Capability Source Sink Data Sheet Test Conditions/Comments VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from +20 dBm to -5 dBm Deviation from output at TA = 25C -40C, PIN = 0 dBm -40C, PIN = 20 dBm 85C, PIN = 0 dBm 85C, PIN = 20 dBm 70C, PIN = 0 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR, VTADJI = 0.2 V, VTADJS = 0.8 V 50 load on RFOUT No capacitors on CHPR+/CHPR- and CHPF+/CHPF- VRMSF, VRMSR, CW input Slope and intercept calculated using linear regression from 20 dBm to 0 dBm Deviation from output at TA = 25C -40C, PIN = 0 dBm -40C, PIN = 20 dBm 85C, PIN = 0 dBm 85C, PIN = 20 dBm 70C, PIN = 0 dBm 70C, PIN = 20 dBm VRMSF, VRMSR VRMSF, VRMSR VRMSF, VRMSR VRMSF and VRMSR = 3.5 V VRMSR and VRMSR = 100 mV, no RF Input PIN = off to -10 dBm, 10% to 90%, 10 nF on CRMSF and CRMSR PIN = -10 dBm to off, 10% to 90%, 10 nF on CRMSF and CRMSR VDIFF+, VDIFF- VOCM Rev. B | Page 6 of 26 Min Typ Max Unit 1.9 12 1.7:1 5 33 22 dB dB dB dB dBm -11 dBm -0.74 -1.45 -3.36 -3.57 -1.14 -1.72 57.7 -19.7 dB dB dB dB dB dB mV/dB dBm 2 14 1.5:1 7 31 21 dB dB -10 dBm -1.39 -2.75 -3.77 -3.11 -1.55 -1.15 57.4 -17.7 dB dB dB dB dB dB mV/dB dBm 73 71 0.4 18 mA mA s 75 s 2.5 0.4 V 69 69 mA mA dB dB dBm Data Sheet Parameter 1 TEMPERATURE COMPENSATION Input Voltage Range Input Bias Current Input Resistance VOLTAGE REFERENCE Output Voltage Small Signal Output Impedance Current Capability Source Sink TEMPERATURE REFERENCE Output Voltage Temperature Coefficient POWER-DOWN INTERFACE AND TEMPERATURE COMPENSATION Voltage Level To Enable To Disable Enable Time Disable Time Input Bias Current Input Resistance POWER SUPPLY Supply Voltage Quiescent Current 1 ADL5920 Test Conditions/Comments TADJI Min Typ Max Unit 1 14 70 V A k 2.5 3.1 V 9.8 4.6 mA mA 1.38 4.5 V mV/C 0 VTADJI = 1 V VREF TA = 25C, load resistance (RL) = 10 k VTEMP TA = 25C, RL 10 k -40C TA +85C, RL 10 k Pin PWDN/TADJS 1.2 10 V V s 5 s 36 70 A k 1.5 PIN = 10 dBm, PWDN/TADJS at 50% to output voltage at 90%, 10 nF on CRMSF and CRMSR PIN = 10 dBm, PWDN/TADJS at 50% to output voltage at 10%, 10 nF on CRMSF and CRMSR VTADJS = 2.5 V VPOS1, VPOS2, VPOS3 4.9 130 PWDN/TADJS low PWDN/TADJS high 5 160 1 5.1 200 3 V mA mA When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. B | Page 7 of 26 ADL5920 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage (VPOS1, VPOS2, and VPOS3) Negative Supply Voltage (VNEG1 and VNEG2) Input Average Radio Frequency (RF) Power1 50 Load Open or Shorted Load Equivalent Voltage, Sine Wave Input PWDN/TADJS, TADJI, VOCM VTGT Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 5.5 V -3 V 33 dBm 30 dBm 28.25 V p-p 0 V, VPOSx 4V 150C -40C to +85C -65C to +150C 300C JA is junction to ambient thermal impedance, and JC is junction to case (exposed pad) thermal impedance. Table 3. Thermal Resistance Package Type1 CP-32-7 1 JA 44.05 JC 1.08 Unit C/W No airflow with the exposed pad soldered to a 4-layer JEDEC board. ESD CAUTION Guaranteed by design based on extended duration bench testing at 85C case temperature Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 26 Data Sheet ADL5920 32 31 30 29 28 27 26 25 RFIN RFIN GND6 GND5 GND4 GND3 RFOUT RFOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADL5920 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND2 VNEG2 CHPF- CHPF+ TADJI VREF VRMSF VPOS3 NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE WITH LOW THERMAL AND ELECTRICAL IMPEDANCE. 16085-002 CRMSR VOCM VDIFF- DECL VPOS2 VDIFF+ VTGT CRMSF 9 10 11 12 13 14 15 16 GND1 VNEG1 CHPR+ CHPR- PWDN/TADJS VTEMP VRMSR VPOS1 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 24, 27 to 30 2, 23 Mnemonic GND1, GND2, GND3, GND4, GND5, GND6 VNEG1, VNEG2 8, 13, 17 VPOS1, VPOS2, VPOS3 3, 4, 21, 22 CHPR+, CHPR-, CHPF+, CHPF- 5 PWDN/TADJS 6 7, 18 VTEMP VRMSR, VRMSF 9, 16 CRMSR, CRMSF 10 VOCM 11, 14 VDIFF-, VDIFF+ Description RF Ground. Connect all ground pins to a low impedance ground plane. Negative Supply Pins. For normal single-supply operation, connect these pins to ground. In applications where the RF input and output are dc-coupled, apply a -2.5 V supply voltage to these pins along with a +5 V power supply on VPOS1, VPOS2, and VPOS3. In this dc-coupled operating mode, Pin 12 (DECL) must be connected to ground. Power Supply. Separately decouple each power supply pin using 100 pF and 0.1 F capacitors. The nominal supply voltage on these pins is 5 V. Offset Compensation Loop Control. The capacitances on these pin pairs set the highpass corner frequency of the internal offset compensation loops, which in turn sets the minimum operating frequency of the rms detectors in the forward and reverse paths. For normal operation, add a capacitor from each pin to ground along with a capacitor across the pins. To operate at input frequencies down to 9 kHz, capacitances in the 1 F range are required. To maintain the specified directivity, leave these pins open when operating at frequencies above 2 GHz. Temperature Compensation and Shutdown. This pin is a dual function pin that controls temperature slope compensation at voltages <1.0 V and/or shuts down the device at voltages >1.4 V. The temperature compensation voltage is set by connecting this pin to VREF through a resistor divider. Temperature Sensor Output of 1.38 V at TA = 25C with a Coefficient of 4.5 mV/C. Reverse and Forward RMS Voltage Measurement. The voltages on these pins are proportional to the decibel power of the incident signal to the RFOUT and RFIN pins. RMS Averaging Capacitor for Reverse and Forward Path Detectors. Connect rms averaging capacitors between CRMSR and ground and between CRMSF and ground to set the averaging time constant of the forward and reverse rms detectors. For normal operation, the values of these two capacitors must be equal. Common-Mode Input Voltage for VDIFF+ and VDIFF-. The input voltage applied to VOCM sets the common-mode voltage for the VDIFF+ and VDIFF- differential pair. The nominal voltage on this pin is 2.5 V. However, this value can be reduced to as low as 1.5 V to accommodate the common-mode requirements of the ADC, which is driven by VDIFF+ and VDIFF-. The VOCM input requires a bias current of 1 mA and must be driven from a low impedance source. VOCM can be driven from the VREF pin but the connection must include a 1 k resistor to ground. Return Loss and VSWR Output. The differential voltage on these pins is proportional to the dB return loss of the load connected to the RFOUT port when the device is driven through the RFIN port. This differential voltage has a bias level equal to the voltage applied to VOCM, nominally 2.5 V. Rev. B | Page 9 of 26 ADL5920 Data Sheet Pin No. 12 Mnemonic DECL 15 VTGT 19 VREF 20 TADJI 25, 26, 31, 32 RFOUT, RFIN EPAD Description Internal Decoupling Node. Decouple this pin with a 0.1 F capacitor to ground. Do not use the voltage on this pin, nominally 3.2 V, externally to set any bias levels. In dc-coupled applications where VNEGx is connected to -2.5 V, this pin must be connected directly to ground. RMS Target Voltage. The voltage applied to this pin sets the target RF level at the output of the internal voltage controlled amplifiers that drive the internal squaring cells of the rms detectors. The recommended voltage for VTGT is 1 V. Increasing VTGT above 1 V degrades the rms accuracy of the ADL5920. Reducing VTGT below 1 V can improve the rms accuracy for signals with high crest factors. The voltage on this pin can be derived from a resistor divider circuit that is driven by the VREF pin (Pin 19). Reference Voltage Output. This voltage reference has a nominal value of 2.5 V. This reference output voltage can set the voltage to the TADJI, TADJS, VTGT, and VOCM pins. RMS Detector Temperature Compensation. Use this pin to fine tune the temperature intercept stability of the rms detectors. The voltage applied to this pin can be derived from VREF using a simple resistor divider. RF Inputs and Outputs. The two RFIN pins are common inputs that must always be connected to each other. Likewise, the two RFOUT pins must always be connected to each other. The power of the incident signal on RFIN is measured on the VRMSF pin, and the power on the incident signal into RFOUT is measured on the VRMSR pin. The ratio of the incident signals on RFIN and RFOUT is measured on the VDIFF+ and VDIFF- pins. The RFIN and RFOUT pins are interchangeable, allowing the source signal to drive into RFOUT with the load connected to RFIN. RFIN and RFOUT are normally ac-coupled to the source and load. RFIN and RFOUT can be dc-coupled by connecting a -2.5 V supply to the two VNEGx pins and by connecting the DECL pin to ground. Exposed Pad. Connect the exposed pad to a ground plane with low thermal and electrical impedance. Rev. B | Page 10 of 26 Data Sheet ADL5920 TYPICAL PERFORMANCE CHARACTERISTICS 2 2 RFIN TO RFOUT RFOUT TO RFIN 1 1 INSERTION LOSS (dB) 0 -3 -4 -5 -2 -3 -4 -6 -6 -7 -7 -8 100k 1M 10M 100M 1G 10G FREQUENCY (Hz) Figure 3. Forward and Reverse Insertion Loss vs. Frequency +85C +70C +25C 0C -40C -5 -8 10M 10G Figure 6. Forward Insertion Loss vs. Frequency at Various Temperatures 2.5 10MHz (CHPF,CHPR = 100nF) 100MHz (CHPF,CHPR = 100nF) 1GHz (CHPF,CHPR = 100nF) 2GHz (CHPF,CHPR = OPEN) 4GHz (CHPF,CHPR = OPEN) 6GHz (CHPF,CHPR = OPEN) 10 2.0 VDIFF (VDIFF+ - VDIFF -) (V) 0 RETURN LOSS (dB) 1G FREQUENCY (MHz) 20 -10 -20 -30 -40 -50 1.5 1.0 0.5 INPUT RETURN LOSS (RFIN) OUTPUT RETURN LOSS (RFOUT) -60 100M 16085-006 -2 -1 16085-003 INSERTION LOSS (dB) 0 -1 1 10 100 1k 10k FREQUENCY (MHz) 0 16085-004 -80 0.1 Figure 4. Return Loss vs. Frequency 0 5 10 4.0 CHPF, CHPR = 100nF CHPF, CHPR = OPEN 25 30 2 VRMSF LTE (9MHz BW, PEP =10.39dB) VRMSF QPSK (5MSPS, PEP = 3.8dB) VRMSF 16 QAM (5MSPS, PEP = 6.3dB) VRMSF 64 QAM (5MSPS, PEP = 7.4dB) V RMS CW PEP = 0dB 3.5 40 3.0 1 25 20 2.5 0 2.0 1.5 ERROR CW ERROR LTE ERROR QPSK ERROR 16 QAM ERROR 64 QAM 15 1.0 10 0.5 5 100M 1G FREQUENCY (MHz) 10G 0 -40 16085-007 0 10M Figure 5. Directivity vs. Frequency with Bridge Driven from RFIN at 20 dBm and RFOUT Terminated with 50 -30 -20 -10 0 PIN (dBm) 10 20 -1 30 -2 40 16085-009 30 ERROR (dB) 35 VRMSF (V) DIRECTIVITY (dB) 20 Figure 7. VDIFF (VDIFF+ - VDIFF-) vs. Applied Return Loss on RFOUT, Bridge Driven from RFIN at 15 dBm and Variable Return Loss at RFOUT 50 45 15 APPLIED RETURN LOSS ON RFOUT (dB) 16085-007 -70 Figure 8. VRMSF Error from CW Linear Reference vs. Signal Modulation, Frequency = 1 GHz, CRMSF = 0.1 F, Error Calculated Using Linear Regression of Data From -15 dBm to +30 dBm (BW Stands for Bandwidth and PEP Stands for Peak Envelope Power) Rev. B | Page 11 of 26 4.0 3.5 2.5 2.0 4.0 4 3.5 3 3.0 2 2.5 1 1.5 1.0 1.0 0.5 0.5 0 -30 -20 -10 0 10 20 30 PIN (dBm) Figure 9. VRMSF Output Voltage vs. PIN at Various Frequencies, Forward Drive 0 2.0 1.5 0 -40 16085-010 VRMMSF (V) 3.0 VRMSF (V) 7GHz 6GHz 5GHz 1GHz 100MHz 10MHz 4GHz 3GHz 2GHz +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR -30 -20 -10 0 10 20 -1 ERROR (dB) Data Sheet -2 -3 -4 30 16085-013 ADL5920 RF INPUT (dBm) Figure 12. VRMSF Output Voltage and Error vs. RF Input and Temperature at 10 MHz, Error Calculated Using Linear Regression of Data Between +30 dBm and -15 dBm, TADJS = 0 V, TADJI = 0 V, 0.1 F Across CHPF+, CHPF- 4.0 4.0 4 3.5 3 3.0 2 2.5 1 +30dBm 3.5 +25dBm +20dBm +5dBm 2.0 1.5 0dBm -5dBm 0 2.0 +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 1.5 -10dBm 1.0 -15dBm 1.0 0.5 -20dBm -25dBm 0.5 -30dBm 0.1 1 10 FREQUENCY (GHz) 0 -40 16085-011 0 0.01 Figure 10. VRMSF vs. Frequency at Various Input Power Levels, Forward Drive -1 ERROR (dB) +10dBm -2 -3 -4 -30 -20 -10 0 10 20 16085-014 2.5 +15dBm VRMSF (V) VRMSF (V) 3.0 30 RF INPUT (dBm) Figure 13. VRMSF and Error vs. RF Input and Temperature at 100 MHz, Error Calculated Using Linear Regression of Data Between +30 dBm and -15 dBm, TADJS = 0 V, TADJI = 0 V, 0.1 F Across CHPF+, CHPF- 4.0 4.0 4 3.5 3 3.0 2 2.5 1 2.0 0 +30dBm 3.5 3.0 +25dBm +20dBm +5dBm 2.0 1.5 0dBm -5dBm +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 1.5 -10dBm 1.0 0.5 1.0 -15dBm -20dBm -25dBm 0.5 -30dBm 0.1 FREQUENCY (GHz) 1 10 0 -40 16085-012 0 0.01 Figure 11. VRMSR vs. Frequency at Various Input Power Levels, Reverse Drive -30 -20 -10 0 RF INPUT (dBm) 10 20 -1 ERROR (dB) +10dBm -2 -3 -4 30 16085-015 2.5 VRMSF (V) VRMSR (V) +15dBm Figure 14. VRMSF and Error vs. RF Input and Temperature at 1 GHz, Error Calculated Using Linear Regression of Data Between +30 dBm and -15 dBm, TADJS = 0 V, TADJI = 0 V, 0.1 F Across CHPF+, CHPF- Rev. B | Page 12 of 26 Data Sheet ADL5920 3.0 2 3.0 1 2.5 -20 1.5 -1 -2 1.0 -2 -3 0.5 -3 -1 10 0 -10 20 -4 30 0 -30 RF INPUT (dBm) Figure 15. VRMSF and Error vs. RF Input and Temperature at 2 GHz, Error Calculated Using Linear Regression of Data Between +25 dBm and -15 dBm, TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF- Open -10 3.00 2.50 2 2.25 1.5 1.0 +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 0 -1 -2 -30 -20 -10 0 10 20 -4 30 RF INPUT (dBm) Figure 16. VRMSF and Error vs. RF Input and Temperature at 3 GHz, Error Calculated Using Linear Regression of Data Between +25 dBm and -15 dBm, TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF- Open +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 5 4 3 2 1 1.50 0 1.25 -1 1.00 -2 0.75 -3 0.50 -4 0.25 -5 2.5 -10 2.50 2 2.25 2.00 0 -1 1.5 -2 1.0 20 -6 30 6 +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 3 2.0 10 RF INPUT (dBm) 2.75 1 0 Figure 19. VRMSF and Error vs. RF Input Level and Temperature at 6 GHz, Error Calculated Using Linear Regression of Data Between 20 dBm and -5 dBm, TADJS = 0 V, TADJI = 0.2 V, CHPF+/CHPF- Open VRMSF (V) 3.0 -20 3.00 ERROR (dB) 3.5 5 4 3 2 1.75 1 1.50 0 1.25 -1 1.00 -2 0.75 -3 0.50 -4 0.25 -5 -3 0.5 -20 -10 0 10 20 -4 30 0 -30 16085-018 VRMSF (V) 6 1.75 0 -30 4 4.0 0 -30 -4 30 -3 0.5 0 -40 VRMSF (V) 2.0 ERROR (dB) 1 16085-017 VRMSF (V) 2.00 2.5 20 +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR 3 3.0 10 RF INPUT (dBm) 2.75 3.5 0 Figure 18. VRMSF and Error vs. RF Input Level and Temperature at 5 GHz, Error Calculated Using Linear Regression of Data Between 15 dBm and -10 dBm, TADJS = 0.2 V, TADJI = 0.2 V, CHPF+/CHPF- Open 4 4.0 -20 ERROR (dB) -30 0 16085-020 0 -40 1 2.0 0 0.5 2 ERROR (dB) 1.0 3 RF INPUT (dBm) Figure 17. VRMSF and Error vs. RF Input Level and Temperature at 4 GHz, Error Calculated Using Linear Regression of Data Between +20 dBm and -15 dBm, TADJS = 0.2 V, TADJI = 0 V, CHPF+/CHPF- Open -20 -10 0 10 20 -6 30 RF INPUT (dBm) Figure 20. VRMSF and Error vs. RF Input and Temperature at 7 GHz, Error Calculated Using Linear Regression of Data Between 20 dBm and 0 dBm, TADJS = 0.8 V, TADJI = 0.2 V, CHPF+/CHPF- Open Rev. B | Page 13 of 26 16085-021 1.5 VRMSF (V) 2.0 +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR +85C VRMSF +70C VRMSF +25C VRMSF -40C VRMSF +85C ERROR +70C ERROR +25C ERROR -40C ERROR ERROR (dB) 3.5 ERROR (dB) 3 16085-016 VRMSF (V) 3.5 2.5 4 4.0 16085-019 4 4.0 ADL5920 Data Sheet 14 22 20 12 +85C 18 +85C +25C +25C 16 10 -40C -40C COUNT COUNT 14 12 10 8 6 8 4 6 4 2 2 2.85 2.90 2.95 3.00 3.05 3.10 0 VRMSF (V) 2.10 2.20 2.25 2.30 2.35 2.40 2.45 2.50 VRMSF Figure 21. Distribution of VRMSF, PIN = 20 dBm, 1 GHz Figure 24. Distribution of VRMSF, PIN = 20 dBm, 6 GHz 14 18 16 12 +85C 14 +85C +25C +25C 10 -40C COUNT 12 COUNT 2.15 16085-025 2.80 16085-022 0 10 8 -40C 8 6 6 4 4 2 2 16085-026 0.85 0.80 0.75 VRMSF (V) Figure 25. Distribution of VRMSF, PIN = -10 dBm, 6 GHz 16 7 14 6 12 5 10 COUNT 8 4 8 3 6 2 4 1 2 0 56.50 56.75 57.00 57.25 57.50 57.75 58.00 SLOPE (mV/dB) 58.25 16085-030 COUNT Figure 22. Distribution of VRMSF, PIN = -20 dBm, 1 GHz Figure 23. Distribution of Slope at 6 GHz 0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 SLOPE (mV/dB) Figure 26. Distribution of Slope at 1 GHz Rev. B | Page 14 of 26 63.0 16085-027 VRMSF (V) 0.70 0 0.65 0.80 0.60 0.75 0.55 0.70 0.50 0.65 0.45 0.60 0.40 0.55 0.35 0.50 0.30 0.45 16085-023 0 Data Sheet ADL5920 20 18 18 16 16 14 14 12 COUNT COUNT 12 10 10 8 8 6 6 4 4 2 2 -30 -29 -28 -27 -26 -25 -26 0 INTERCEPT (dBm) -25 -22 -21 -20 -19 -18 -17 -16 Figure 30. Distribution of Intercept at 6 GHz 6.0 5.5 5.5 4.5 VRMSF OUTPUT VOLTAGE (V) +15dBm +10dBm 0dBm -10dBm RF ENABLE PULSE 5.0 4.0 3.5 3.0 2.5 2.0 1.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 TIME (ms) 0 16085-029 0 +15dBm +10dBm 0dBm -10dBm RF ENABLE PULSE 5.0 0 40 80 120 160 200 240 280 320 360 400 TIME (s) Figure 28. VRMSF Response to Various RF Input Burst Levels, Carrier Frequency = 1 GHz, CRMSF = 0.1 F 16085-033 6.0 Figure 31. VRMSF Response to Various RF Input Burst Levels, Carrier Frequency = 1 GHz, CRMSF = 0.01 F 6.0 6.0 5.5 5.5 4.5 VRMSF OUTPUT VOLTAGE (V) +20dBm +10dBm 0dBm -10dBm PWDN/TADJS 5.0 4.0 3.5 3.0 2.5 2.0 1.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0 0.4 0.8 1.2 1.6 2.0 2.4 TIME (ms) 2.8 3.2 3.6 4.0 0 16085-032 0 Figure 29. VRMSF Response to PWDN/TADJS for Various RF Input Levels, Carrier Frequency = 1 GHz, CRMSF = 0.1 F +20dBm +10dBm 0dBm -10dBm PWDN/TADJS 5.0 0 0.04 0.08 0.12 0.16 0.20 0.24 TIME (ms) 0.28 0.32 0.36 0.40 16085-036 VRMS OUTPUT VOLTAGE (V) -23 INTERCEPT (dBm) Figure 27. Distribution of Intercept at 1 GHz VRMS OUTPUT VOLTAGE (V) -24 16085-031 -31 16085-028 0 Figure 32. VRMSF Response to PWDN/TADJS for Various RF Input Levels, Carrier Frequency = 1 GHz, CRMSF = 0.01 F Rev. B | Page 15 of 26 ADL5920 Data Sheet 0.22 0.20 SUPPLY CURRENT (A) 10 1 1.30 1.35 1.40 1.45 0.14 0.10 -60 16085-034 1.25 0.16 0.12 VPWDN/TADJS INCREASING VPWDN/TADJS DECREASING 0 1.20 0.18 1.50 VPWDN/TADJS (V) -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) Figure 36. Supply Current vs. Temperature Figure 33. Supply Current vs. PWDN/TADJS Voltage (VPWDN/TADJS) 60 50 50 40 40 30 COUNT COUNT -40 16085-038 SUPPLY CURRENT (mA) 100 30 20 20 1.29 1.32 1.38 1.35 1.41 1.44 1.50 1.47 0 2.44 16085-035 0 1.26 VTEMP (V) 3 1.6 2 1.5 1 1.4 0 1.3 -1 1.2 -2 1.1 -3 1.0 -4 0.9 -50 -40 -30 -20 -10 -5 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) LINEARITY ERROR (C) 4 VTEMP ERROR (C) 16085-037 VTEMP (V) 1.7 2.50 2.52 Figure 37. Distribution of VREF Voltage 5 1.8 2.48 VREF (V) Figure 34. Distribution of VTEMP Voltage at TA = 25C, No RF Input 1.9 2.46 Figure 35. VTEMP and Linearity Error vs. Temperature Rev. B | Page 16 of 26 2.54 16085-024 10 Data Sheet ADL5920 THEORY OF OPERATION The ADL5920 contains a symmetric and bidirectional resistive bridge plus two identical rms detectors that provide both forward and reverse power indications at the VRMSF and VRMSR pins, respectively. A detailed description of the theory of operation can be found in the Analog Dialogue article, An Integrated Bidirectional Bridge with Dual RMS Detectors for RF Power and Return Loss Measurement. The device provides return loss and VSWR indication at the VDIFF+ and VDIFF- outputs, where VDIFF = (VDIFF+) - (VDIFF-) = VRMSF - VRMSR (1) The bridge has an insertion loss (IL) of 0.9 dB below about 1 GHz when the source and load impedances are 50 (the ADL5920 is only intended to be used in 50 systems). The insertion loss increases with increasing frequency to 1.9 dB at 6 GHz. Note that insertion loss in dB is IL = -20log10|S21| = -20log10|VRFOUT/VRFIN| (2) where: VRFOUT is the RFOUT voltage. VRFIN is the RFIN voltage. As the source or load impedance deviates from 50 , the VRMSF and VRMSR outputs indicate this deviation via a reduction in the separation of these two voltages. For example, with a fixed signal level applied to the RFIN port, as the load resistance on the RFOUT port varies from a short-circuit condition to an open circuit condition, only the VRMSR signal changes. The VRMSF output stays constant. The voltage difference indicates the return loss and reflection coefficient of the load and indicates the directivity of the structure when RLOAD = RSOURCE = 50 . The two rms detectors are architecturally similar to the ADL5906 but are internally dc-coupled to operate down to dc. The detectors provide linear in dB outputs and thereby give a direct indication in dBm of the applied forward and reverse signals. Due to their linear in dB response, the output voltages represent the coupled and isolated port voltages in dB and thereby their difference directly indicates directivity or return loss, which is an advantage over simple diode detectors that produce a linear in volt output. The detector slope of each detector output voltage vs. PIN is approximately 60 mV/dB. Because both detectors are identical, the difference in output voltage with a perfectly matched source and load (50 RSOURCE and RLOAD) is the directivity of the bidirectional bridge and is calculated as follows: Directivity = ((VRMSF - VRMSR)/Slope) (dB) (3) Directivity is defined as follows: Directivity (dB) = Coupling (dB) - Isolation (dB) = 20log10(C/I) (4) Where the isolation (I) and coupling (C) factors are positive numbers, and isolation is a smaller value than C. In the default, single-supply and ac-coupled connection (see Figure 38), the ADL5920 device directivity is greater than 30 dB for frequencies below 400 MHz, as shown in Figure 5, which shows as a constant difference voltage for the largest input powers. When the signal is applied to the RFIN port (by definition in the forward direction), the resulting VDIFF, VRMSF - VRMSR, is approximately constant at frequencies less than 100 MHz. However, as the input signal level reduces, eventually, the rejected side limits at the noise and offset floor, and the VRMSR output stays constant while the VRMSF output keeps decreasing until this output also reaches the noise and offset floor. To determine the inherent directivity of the ADL5920 measurement system, apply a large enough input signal level to reliably determine the isolated port voltage, which is best achieved through a PIN sweep of around 100 MHz. Rev. B | Page 17 of 26 ADL5920 Data Sheet APPLICATIONS INFORMATION BASIC CONNECTIONS frequency. For example, for a minimum input frequency of 1 MHz, the high-pass corner frequency must be set to 1 kHz to ensure that the offset compensation loop does not interfere with the input signal being measured. For ac-coupled operation, the ADL5920 requires a single supply of 5 V. The supply is connected to the VPOS1, VPOS2, and VPOS3 supply pins. Decouple each of these pins using two capacitors with values equal or similar to those shown in Figure 38. Place these capacitors as close as possible to the VPOS pins. Capacitors connected between CHPF+ and CHPF- and between CHPR+ and CHPR- can reduce the corner frequency (f3dB) of the offset compensation loops for each detector. The following equation sets the corner frequency of the offset compensation loop: The RF input and output pins are ac-coupled using broadband 0.01 F capacitors, which allow operation down to approximately 600 kHz. Larger value capacitors can reduce the minimum input frequency further. f3dB = 1/(2 x 2000 x (190 pF + CHPx)) For example, setting the CHPx capacitors values to 0.1 F results in a high-pass corner of approximately 800 Hz, ensuring reliable operation for input frequencies down to 800 kHz. CHPR AND CHPF CAPACITORS Each rms detector contains an offset compensation loop that eliminates internal offset voltages and ensures optimal detector sensitivity. The offset compensation loop works like a high-pass filter so that all input frequencies (and dc) below a certain corner frequency are nulled by the servo action of the loop. An internal 190 pF capacitor and an internal 2 k resistor sets the nominal corner frequency of this loop. This configuration results in a high-pass corner frequency of approximately 400 kHz. For operation at a specific input frequency, the high-pass corner must be set two to three decades lower than this corner GND6 EPAD RFIN C2 31 At input frequencies above 2 GHz, the presence of capacitors or stray capacitance on the CHPx nodes adversely affects directivity. As a result, it is recommended to leave these nodes open with no stray capacitance present for operation from 2 GHz to 7 GHz. For broadband operation (for example, from 1 MHz to 7 GHz), it is recommended to use 0201 size capacitors and to mount the capacitors as close the pins as possible. GND4 29 28 GND3 27 GND2 24 GND1 1 ADL5920 26 C19 RFOUT BIDIRECTIONAL BRIDGE 32 0.01F 0.01F VNEG1 CHPR+ C7 (SEE TEXT) CHPR- C8 CRMSR 2 23 3 21 4 REVERSE PATH RMS DETECTOR 9 0.1F VREV VRMSR 22 FORWARD PATH RMS DETECTOR 16 18 12 VREF 10 TEMPERATURE SENSOR 1.4V x1 VREF 2.5V 19 15 PWDN/TADJS VNEG2 CHPF+ CRMSF 20 5 VPOS1 13 VPOS2 11 VDIFF- 14 DECL VOCM VFWD C10 4.7F 1k VOCM R1 VREF 3.6k VTGT TADJI VREF VTGT R2 2.43k R9 (SEE TEXT) 17 VDIFF+ C12 VRMSF R2 (SEE TEXT) 8 C13 (SEE TEXT) CHPF- 0.1F 7 VTEMP 6 R1 (SEE TEXT) RFOP 25 VPOS3 R10 (SEE TEXT) 5V C1 0.1F C6 C9 100pF 0.1F C11 100pF C18 0.1F C14 100pF VDIFF OUTPUT Figure 38. Basic Connections for Single-Supply AC-Coupled Operation Rev. B | Page 18 of 26 16085-039 RFIP GND5 30 (5) Data Sheet ADL5920 VREF INTERFACE TEMPERATURE DRIFT COMPENSATION The VREF pin provides an internally generated voltage reference for the user. The VREF voltage is temperature stable and is capable of sourcing 4 mA and sinking 50 A maximum. To provide additional current sink capability, connect an external resistor from VREF to GNDx. The voltage on this pin can drive the PWDN/TADJS, TADJI, VTGT, and VOCM pins. The TADJI and TADJS pins provide the option to optimize the temperature drift of the output voltages of ADL5920. The voltage on TADJI provides compensation of intercept temperature drift and the voltage on TADJS compensates for temperature drift of the slope. VPOSx INTERNAL VOLTAGE Table 5. Recommended VTADJI and VTADJS Values for Selected Frequencies VREF 16085-040 18k GNDx Figure 39. VREF Interface Simplified Schematic VDIFF OUTPUT INTERFACE The ADL5920 contains a differential output stage (see Figure 40) that converts the detector output voltages of VRMSF and VRMSR to a differential voltage (VDIFF+ - VDIFF-) with two differential amplifiers that each have a gain of one half. The differential gain from VRMSF minus VRMSR to VDIFF+ - VDIFF- is therefore equal to one, that is, VDIFF+ - VDIFF- = VRMSF - VRMSR (6) The VOCM pin sets the output common-mode voltage of VDIFF. Because the difference voltage can be as large as 2 V to 2.5 V depending on directivity and frequency, VOCM must be high enough (at least 1.25 V for |VRMSF - VRMSR| = 2.5 V) such that the negative swinging output voltage is not limited at ground. A voltage of midsupply (2.5 V) is optimal for VOCM. The VOCM pin must be driven by a low impedance because the current flowing in and out of this pin can be up to 2 mA, depending on the voltage applied to the VOCM pin and the voltages present on VRMSF and VRMSR. VOCM can connect directly to VREF. However, the connection must include a 1 k resistor to ground, as shown in Figure 38. VRMSF 2k 2k 2k 1k 1k 1k VOCM VDIFF+ Frequency (GHz) 0.01 0.1 1 2 3 4 5 6 7 VTADJI (V) 0 0 0 0 0 0 0.2 0.2 0.2 VTADJS (V) 0 0 0 0.2 0.2 0.2 0.2 0 0.8 The TADI and TADJS pins have a high input impedance and can be conveniently driven from an external source or from an attenuated value of VREF using a resistor divider. SETTING VTGT The voltage on the VTGT pin determines the settling point of internal automatic level control (ALC) loops that are part of the rms computation core. The recommended value for VTGT is 1 V, which represents a compromise between achieving excellent rms accuracy and maximizing dynamic range. The voltage on VTGT can be derived from the VREF pin using a resistor divider, as shown in Figure 38. Like the resistors chosen to set the voltage on TADJI and TADJS, the resistors setting VTGT must have reasonable values that do not pull too much current from VREF or cause bias current errors. In addition, note the combined current that VREF must deliver to generate the voltages on TADJI, TADJS and VTGT (which cannot exceed 4 mA). 16085-041 VRMSR VDIFF- Table 5 shows the recommended voltages for VTADJI and VTADJS to minimize temperature drift over the intended temperature range (-40C < TA < +85C). Figure 40. Differential Output Stage Rev. B | Page 19 of 26 ADL5920 Data Sheet CHOOSING VALUES FOR CRMSF AND CRMSR CRMSF and CRMSR provide the averaging function for the rms computation in the forward path and reverse path rms detectors, respectively. Using the minimum value for these capacitances allows the quickest response time to a pulsed waveform but leaves significant output noise on the output voltage signal, especially with input signals that are modulated. Similarly, a large filter capacitor reduces output noise at the expense of response time. In applications where response time is not critical, place a relatively large capacitor on the CRMSF and CRMSR pins. In Figure 38, a 0.1 F capacitor was used on these pins. For most signal modulation schemes, this value ensures excellent rms measurement compliance and low residual output noise. There is no maximum capacitance limit for CRMSF and CRMSR. Figure 41 shows how output noise varies with CRMSF when the ADL5920 is driven by a single-carrier W-CDMA signal (Test Model TM1-64, peak envelope power = 10.56 dB, bandwidth = 3.84 MHz). The response for the reverse path is identical. OUTPUT NOISE (mV p-p) 300 1000000 100000 250 10000 200 1000 150 100 100 10 50 1 0 1 10 100 1000 0.1 10000 CRMS (nF) RISE TIME/FALL TIME (s) OUTPUT NOISE (mV p-p) RISE TIME (s) FALL TIME (s) Table 6 shows the recommended minimum values of CRMSF and CRMSR for popular modulation schemes. Using lower capacitor values results in rms measurement errors. Output response time is also shown. If the output noise shown in Table 6 is too high, increase the CRMSF and CRMSR values to reduce the noise. However, increasing the CRMSF and CRMSR values results in slower rise and fall times. The values in Table 6 are experimentally determined as the minimum capacitance that ensures achieving the specified rms accuracy for that particular signal type. This test is carried out by starting out with a large capacitance value on the CRMSF pin (for example, 10 F). The VRMSF value is noted for a fixed input power level (for example, 10 dBm). The CRMSF value is then progressively reduced (with press down capacitors) until the value of VRMSF starts to deviate from its original value. This deviation indicates that the accuracy of the rms computation is degrading and that CRMSF is becoming too small). In general, the minimum required rms averaging capacitance increases as the peak to average ratio of the carrier increases. The minimum required CRMSF and CRMSR values also tend to increase as the bandwidth of the carrier decreases. With narrow-band carriers, the noise spectrum of the VRMSF and VRMSR outputs tend to have a correspondingly narrow profile. The relatively narrow spectral profile demands larger CRMSF and CRMSR values to reduce the low-pass corner frequency of the averaging function and to ensure a valid rms computation. 16085-042 350 Figure 41 also shows how the response time is affected by the value of CRMSF and CRMSR. To measure this response time, an RF burst at 2.14 GHz at 0 dBm is applied to the ADL5920. The 10% to 90% rise time and 90% to 10% fall time are then measured. Figure 41. Output Noise, Rise and Fall Times vs. CRMS Capacitance, Single-Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm Table 6. Recommended Minimum Capacitor Values on CRMSF and CRMSR for Various Modulation Schemes Modulation/Standard QPSK, 5 MSPS (SQR COS Filter, = 0.35) QPSK ,15 MSPS (SQR COS Filter, = 0.35) 64 QAM, 1 MSPS (SQR COS Filter, = 0.35) 64 QAM, 5 MSPS (SQR COS Filter, = 0.35) 64 QAM, 13 MSPS (SQR COS Filter, = 0.35) W-CDMA, One Carrier, TM1-64 W-CDMA Four Carrier, TM1-64, TM1-32, TM1-16, TM1-8 LTE, TM1, One Carrier, 20 MHz (2048 QPSK Subcarriers) Peak Envelope Power Ratio (dB) 3.8 3.8 7.4 7.4 7.4 10.56 12.08 11.58 Carrier Bandwidth (MHz) 5 15 1 5 13 3.84 18.84 20 Rev. B | Page 20 of 26 CRMSF and CRMSR (nF) 1 1 10 1 1 1 1 1 Output Noise (mV p-p) 84 42 265 380 205 820 640 140 Rise/Fall Time (s) 0.2/10 0.2/10 3/85 0.2/10 0.2/10 0.2/10 0.2/10 0.2/10 Data Sheet ADL5920 RF POWER AND RETURN LOSS CALCULATION Figure 42 shows the voltage measured on VRMSF and VRMSR when RFIN is swept across its power range at various frequencies with a 50 termination on RFOUT. The VRMSR output ideally only responds to power reflected from the load. However, because of the finite directivity of the bridge circuit of the ADL5920, the VRMSR voltage starts to increase as the RF power at RFIN increases. Thereafter, the VRMSR voltage follows a similar linear in dB response as VRMSF, although at a much lower level. At a particular frequency, the difference in output voltage between VRMSF and VRMSR, where both voltages are following this linear in dB characteristic, is proportional to the directivity in dB of the bridge circuit when the load is 50 . As frequency increases, the vertical difference between the VRMSF and VRMSR traces decreases, indicating a decrease in directivity. 3.5 3.0 2.5 2.0 5GHz VRMSF 3GHz VRMSF 7GHz VRMSF 1GHz VRMSF 10MHz VRMSF 5GHz VRMSR 3GHz VRMSR 7GHz VRMSR 1GHz VRMSR 10MHz VRMSR 1.0 0.5 -30 -20 In general, calibration is performed by applying two or more known signal levels (PIN1 and PIN2 in this case) to the input of the ADL5920 and measuring the corresponding output voltages (VRMSF1 and VRMSF2). The calibration points must be within the linear operating range of the device. With a two-point calibration, calculate the slope and intercept as follows: Slope = (VRMSF1 - VRMSF2)/(PRFIN1 - PRFIN2) Intercept = PRFIN1 - (VRMSF1/Slope) -10 0 10 20 30 RF INPUT (dBm) (10) After the slope and intercept are calculated and stored in nonvolatile memory during equipment calibration, use the following equation to calculate the unknown input power based on the output voltage of the detector: Figure 42. VRMSF, VRMSR Output Voltage vs. RF Input at Various Frequencies When Bridge Driven from RFIN and RFOUT Terminated with 50 (11) PFWD (dBm) = (VRMSF/Slope) + Intercept (12) PREV (dBm) = (VRMSR/Slope) + Intercept (13) Return Loss (dB) = (PFWD - PREV) + Insertion Loss (dB) (14) Use the following equation to calculate the idealized output voltage on VRMSF (VRMSF(IDEAL)): Note that insertion loss has a negative sign for a passive load. VRMSF(IDEAL) = Slope x (PINF - Intercept) (7) where: Slope is the change in output voltage divided by the dB change in input power. PINF is the power level in dBm applied to the RFIN pin. Intercept is the calculated input power level (in dBm) at which the output voltage is equal to 0 V. Note that Intercept is an extrapolated theoretical value, not a measured value. Return loss can also be calculated by using the VDIFF+ and VDIFF- differential outputs. Return Loss (dB) = (VDIFF+ - VDIFF-)/Slope + Insertion Loss (dB) (15) To calculate the directivity of the bridge circuit, place a 50 load on RFOUT and measure VDIFF+ and VDIFF-. Directivity in dB is then given by the following equation: The equation for VRMSR(IDEAL) is similar with the exception that PINR substitutes in for PINF. VRMSR(IDEAL) = Slope x (PINR - Intercept) (9) Perform a separate calibration to establish the slope and intercept of the reverse path. Alternatively, because the forward and reverse path bridge circuits and rms detectors are matched closely, use the slope and intercept from the forward path calibration to convert the VRMSR voltage to the equivalent dBm RF power. Using this methodology, use the following equations to calculate forward power (PFWD), reverse power (PREV), and return loss. 1.5 0 -40 Because slope and intercept vary from device to device and vs. frequency, calibration must be performed to achieve high accuracy. PRFIN (Unknown) = (VRMSF(MEASURED)/Slope) + Intercept 16085-043 VRMSF, VRMSR OUTPUT VOLTAGE (V) 4.0 Where PINR is the power level in dBm applied to the RFOUT pin with the RFIN pin terminated with 50 . (8) Rev. B | Page 21 of 26 Directivity (dB) = (VDIFF+ - VDIFF-)/Slope (16) ADL5920 Data Sheet DC-COUPLED OPERATION connect capacitors to the CHPF and CHPR pins to reduce the corner frequency of the offset compensation loops as previously detailed. In addition, connect the DECL pin (Pin 12) to ground to ensure that the specified directivity is achieved at low frequencies. The ADL5920 RFIN and RFOUT pins can be dc-coupled as shown in Figure 43. However, to drive the inputs with signals that are biased at 0 V, apply a negative supply of -2.5 V to the two VNEG pins as shown in Figure 43. If dc-coupled operation is required for the sake of applying low input frequencies, GND6 EPAD GND5 30 31 RFIP GND3 27 GND2 24 GND1 1 ADL5920 26 RFOUT BIDIRECTIONAL BRIDGE VNEG1 C16 100pF CHPR+ C7 1F CHPR- C8 CRMSR 2 23 3 21 4 REVERSE PATH RMS DETECTOR 9 0.1F VRMSR 22 FORWARD PATH RMS DETECTOR 16 7 6 18 10 TEMPERATURE SENSOR 1.4V x1 VREF 2.5V 19 15 PWDN/TADJS 55 20 8 VPOS1 13 VPOS2 11 VDIFF- 14 -2.5V VNEG2 C15 0.1F C13 1F CHPF+ CHPF- CRMSF C17 100pF C12 0.1F 12 VTEMP RFOP 25 VRMSF VFWD DECL 1k VOCM VOCM VREF VTGT R1 3.6k VTGT TADJI 17 VDIFF+ VPOS3 +5V C1 0.1F C9 C6 100pF 0.1F C11 100pF C18 0.1F C14 100pF VDIFF OUTPUT Figure 43. Basic Connections for DC-Coupled Operation Rev. B | Page 22 of 26 16085-044 -2.5V VREV 28 RFIN 32 C5 0.1F GND4 29 Data Sheet ADL5920 EVALUATION BOARD with the load on RFIN). The output voltages are available on the VRMSR, VRMSF, VDIFF+, and VDIFF- SMA connectors or on the adjacent test loops. Configuration options for the evaluation board are listed in Table 7. Note that an Arduino/ Linduino based evaluation platform for the ADL5920 is also available (Part Number DC2847A-Kit). For more information, go to www.analog.com/ADL5920. The ADL5920-EVALZ is a fully populated, 4-layer, FR4-based evaluation board. For normal operation, the board requires a 5 V, 200 mA power supply. The 5 V power supply must be connected to the VPOS and GND test loops. The RF input and load must be applied to the RFIN and RFOUT 2.92 mm connectors, respectively (because the ADL5920 is fully bidirectional, the input signal can also be applied to RFOUT GND1 GND2 J1 C20 C21 0.01F 0.01F J2 GND GND RFIN GND C2 C19 RFOUT VRSMR VNEG GND GND S1 3 GND 1 R3 0 GND GND C7 0.1F R1 0 DNI VREF 1 2 3 4 5 6 7 8 R2 100 GND VRMSR GND VRMS_R GND C1 0.1F C6 100pF GND GND GND1 VNEG1 ADL5920 CHPR+ CHPR- PWDN/TADJS VTEMP VRMSR VPOS1 GND2 VNEG2 CHPF- CHPF+ TADJI VREF VRMSF VPOS3 VOCM VOCM R5 1k C9 0.1F C11 100pF GND GND C13 0.1F VREF VRSMF R9 0 DNI VREF GND TADJI R10 100 GND C14 100pF C18 0.1F GND GND VNEG GND VRMSF 543 2 VRMS_F GND C12 0.1F GND GND GND VDIFF- GND VPOS VTGT 24 23 22 21 20 19 18 C10 4.7F VREF VDIFFN GND VTEMP VDIFF- C8 0.1F GND R4 0 C15 0.1F VDIFF+ 9 10 11 12 13 14 15 16 2345 R8 0 PAD 32 31 30 29 28 27 26 25 2 VTEMP EPAD RFIN RFIN GND6 GND5 GND4 GND3 RFOUT RFOUT C5 0.1F CRMSR VOCM VDIFF- DECL VPOS2 VDIFF+ VTGT CRMSF VPOS P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TADJS 0.01F 0.01F VREF VTGT R6 3.6k R7 2.43k 2 3 4 5 VDIFF+ GND VDIFFP 2345 16085-045 GND GND Figure 44. Evaluation Board Schematic Rev. B | Page 23 of 26 Data Sheet 16085-046 ADL5920 Figure 45. Evaluation Board Layout, Component Side Table 7. Evaluation Board Configuration and Operation Component VPOS, GND1, GND2, C1, C6, C9, C11, C14, C18 RFIN, RFOUT, C2, C19 J1, J2, C20, C21 Function Description/Comments Power supply interface and decoupling. Apply a 5 V power supply from the evaluation board to the VPOS and GND1/GND2 test loops (GND1 and GND2 are connected to a common ground). The nominal supply decoupling on the VPOS1, VPOS2, and VPOS3 pins consist of a 100 pF capacitor and a 0.1 F capacitor on each power supply pin, with the 100 pF capacitor placed closer to the pin. RF inputs and outputs to bridge circuit. The main signal path is ac-coupled by 0.01 F, 0201 capacitors, setting the input corner frequency to approximately 600 kHz. For operation at lower frequencies, larger capacitor values can be installed. The RFIN and RFOUT connectors are interchangeable, allowing the source signal driven into RFOUT with the load connected to RFIN. The RFIN and RFOUT connectors are 2.92 mm. Take care when attaching to these connectors because of mechanical fragility. Calibration path. This path can calibrate out the insertion loss of the RFIN and RFOUT traces. This signal path is ac-coupled by 0.01 F, 0201 capacitors. The J1 and J2 connectors are 2.92 mm. Take care when connecting to these connectors because of mechanical fragility. Rev. B | Page 24 of 26 Default Value VPOS = 5 V, GND1 = GND2 = 0 V, C1, C9, C18 = 0.1 F (0402), C6, C11, C14 = 100 pF (0402) C2 = C19 = 0.01 F (0201), RFIN, RFOUT = 2.92 mm end launch connector C20 = C21 = 0.01 F (0201), J1, J2 = 2.92 mm end launch connector Data Sheet Component VNEG, C5, C15, R3, R8, C10 R6, R7 C7, C13 S1, R1, R2, PWDN/TADJS VTEMP VRMSF, RMSR, VRMS_F, RMS_R C8, C12 VOCM, R4, R5 VDIFF+, VDIFF-, VDIFFN, VDIFFP R9, R10, TADJI P1 ADL5920 Function Description/Comments Negative supply. The main signal path from RFIN and RFOUT can be dc-coupled by connecting a -2.5 V supply to the VNEG test loop and replacing ac coupling capacitors, C2 and C19, with 0 resistors. R3 and R8 must be removed and replaced with 100 pF capacitors pins. Connect the DECL pin to ground by removing C10 and replacing it with a 0 resistor. In this mode, the voltage on VPOS must remain at 5 V. VTGT interface. R7 and R6 are driven from VREF (2.5 V) and provide 1 V to VTGT. If R6 and R7 are removed, an external voltage can be applied on the VTGT test point. RMS detector offset compensation loop. The capacitances on these pins set the corner frequency of internal offset compensation loops of the two rms detectors. These loops limit the minimum input frequency that can be sensed by the ADL5920. The default values for these capacitors set minimum input frequencies that are well below the frequency corner set by the ac-coupling capacitors in the main signal path. These capacitors are deliberately located as close as possible to Pin 3 and Pin 4 and Pin 21 and Pin 22. To achieve the specified directivity when operating above 2 GHz, remove these capacitors (see Figure 5). Device enable and slope temperature compensation. S1 is used to disable the ADL5920 by connecting the PWDN/TADJS pin to VPOS. In its other position, S1 is open and the voltage on PWDN/TADJS is set by VREF (2.5 V) and the R1, R2 resistor divider. This voltage is used to fine tune the temperature stability of the slope of the rms detectors. Temperature sensor output. This yellow test loop is connected directly to Pin 6 of the ADL5920 (VTEMP). Reverse and forward rms voltage measurement. The voltages on these connectors are proportional to the dB power of the forward and reverse signals in the bridge circuit. RMS averaging capacitors. The value of the rms averaging capacitor must be set based on the peak to average ratio of the input signal and based on the desired output response time and residual output noise on the rms detector outputs. Common-mode voltage for VDIFF+ and VDIFF-. The voltage on VOCM pin (Pin 10) sets the common-mode level for the VDIFF+ and VDIFF- differential pair. The nominal voltage on this pin must be 2.5 V. This input requires a bias current of 1 mA and must be driven from a low impedance source. The nominal biasing method for VOCM is to connect it to VREF and connecting a 1 k resistor from VOCM to ground. An external voltage can be applied VOCM through Pin 8 of the P1 connector. Return loss measurement. The output voltage from this differential pair is proportion to the ratio of the forward and reverse power in the bridge circuit. The common-mode level is set by the voltage on VOCM. TADJI interface. R9 and R10 set the voltage on the TADJI pin that is derived from VREF. This voltage is used to fine tune the temperature stability of the Intercept of the rms detectors. P1 header. The P1 header can access all of the dc levels on the evaluation board. Rev. B | Page 25 of 26 Default Value VNEG = 0 V, R3 = R8 = 0 (0603), C15 = C5 = 0.1 F (0402), C10 = 4.7 F (0402) R7 = 2.43 k, R6 = 3.6 k, VTGT = 1 V C7, C13 = 0.1 F (0201) S1 = open position, R1 = 0 DNI, R2 = 100 , PWDN/TADJS = 0 V Not applicable VRMSF, VRMSR = SMA end launch connector, VRMS_F, VRMS_R = yellow test loops C8 = C12 = 0.1 F (0402) R4 = 0 (0402), R5 = 1 k (0402), VOCM = 2.5 V VDIFF+, VDIFF- = SMA end launch connector, VDIFFN, VDIFFP = yellow test loops R9 = 0 DNI, R10 = 100 (0402), TADJI = 0 V Not applicable ADL5920 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 25 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 32 24 1 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-003898 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 9 16 BOTTOM VIEW 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD 09-12-2018-A PIN 1 INDICATOR AREA 5.10 5.00 SQ 4.90 Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5920ACPZ ADL5920ACPZ-R2 ADL5920ACPZ-R7 ADL5920-EVALZ DC2847A-Kit 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board with Voltage Outputs ADL5920 Linduino Demo Kit Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16085-0-12/19(B) Rev. B | Page 26 of 26 Package Option CP-32-7 CP-32-7 CP-32-7 Ordering Quantity 490 250 1500