1. General description
The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optim ized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1413D is accurate enough to
guarantee zer o missing codes over the entire oper ating range. Supplied from a 3 V sou rce
for analog and a 1.8 V source for the output driver , it embeds two serial outpu ts. Each lane
is differential and complies with the JESD204A standard. An integrated Serial Peripheral
Interface (SPI) allows the user to easily configure the ADCs. A set of IC configurations is
also available via the binary level control pins taken, which are used at power-u p. The
device also includes a programmable full-sca le SPI to allow a flexible input voltage range
of 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1413D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
ADC1413D series
Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 6 — 8 June 2011 Product data sheet
SNR, 72 dBFS; SFDR, 86 dBc Input bandwidth, 600 MHz
Sample rate up to 125 Msps Power dissipation, 995 mW at 80 Msps
Clock input divided by 2 for less jitter
contribution
SPI register programming
3 V, 1.8 V power supplies Duty cycle stabilizer (DCS)
Flexible input voltage rang e: 1 V (p -p )
to 2 V (p-p)
High IF capability
Two configura ble ser ial ou tp uts Offset binary, two’s complement, gray
code
Compliant with JESD204A serial
transmission standar d
Power-down mode and Sleep mode
Pin compatible with the
ADC1613D series, ADC1213D series,
and ADC1113D125
HVQFN56 package
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Product data sheet Rev. 6 — 8 June 2011 2 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
3. Applications
4. Ordering information
Wireless and wired broadband
communications
Portable instrumentation
Spectral analysis Imaging systems
Ultrasound equip m en t Software defined radio
Table 1. Ordering information
Type number Sampling
frequency
(Msps)
Package
Name Description Version
ADC1413D125HN/C1 125 HVQFN56 plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 80.85 mm SOT684-7
ADC1413D105HN/C1 105 HVQFN56 plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 80.85 mm SOT684-7
ADC1413D080HN/C1 80 HVQFN56 plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 80.85 mm SOT684-7
ADC1413D065HN/C1 65 HVQFN56 plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 80.85 mm SOT684-7
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Product data sheet Rev. 6 — 8 June 2011 3 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
5. Block diagram
Fig 1. Block diagram
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
ADC A CORE
14-BIT
PIPELINED
T/H
INPUT
STAGE
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC B CORE
14-BIT
PIPELINED
T/H
INPUT
STAGE
ADC1413D
DLL
PLL
FRAME ASSEMBLY
SERIALIZER A
SPI
OUTPUT
BUFFER A
SERIALIZER B
OUTPUT
BUFFER B
SCRAMBLER A
ENCODER 8-bit/10-bit A
SCRAMBLER B
ENCODER 8-bit/10-bit B
8-bit 8-bit
INAP
INAM
CLKP
CLKM
INBP
SCRAMBLER RESET
INBM
8-bit8-bit 10-bit
10-bit
SWING_n
SWING_n
SYNCP
SCLK
CFG (0 to 3) SDIO
CS
SYNCN
CMLNB
CMLPB
CMLNA
CMLPA
OTR
D13 to D0
D13 to D0
OTR
005aaa067
REFAT
REFAB
REFBB
REFBT
VCMA
VREF
SENSE
VCMB
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Product data sheet Rev. 6 — 8 June 2011 4 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pinning diagram
005aaa068
ADC1413D
Transparent top view
DGND
INBM
INBP
DGND
VCMB VDDD
REFBT CMLPB
REFBB CMLNB
AGND VDDD
CLKM DGND
CLKP DGND
AGND VDDD
REFAB CMLNA
REFAT CMLPA
VCMA VDDD
INAM DGND
INAP DGND
VDDA
VDDA
SCLK
SDIO
CS
AGND
RESET
SCRAMBLER
CFG0
CFG1
CFG2
CFG3
VDDD
DGND
VDDA
VREF
SENSE
VDDA
AGND
AGND
VDDA
DNC
SWING_1
SWING_0
VDDD
DGND
SYNCN
SYNCP
14 29
13 30
12 31
11 32
10 33
934
835
736
637
538
439
340
241
142
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Table 2. Pin description
Symbol Pin Type[1] Description
INAP 1 I channel A analog input
INAM 2 I channel A compleme ntary analog input
VCMA 3 O channel A output common voltage
REFAT 4 O channel A top refe rence
REFAB 5 O channel A bottom reference
AGND 6 G analog ground
CLKP 7 I clock input
CLKM 8 I complementary clock input
AGND 9 G analog ground
REFBB 10 O channel B bottom reference
REFBT 11 O channel B top reference
VCMB 12 O channel B output common voltage
INBM 13 I channel B complementary analog input
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Product data sheet Rev. 6 — 8 June 2011 5 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
INBP 14 I channel B analog input
VDDA 15 P analog power supply 3 V
VDDA 16 P analog power supply 3 V
SCLK 17 I SPI clock
SDIO 18 I/O SPI data input/output
CS 19 I chip select
AGND 20 G analog ground
RESET 21 I JEDEC digital IP reset
SCRAMBLER 22 I scrambler enable and disable
CFG0 23 I/O See Table 28 (input) or OTRA (output)[2]
CFG1 24 I/O See Table 28 (input) or OTRB (output)[2]
CFG2 25 I/O See Table 28 (input)
CFG3 26 I/O See Table 28 (input)
VDDD 27 P digital power supply 1.8 V
DGND 28 G digital ground
DGND 29 G digital ground
DGND 30 G digital ground
VDDD 31 P digital power supply 1.8 V
CMLPB 32 O channel B output
CMLNB 33 O channel B complementary output
VDDD 34 P digital power supply 1.8 V
DGND 35 G digital ground
DGND 36 G digital ground
VDDD 37 P digital power supply 1.8 V
CMLNA 38 O channel A complementary output
CMLPA 39 O channel A output
VDDD 40 P digital power supply 1.8 V
DGND 41 G digital ground
DGND 42 G digital ground
SYNCP 43 I synchronization from FPGA
SYNCN 44 I synchronization from FPGA
DGND 45 G digital ground
VDDD 46 P digital power supply 1.8 V
SWING_0 47 I JESD204 serial buffer programmable output swing
SWING_1 48 I JESD204 serial buffer programmable output swing
DNC 49 O do not connect
VDDA 50 P analog power supply 3 V
AGND 51 G analog ground
AGND 52 G analog ground
Table 2. Pin description …continued
Symbol Pin Type[1] Description
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Product data sheet Rev. 6 — 8 June 2011 6 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
[2] OTRA stands for “OuT of Range A”. OTRB stands for “OuT of Range B”
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
VDDA 53 P analog power supply 3 V
SENSE 54 I reference programming pin
VREF 55 I/O voltage reference input/output
VDDA 56 P analog power supply 3 V
Table 2. Pin description …continued
Symbol Pin Type[1] Description
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA analog supply voltage 0.4 +4.6 V
VDDD digital supply voltage 0.4 +2.5 V
Tstg storage temperature 55 +125 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature - 125 C
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1] 17.8 K/W
Rth(j-c) thermal resistance from junction to case [1] 6.8 K/W
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Product data sheet Rev. 6 — 8 June 2011 7 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
9. Static characteristics
Table 5. Static characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDDA analog supply voltage 2.85 3.0 3.4 V
VDDD digital supply voltage 1.65 1.8 1.95 V
IDDA analog supply current fclk = 125 Msps;
fi=70MHz -343- mA
IDDD digital supply current fclk = 125 Msps;
fi=70MHz -150- mA
Ptot total power dissipation fclk = 125 Msps - 1270 - mW
fclk = 105 Msps - 1150 - mW
fclk =80Msps - 995 - mW
fclk =65Msps - 885 - mW
P power dissipation Powe r-down mode - 30 - mW
Standby mode - 200 - mW
Clock inputs: pins CLKP and CLKM (AC-coupl ed)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Vi(clk)dif differential clock input
voltage peak-to-peak - 1.6 - V
SINE
Vi(clk)dif differential clock input
voltage peak - 3.0 - V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
VIL LOW-level input voltage - - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA -- V
Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESET
VIL LOW-level input voltage - 0 - V
VIH HIGH-level input voltage - 0.66VDDD -V
IIL LOW-level input current 6- +6 A
IIH HIGH-level input current 30 - +30 A
SPI: pins CS, SDIO, and SCLK
VIL LOW-level input voltage 0 - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA -V
DDA V
IIL LOW-level input current 10 - +10 A
IIH HIGH-level input current 50 - +50 A
CIinput capacitance - 4 - pF
Analog inputs: pins INAP, INAM, INBP, and INBM
IIinput current track mode 5- +5 A
RIinput resistance track mode - 15 -
CIinput capacitance track mode - 5 - pF
VI(cm) common-mode input
voltage track mode 0.9 1.5 2 V
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Product data sheet Rev. 6 — 8 June 2011 8 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Biinput bandwidth - 600 - MHz
VI(dif) diff erential input voltage peak-to-peak 1 - 2 V
Voltage controlled regulator output: pins VCMA and VCMB
VO(cm) common-mode output
voltage -V
DDA /2 - V
IO(cm) common-mode output
current -4 - mA
Referenc e vo ltage input/output: pin VREF
VVREF voltage on pin VREF output 0.5 - 1 V
input 0.5 - 1 V
Data outputs: pins CMLPA, CMLNA
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 000
VOL LOW-level output
voltage DC coupled; output - 1.5 - V
AC coupled - 1.35 - V
VOH HIGH-level output
voltage DC coupled; output - 1.8 - V
AC coupled - 1.65 - V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 001
VOL LOW-level output
voltage DC coupled; output - 1.45 - V
AC coupled - 1.275 - V
VOH HIGH-level output
voltage DC coupled; output - 1.8 - V
AC coupled - 1.625 - V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 010
VOL LOW-level output
voltage DC coupled; output - 1.4 - V
AC coupled - 1.2 - V
VOH HIGH-level output
voltage DC coupled; output - 1.8 - V
AC coupled - 1.6 - V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 011
VOL LOW-level output
voltage DC coupled; output - 1.35 - V
AC coupled - 1.125 - V
VOH HIGH-level output
voltage DC coupled; output - 1.8 - V
AC coupled - 1.575 - V
Output levels, VDDD = 1.8 V; SWING_SEL[2:0] = 100
VOL LOW-level output
voltage DC coupled; output - 1.3 - V
AC coupled - 1.05 - V
VOH HIGH-level output
voltage DC coupled; output - 1.8 - V
AC coupled - 1.55 - V
Serial configuration: pins SYNCCP, SYNCCN
VIL LOW-level input voltage differential; input - 0.95 - V
VIH HIGH-level input voltage differential; input - 1.47 - V
Accuracy
INL in te gral non-linearity - 5- LSB
Table 5. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 6 — 8 June 2011 9 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
[1] Typical values measured at VDDA =3V, V
DDD = 1.8 V, Tamb =25C. Minimum and maximum values are across the full temperature
range Tamb =40 C to +85 C at VDDA =3V, V
DDD = 1.8 V; VI(INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode;
100 differential applied to serial outputs; unless otherwise specified.
DNL differential non-linearity guaranteed no missing
codes 0.95 0.5 +0.95 LSB
Eoffset offset error - 2- mV
EGgain error full-scale - 0.5 - %
MG(CTC) channel-to-channel gain
matching -1.1- %
Supply
PSRR power supply rejection
ratio 200 mV (p-p) on pi n
VDDA; fi=DC -54 - dB
Table 5. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 6 — 8 June 2011 10 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 6. Dynamic characteristics [1]
Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
2H second harmonic level fi= 3 MHz - 87 - - 87 - - 86 - - 88 - dBc
fi=30MHz -86- -86- -86--87-dBc
fi=70MHz -85- -85- -84--85-dBc
fi= 170 MHz - 82 - - 82 - - 81 - - 83 - dBc
3H third harmonic level fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz -85- -85- -85--86-dBc
fi=70MHz -84- -84- -83--84-dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
THD total harmonic distortion fi= 3 MHz - 83 - - 83 - - 82 - - 84 - dBc
fi=30MHz -82- -82- -82--83-dBc
fi=70MHz -81- -81- -80--81-dBc
fi= 170 MHz - 78 - - 78 - - 77 - - 79 - dBc
ENOB effective number of bits fi=3MHz -11.7--11.7--11.6--11.6-bits
fi= 30 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits
fi= 70 MHz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bits
fi=170MHz -11.4--11.4--11.3--11.3-bits
SNR signal-to-noise ratio fi= 3 MHz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dBFS
fi= 30 MHz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dBFS
fi= 70 MHz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dBFS
fi= 170 MHz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dBFS
SFDR spurious-fre e dy na mi c
range fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz -85- -85- -85--86-dBc
fi=70MHz -84- -84- -83--84-dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
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Product data sheet Rev. 6 — 8 June 2011 11 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
[1] Typical values measured at VDDA =3V, V
DDD =1.8V, T
amb =25C. Minimum and maximum values are across the full temperature range Tamb =40 C to +85 C at VDDA =3V,
VDDD = 1.8 V; VI(INAP, INBP) VI(INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
[1] Typical values measured at VDDA =3V, V
DDD =1.8V, T
amb =25C. Minimum and maximum values are across the full temperature range Tamb =40 C to +85 C at VDDA =3V,
VDDD = 1.8 V; VI(INAP, INBP) VI(INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
IMD intermodulation distortion fi= 3 MHz - 89 - - 89 - - 88 - - 89 - dBc
fi=30MHz -88- -88- -88--88-dBc
fi=70MHz -87- -87- -86--86-dBc
fi= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc
ct(ch) channel crosstalk fi= 70 MHz - 100 - - 100 - - 100 - - 100 - dBc
Table 6. Dynamic characteristics [1] …continued
Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 7. Clock and digi tal output characteristics[1]
Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
fclk clock frequency 45 - 65 60 - 80 75 - 105 100 - 125 Msps
tlat(data) data latency time clock cycles 307 - 850 250 - 2 83 190 - 226 160 - 170 ns
clk clock duty cycle DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 7 0 %
td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
twake wake-up time -76- -76- -76- -76-s
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Product data sheet Rev. 6 — 8 June 2011 12 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
•3.125 Gbps data rate
•Tamb =25°C
•DC coupling with two different receiver common-mode voltages
Fig 3. Eye diagram at 1 V receiver common-mode
Fig 4. Eye diagram at 2 V receiver common-mode
005aaa088
005aaa089
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Product data sheet Rev. 6 — 8 June 2011 13 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
10.4 SPI timing
[1] Typical values measured at VDDA =3V, V
DDD =1.8V, T
amb =25C. Minimum and maximum values are
across the full temperature range Tamb =40 C to +85 C at VDDA =3V, V
DDD = 1.8 V; VI(INAP,
INBP) VI(INAM,INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs;
unless otherwise specified.
Table 8. SPI timing characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
tw(SCLK) SCLK pulse width - 40 - ns
tw(SCLKH) SCLK HIGH pulse
width -16- ns
tw(SCLKL) SCLK LOW pulse
width -16- ns
tsu set-up time data to SCLKH - 5 - ns
CS to SCLKH - 5 - ns
thhold time data to SCLKH - 2 - ns
CS to SCLKH - 2 - ns
fclk(max) maximum clock
frequency -25- MHz
Fig 5. SPI timing
t
su
SDIO
SCLK
R/W W1 W0 A12 A11 D2 D1 D0
t
su
t
h
t
h
t
w(SCLK)
005aaa065
CS
t
w(SCLKL)
t
w(SCLKH)
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Product data sheet Rev. 6 — 8 June 2011 14 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1413D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) pro tection and circuit and package parasitics.
The sample phase occurs when the internal clock (der ived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Fig 6. Input sampling circuit
005aaa069
INAP
INBP
package ESD parasitics
switch
Ron = 15 Ω 4 pF
4 pF
Cs
Cs
switch
Ron = 15 Ω
INAM
INBM
1, 14
2, 13
internal
clock
internal
clock
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Product data sheet Rev. 6 — 8 June 2011 15 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11 .1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract th e effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The valu e of the ca pa citor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
11.1.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 8 would be suitable for a baseband application.
Fig 7. Anti-kickback circuit
Table 9. RC couplin g versus input frequency, typical values
Input frequency (MHz) Resistance ()Capacitance (pF)
32512
70 12 8
170 12 8
001aan679
R
R
C
INAP/
INBP
INAM/
INBM
Fig 8. Single transformer configuration
005aaa070
100 nF100 nF
100 nF
100 nF 100 nF
25 Ω
25 Ω
25 Ω
25 Ω
12 pF
ADT1-1WT
100 nF
Analog
input
INAP
INBP
INAM
INBM
VCM
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Product data sheet Rev. 6 — 8 June 2011 16 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
The configuration shown in Figure 9 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1413D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference volt age can be se t internally via SPI or with pins VREF and
SENSE (see Figure 11 to Figure 14), in 1 dB steps betwee n 0 dB and 6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21). The equivalent
reference circuit is shown in Figure 10. An external reference is also possible by providing
a voltage on pin VREF as described in Figure 13.
Fig 9. Dual transformer configuration
005aaa071
100 nF
100 nF
100 nF
100 nF
12 Ω
12 Ω
8.2 pF
50 Ω
50 Ω
50 Ω
50 Ω
ADT1-1WTADT1-1WT
Analog
input
INAP
INBP
INAM
VCM
INBM
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Product data sheet Rev. 6 — 8 June 2011 17 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 10.
Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
Fig 10. Reference equivalent schematic
Table 10. Reference modes
Mode SPI bit, “Internal
reference” SENSE pin VREF pin Full-scale
(V (p-p))
Internal (Figure 11) 0 GND 330 pF capacitor
to GND 2
Internal (Figure 12) 0 VREF pi n = SENSE pin and
330 pF capacitor to GND 1
External (Figure 13)0 V
DDA external voltage
from 0.5 V to 1 V 1 to 2
Internal, SPI mode
(Figure 14)1 VREF pin = SENSE pin and
330 pF capacitor to GND 1 to 2
EXT_ref
EXT_ref
001aan670
REFAT/
REFBT
REFAB/
REFBB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP
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Product data sheet Rev. 6 — 8 June 2011 18 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.2.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 11).
Fig 11. Internal reference, 2 V (p-p) full-scale Fig 12. Inte rnal reference, 1 V (p-p) full-scale
Fig 13. External reference, 1 V (p-p) to 2 V (p-p)
full-scale Fig 14. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa116
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa117
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1 μF
VDDA
V
005aaa119
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa118
VREF
SENSE
Table 11. Programmable full-scale
INTREF[2:0] Level (dB) Full-scale (V (p-p))
000 0 2
001 11.78
010 21.59
011 31.42
100 41.26
101 51.12
110 61
111 not used x
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Product data sheet Rev. 6 — 8 June 2011 19 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.2.3 Common-mode output voltage (VO(cm))
An 0.1 F filter capacitor should be connected between pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
11.2.4 Biasing
The common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1413D can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
1.5 V
VCMA
VCMB
0.1 μF
PACKAGE ESD PARASITICS
005aaa077
COMMON MODE
REFERENCE
ADC CORE
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock inp ut
LVCMOS
clock input CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM
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Product data sheet Rev. 6 — 8 June 2011 20 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via 5 k internal resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 17. Differential clock inpu t
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM
Vcm(clk) = common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
CLKP
CLKM
005aaa081
5 kΩ5 kΩ
V
cm(clk)
SE_SEL SE_SEL
package ESD parasitics
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Product data sheet Rev. 6 — 8 June 2011 21 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.3.4 Clock input divider
The ADC1413D cont ai ns an input clock divider that divides th e incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see Table 20). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.4 Digital outputs
11.4.1 Serial output equivalent circuit
The JESD204A standar d specifies that if the receiver and the transmitter are DC-coupled,
both must be fed from the same supply.
The output should be terminated when 100 (typical) is reached at the receiver side.
Table 12. Duty cycle stab ilizer
Bit DCS_EN Description
0 duty cycle stabilizer disable
1 duty cycle stabilizer enable
Fig 19. CML output connec ti on to the recei ve r (DC-cou pl ed )
VDDD
CMLPA/CLMPB
CMLNA/CLMNB
AGND
005aaa082
12 mA to 26 mA
100 Ω
+
RECEIVER
50 Ω
−
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Product data sheet Rev. 6 — 8 June 2011 22 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.5 JESD204A serializer
For more informa tion about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and th e number of lanes used.
Fig 20. CML output connec ti on to the recei ve r (AC-cou pl ed )
CMLPA/CMLPB
CMLNA/CMLNB
12 mA to 26 mA
100 Ω
50 Ω
10 nF
10 nF
005aaa083
VDDD
−
+
RECEIVER
Fig 21. General overview of the JESD204A serializer
FRAME
TO
OCTETS
F octets SCRAMBLER
TX transport layer
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
Mx(N'xS) bits Lx(F) octets L octets
N' = N+CS
S samples per frame cycle
samples stream to
lane stream mapping
N bits from Cr0 +
CS bits for control
N bits from CrM−1 +
CS bits for control
M CONVERTERS L LANES
LANE 1
FRAME
TO
OCTETS
F octets SCRAMBLER 8-bit/
10-bit SER
TX CONTROLLER
LANE 0
8-bit/
10-bit SER
ALIGNMENT
CHARACTER
GENERATOR
ALIGNMENT
CHARACTER
GENERATOR
SYNC~
005aaa084
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Product data sheet Rev. 6 — 8 June 2011 23 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Fig 22. Detailed vi ew of the JESD204A serial ize r wi th de bu g functionality
N
AND
CS
N
AND
CS
00
SCR
SCR
PRBS
8-bit/
10-bit
01
00
01
00
01
10
11
8-bit/
10-bit
PRBS
'0'
'0/1'
PRBS
'0'
'0/1'
PRBS
8
8
N + CS
N + CS
14 + 114 + 1
14 + 1
ADC A
PLL
AND
DLL
frame CLK
character CLK
bit CLK
10
10
11
10
01
00
SER
SER
11
10
00
11
10
00
× 1
× F
× 10F
DUMMY
ADC_PD
ADC_PD
ADC B
PRBS
FSM
(frame
assembly,
character
replication;
ILA,
test mode)
FRAME
ASSEMBLY
005aaa085
sync_request
14 + 1
ADC_MODE[1:0]
SCR_IN_MODE
SCR_IN_MODE
LANE_MODE[1:0]
SWING_SEL[2:0]
LANE_POL
LANE_MODE[1:0]
LANE_POL
14 + 1
14 + 1
DUMMY
PRBS
ADC_MODE[1:0]
Table 13. Output codes versus input voltage
INP INM (V) Offset binary Two’s complement OTR
< 1 00 0000 0000 0000 10 0000 0000 0000 1
100 0000 0000 0000 10 0000 0000 0000 0
0.9998779 00 0000 0000 0001 10 0000 0000 0001 0
0.9997559 00 0000 0000 0010 10 0000 0000 0010 0
0.9996338 00 0000 0000 0011 10 0000 0000 0011 0
0.9995117 00 0000 0000 0100 10 0000 0000 0100 0
.... .... .... 0
0.0002441 01 1111 1111 1110 11 1111 1111 1110 0
0.0001221 01 1111 1111 1111 11 1111 1111 1111 0
0 10 0000 0000 0000 00 0000 0000 0000 0
+0.000122110 0000 0000 0001 00 0000 0000 0001 0
+0.0002441 10 0000 0000 0010 00 0000 0000 0010 0
.... .... .... 0
+0.9995117 11 1111 1111 1011 01 1111 1111 1011 0
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Product data sheet Rev. 6 — 8 June 2011 24 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.6 Serial Peripheral Interface (SPI)
11 .6.1 Register description
The ADC1413D serial inter face is a synchronous serial communications port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both re ad and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
[1] R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte.
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this addres s is th e first registe r to be accessed. An ad dress co unter
is incremented to access subsequent addresses.
+0.9996338 11 1111 1111 110001 1111 1111 11000
+0.9997559 11 1111 1111 1101 01 1111 1111 1101 0
+0.9998779 11 1111 1111 1110 01 1111 1111 1110 0
+1 11 1111 1111 1111 01 1111 1111 1111 0
>+1 11 1111 1111 1111 01 1111 1111 1111 1
Table 13. Output codes versus input voltage …continued
INP INM (V) Offset binary Two’s complement OTR
Table 14. SPI instruction bytes
MSB LSB
Bit 76543210
Description R/W[1] W1 W0 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Table 15. Read or Write mode access description
R/W[1] Description
0 Write mo de operation
1 Read mode operation
Table 16. Number of bytes to be transferred
W1 W0 Number of bytes transferred
001 byte
012 bytes
103 bytes
1 1 4 or more bytes
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Product data sheet Rev. 6 — 8 June 2011 25 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
The steps for a data transfer:
1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine
the start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The Most Significant Bit (MSB) is always sent first (for instruction
and data bytes).
4. A rising edge on pin CS indicates the end of data transmis sion .
11.6.2 Channel control
The two ADC channels can be configured at the same time or separ ately. By using the
register “Channel index”, the user can cho ose which ADC channel receives the next
SPI-instruction. By default the channel A and B receives the same instructions in write
mode. In read mode only A is active.
Fig 23. Transfer diagram for two data bytes (3-wire type)
CS
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data) 005aaa086
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NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 17. Register allocation map
Address
(hex) Register name Access[1] Bit definition Default
(bin)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC control register
0003 Channel index R/W - - - - - - ADCB ADCA 1111 1111
0005 Re set and
Power-down
modes
R/W SW_RST - - - - - PD[1:0] 0000 0000
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV2_SEL DCS_EN 0000 0001
0008 Vref R/W - - - - INTREF_EN INTREF[2:0] 0000 0000
0013 Offset R/W - - DIG_OFFSET[5:0] 0000 0000
0014 Test pattern 1 R/W - - - - - TESTPAT_1[2:0] 0000 0000
0015 Test pattern 2 R/W TESTPAT_2[13:6] 0000 0000
0016 Test pattern 3 R/W TESTPAT_3[5:0] - - 0000 0000
JESD204A control
0801 Ser_Status R RXSYNC_
ERROR RESERVED[2:0] 0 0 POR_TST RESERVED 0100 0000
0802 Ser_Reset R/W SW_RST 0 0 0 FSM_SW_
RST 0 0 0 0000 0000
0803 Ser_Cfg_Setup R/W 0 0 0 0 CFG_SETUP[3:0] 0000 1000
0805 Ser_Control1 R/W 0 TRISTATE_
CFG_PINS SYNC_
POL SYNC_
SINGLE_
ENDED
1 REV_
SCR REV_
ENCODER REV_SERIAL 0100 1001
0806 Ser_Control2 R/W 0 0 0 0 0 0 SWAP_
LANE_1_2 SWAP_
ADC_0_1 0000 0011
0808 Ser_Analog_Ctrl R/W 0 0 0 0 0 SWING_SEL[2:0] 0000 0011
0809 Ser_ScramblerA R/W 0 LSB_INIT[6:0] 0000 0000
080A Ser_ScramblerB R/W MSB_INIT[7:0] 1111 1111
080B Ser_PRBS_Ctrl R/W 0 0 0 0 0 0 PRBS_TYPE[1:0] 0000 0000
0820 Cfg_0_DID R* DID[7:0] 1110 1101
0821 Cfg_1_BID R/W* 0 0 0 0 BID[3:0] 0000 1010
0822 Cfg_3_SCR_L R/W* SCR 0 0 0 0 0 0 L 0000 0000
0823 Cfg_4_F R/W* 0 0 0 0 0 F[2:0] 0000 0001
0824 Cfg_5_K R/W* 0 0 0 K[4:0] 0000 1000
0825 Cfg_6_M R/W* 0 0 0 0 0 0 0 M 0000 0000
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Product data sheet Rev. 6 — 8 June 2011 27 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
[1] an "*" in the Access column means that this register is subject to control access conditions in Write mode.
0826 Cfg_7_CS_N R/W* 0 CS[0] 0 0 N[3:0] 0100 0100
0827 Cfg_8_Np R/W 0 0 0 NP[4:0] 0000 1111
0828 Cfg_9_S R/W* 0 0 0 0 0 0 0 S 0000 0000
0829 Cfg_10_HD_CF R/W* HD 0 0 0 0 0 CF[1:0] 0000 0000
082C Cfg_01_2_LID R/W* 0 0 0 LID[4:0] 0001 1011
082D Cfg_02_2_LID R/W* 0 0 0 LID[4:0] 0001 1100
084C Cfg01_13_FCHK R FCHK[7:0] 0000 0000
084D Cfg02_13_FCHK R FCHK[7:0] 0000 0000
0870 Lane0_0_Ctrl R/W 0 SCR_IN_
MODE LANE_MODE[1:0] 0 LANE_
POL LANE_CLK_
POS_EDGE LANE_PD 0000 0001
0871 Lane1_0_Ctrl R/W 0 SCR_IN_
MODE LANE_MODE[1:0] 0 LANE_
POL LANE_CLK_
POS_EDGE LANE_PD 0000 0000
0890 ADCA_0_Ctrl R/W 0 0 ADC_MODE[1:0] 0 0 0 ADC_PD 0000 0001
0891 ADCB_0_Ctrl R/W 0 0 ADC_MODE[1:0] 0 0 0 ADC_PD 0000 0000
Table 17. Register allocation map …continued
Address
(hex) Register name Access[1] Bit definition Default
(bin)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Product data sheet Rev. 6 — 8 June 2011 28 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11 .6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register Channel index (add ress 0003h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 111111 not used
1 ADCB R/W ADC B gets the next SPI command:
0 ADC B not selected
1 ADC B selected
0 ADCA R/W ADC A gets the next SPI command:
0ADC A not selected
1 ADC A selected
Table 19 . Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital part:
0 no reset
1 performs a reset of the digital part
6 to 2 - - 00000 not used
1 to 0 PD[1:0] R/W Power-down mode:
00 normal (power-up)
01 full power-down
10 sleep
11 normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 SE_SEL R/W select SE clock input pin:
0 select CLKM input
1 select CLKP input
3 DIFF_SE R/W differential/single-ended clock input select:
0 fully differential
1 single-ended
2 - - 0 not used
1 CLKDIV2_SEL R/W select clock input divider by 2:
0 disable
1 active
0 DCS_EN R/W duty cycle stabilizer enable:
0 disable
1 active
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Product data sheet Rev. 6 — 8 June 2011 29 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 21 . Re gister Vref (address 0008h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 I NTREF_EN R/W enable internal programmable VREF mode:
0 disable
1 active
2 to 0 I NTREF[2:0] R/W programmable internal reference:
000 0 dB (FS=2 V)
001 1 dB (FS=1.78 V)
010 2 dB (FS=1.59 V)
011 3 dB (FS=1.42 V)
100 4 dB (FS=1.26 V)
101 5 dB (FS=1.12 V)
110 6 dB (FS=1 V)
111 not used
Table 22. Digital Offset adjustment (address 0013h)
Default values are highlighted.
Register Offset
Decimal DIG_OFFSET[5:0]
+31 011111 +31 LSB
... ... ...
0000000 0
... ... ...
32 100000 32 LSB
Table 23 . Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 TESTPAT_1[2:0] R/W digital test pattern:
000 off
001 mid-scale
010 FS
011 + FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern, to be written in register 0015h and 0016h
110 ‘010101...’
111 ‘101010...’
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Product data sheet Rev. 6 — 8 June 2011 30 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
11.6.4 JESD204A digital control registers
Table 24 . Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_2[13:6] R/W 00000000 custom digital test p a ttern (bit 13 to 6)
Table 25 . Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 TESTPAT_3[5:0] R/W 000000 custom digital test pattern (bit 5 to 0)
1 to 0 - - 00 not used
Table 26. Ser_Status (address 0801 h)
Default values are highlighted.
Bit Symbol Access Value Description
7 RXSYNC_ERROR R 0 set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0] - 100 reserved
3 to 2 - - 00 not used
1POR_TST R 0 power-on-reset
0 RESERVED - 0 reserved
Table 27. Ser_Reset (address 0802h)
Default values are highlighted.
Bit Symbol Access Value Description
7SW_RST R/W0 initiates a software reset of the JESD204A unit
6 to 4 - - 000 not used
3FSM_SW_RSTR/W0 initiates a software reset of the internal state machine of
JESD204A unit
2 to 0 - - 000 not used
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Product data sheet Rev. 6 — 8 June 2011 31 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
[1] F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Table 28. Ser_Cfg_Setup (add ress 0803h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 0 CFG_SETUP[3:0] R/W quick configuration of JESD204A. These settings overrule the
configuration of pins CFG3 to CFG0 (see Table 29).
Table 29 . JESD204A co nfiguration table
CFG_SETUP[3:0] ADC A ADC B La ne 0 Lane 1 F[1] HD[1] K[1] M[1] L[1] Comment CS[1] CF[1] S[1]
0 0000 ON ON ON ON 20922(FK) 17 1 0 1
1 0001 ON ON ON OFF 4 0 5 2 1 (F K) 17 1 0 1
2 0010 ON ON OFF ON 40521(FK) 17 1 0 1
3 0011 ON OFF ON ON 111712(FK) 17 1 0 1
4 0100 OFF ON ON ON 111712(FK) 17 1 0 1
5 0101 ON OFF ON OFF 2 0 9 1 1 (F K) 17 1 0 1
60110 ON OFF OFF ON 20911(FK) 17 1 0 1
70111 OFFON ON OFF 2 0 9 1 1 (F K) 17 1 0 1
8 1000 OFF ON OFF ON 20911(FK) 17 1 0 1
9 1001 reserved
10 1010 reserved
11 1011 reserved
12 1100 reserved
13 1101 reserved
14 1110 ON ON ON ON 2 0 9 2 2 test: loop
alignment 101
15 1111 OFF OFF OFF OFF 2 0 9 2 2 chip
power-down 101
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Product data sheet Rev. 6 — 8 June 2011 32 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 30. Ser_Control1 (address 0805h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 TRISTATE_CFG_PINS R/W 1 pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
5 SYNC_POL R/W defines the sync signal polari ty:
0 synchronization sign al is active LOW
1 synchronization signal is active HIGH
4 SYNC_SINGLE_ENDED R/W defines the inp ut mode of the sync signal:
0 synchr onization input mode is se t in Differential mode
1 synchronizatio n input mode is set in Single-ended mode
3 - - 1 not used
2 REV_SCR - LSBs are swapped with MSBs at the scrambler input:
0disable
1 enable
1 REV_ENCODER - LSBs are swapped with MSBs at the 8-bit/10-bit en coder input:
0disable
1 enable
0 REV_SERIAL - LSBs are swapped with MSBs at the lane input:
0 disable
1enable
Table 31. Ser_Control2 (address 0806h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 000000 not used
1 SWAP_LANE_0_1 R/W swaps the outputs of the JESD204A unit. (output buffer A is
connected to Lane 1, output buffer B is connected to Lane 0):
0 disable
1enable
0 SWAP_ADC_A_B R/W swaps the inputs of the JESD204A unit. (ADC A output is
connected to input B, ADC B is connected to input A):
0 disable
1enable
Table 32. Ser_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 SWING_SEL[2:0] R/W 011 defines the swing output for the lane pads
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Product data sheet Rev. 6 — 8 June 2011 33 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 33. Ser_ScramblerA (address 0809h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 to 0 LSB_INIT[6:0] R/W 0000000 defines the initialization vector for the scr ambler polynomial
(lower)
Table 34. Ser_ScramblerB (address 080Ah)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 MSB_INIT[7:0] R/W 11111111 defines the initialization vector for the scrambler polynomial
(upper)
Table 35. Ser_PRBS_Ctrl (address 080 Bh)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 000000 not used
1 to 0 PRBS_TYPE[1:0] R/W defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset) PRBS-7
01 PRBS-7
10 PRBS-23
11 PRBS-31
Table 36. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 DID[7:0] R 11101101 defines the device (= link) identification number
Table 37. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 0 BID[3:0] R/W 1010 defines the bank ID – extension to DID
Table 38. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit Symbol Access Value Description
7 SCR R/W 0 scrambling enabled
6 to 1 - - 000000 not used
0 L R/W 0 defines the number of lanes per converter device, minus 1
Table 39. Cfg_4_F (address 082 3h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 F[2:0] R/W 001 defines the number of octets per frame, minus 1
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Product data sheet Rev. 6 — 8 June 2011 34 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 40. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 K[4:0] R/W 01000 defines the numbe r of fra mes per multiframe, minus 1
Table 41. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 1 - - 0000000 not used
0 M R/W 0 defines the number of converters per device, minus 1
Table 42. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 CS[0] R/W 1 defines the number of control bits per sample, minus 1
5 to 4 - R 00 not used
3 to 0 N[3:0] R/W 0100 defines the converter resolu tion
Table 43 . Cfg _8_Np (address 0827h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 NP[4:0] R/W 01111 defines the total number of bits per sample, minus 1
Table 44. Cfg_9_S (address 08 28h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 1 - - 0000000 not used
0S R/W0 defines number of samples per converter per frame cycle
Table 45. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit Symbol Access Value Description
7 HD R/W 0 defines high density format
6 to 2 - - 00000 not used
1 to 0 CF[1:0] R/W 00 defines number of control words per frame clock cycle per link.
Table 46. Cfg_01_2_LID (address 082Ch)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 LID[4:0] R/W 11011 defines lane 0 identification nu mber
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Product data sheet Rev. 6 — 8 June 2011 35 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 47. Cfg_02_2_LID (address 082Dh)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 LID[4:0] R/W 11100 defines lane 1 identification number
Table 48 . Cfg01_13_FCHK (address 084Ch)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 FCHK[7:0] R 00000000 defines the checksum value for lane 0
checksum corresponds to the sum of all the link configuratio n
parameters modulo 256 (as defined in JEDEC S tandard
No.204A)
Table 49 . Cfg02_13_FCHK (address 084Dh)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 FCHK[7:0] R 00000000 defines the checksum value for lane 1
checksum corresponds to the sum of all the link configuratio n
parameters module 256 (as defined in JEDEC S tandard
No.204A)
Table 50. Lane0_0_Ctrl (address 0870h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 SCR_IN_MODE R/W defines the input type for scrambler and 8-bit/10-bit units:
0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1 input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
5 to 4 LANE_MODE[1:0] R/W defines output type of lane outp ut unit:
00 (reset) normal mode: lane outp ut is the 8-bit/10-bit output unit
01 constant mode: lane output is set to a constant (0 0)
10 toggle mode: lane output is toggling between 0 0 and 0 1
11 PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
3 - - 0 not used
2 LANE_POL R/W defines lane polarity:
0 lane polarity is normal
1 lane polarity is inverted
1 LANE_CLK_POS_EDGE R/W defines lane clock polarity:
0 lane clock provided to the serializer is active on positive
edge
1 lane clock provided to the serializer is active on negative edge
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Product data sheet Rev. 6 — 8 June 2011 36 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
0 LANE_PD R/W lane power-down control:
0 lane is operationa l
1 lane is in Power-down mode
Table 50. Lane0_0_Ctrl (address 0870h) …continued
Default values are highlighted.
Bit Symbol Access Value Description
Table 51. Lane1_0_Ctrl (address 0871h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 SCR_IN_MODE R/W defines the input type for scrambler and 8-bit/10-bit units:
0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit
units is the output of the frame assembly unit.
1 input of the scrambler and 8-bit/10-bit units is the PRBS
generator (PRBS type is defined with “PRBS_TYPE[1:0]”
(Ser_PRBS_Ctrl register)
5 to 4 LANE_MODE[1:0] R/W defines output type of lane outp ut unit:
00 (reset) normal mode: lane outp ut is the 8-bit/10-bit output unit
01 constant mode: lane output is set to a constant (0x0)
10 toggle mode: lane output is toggling between 0x0 and 0x1
11 PRBS mode: lane output is the PRSB generator (PRBS type is
defined with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
3 - - 0 not used
2 LANE_POL R/W defines lane polarity:
0 lane polarity is normal
1 lane polarity is inverted
1 LANE_CLK_POS_EDGE R/W defines lane clock polarity:
0 lane clock provided to the serializer is active on positive
edge
1 lane clock provided to the serializer is active on negative edge
0 LANE_PD R/W lane power-down control:
0 lane is operational
1 lane is in Power-d own mode
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Product data sheet Rev. 6 — 8 June 2011 37 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 52. ADCA_0_Ctrl (address 0890h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - - 00 not used
5 to 4 ADC_MODE[1:0] R/W defines input type of JESD204A unit:
00 (reset) ADC output is connected to the JESD204A input
01 not used
10 JESD204A input is fed with a dummy const ant , set to : OTR = 0
and ADC[13:0] = “10011011101010”
11 JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
3 to 1 - - 000 not used
0 ADC_PD R/W ADC power-down control:
0 ADC is operational
1 ADC is in Power-down mode
Table 53. ADCB_0_Ctrl (address 0891h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - - 00 not used
5 to 4 ADC_MODE[1:0] R/W defines input type of JESD204A unit
00 (reset) ADC output is connected to the JESD204A input
01 not used
10 JESD204A input is fed with a dummy constant, set to: OTR = 0
and ADC[13:0] = “10011011101010”
11 JESD204A is fed with a PRBS generator (PRBS type is defined
with “PRBS_TYPE[1:0]” (Ser_PRBS_Ctrl register)
3 to 1 - - 000 not used
0 ADC_PD R/W ADC power-down control:
0 ADC is operational
1 ADC is in Power-down mode
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Product data sheet Rev. 6 — 8 June 2011 38 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
12. Package outline
Fig 24. Package outline SOT684-7 (HVQFN56)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT684-7 - - -
MO-220
- - -
sot684-7_po
08-11-19
09-03-04
Unit
mm max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00 0.2 8.1
8.0
7.9
5.95
5.80
5.65
8.1
8.0
7.9 0.5 6.5 0.5
0.4
0.3 0.1
A(1)
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm SOT684-7
A1b
0.30
0.21
0.18
cD
(1) DhE(1) Eh
6.55
6.40
6.25
ee
1e2
6.5
Lv
0.1
w
0.05
y
0.05
y1
0 2.5 5 mm
scale
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A
c
A1
b
e2
e1
e
e
1/2 e
1/2 e AC B
vCw
terminal 1
index area Dh
Eh
1
15
14 29
42
28
4356
L
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Product data sheet Rev. 6 — 8 June 2011 39 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
13. Abbreviations
Table 54. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
DCS Duty Cycle Stabilizer
ESD ElectroStatic Discharge
IF Intermediate Frequency
IMD InterModulation Distortion
LSB Least Significant Bit
LVCMOS Low Voltage Complementary Metal Oxide Semiconductor
LVPECL Low-Voltage Positive Emitter-Coupled Logic
MSB Most Significant Bit
OTR OuT-of-Range
PRBS Pseudo-Random Binary Sequence
SFDR Spurious-Free Dynamic Ran ge
SNR Signal-to-Noise Ratio
SPI Serial Peripheral Interface
TX Transmitter
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Product data sheet Rev. 6 — 8 June 2011 40 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
14. Revision history
Table 55. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
ADC1413D_SER v.6 20110608 Product data sheet - ADC1413D_SER v.5
Modifications: •Section 10.2 “Clock and digital output timing” has been updated.
ADC1413D_SER v.5 20110209 Product data sheet - ADC1413D_SER v.4
ADC1413D_SER v.4 20100423 Preliminary data sheet - ADC1413 D_SER v.3
ADC1413D_SER v.3 20100412 Objective data sheet - ADC1413D065_080_105_125_2
ADC1413D065_080_105_125_2 20090604 Objective data sheet - ADC1413D065_080_105_125_1
ADC1413D065_080_105_125_1 20090528 Objective data sheet - -
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Product data sheet Rev. 6 — 8 June 2011 41 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury , death or severe property or environmenta l
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo m er(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
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Product data sheet Rev. 6 — 8 June 2011 42 of 43
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifica tions, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 June 2011
Document identifier: ADC1413D_SER
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Thermal characteristics . . . . . . . . . . . . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
10.2 Clock and digital output timing . . . . . . . . . . . . 11
10.3 Serial output timing. . . . . . . . . . . . . . . . . . . . . 12
10.4 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11 Application information. . . . . . . . . . . . . . . . . . 14
11.1 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 14
11.1.1 Input stage description . . . . . . . . . . . . . . . . . . 14
11.1.2 Anti-kickback circuitry. . . . . . . . . . . . . . . . . . . 15
11.1.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11.2 System reference and power management . . 16
11.2.1 Internal/external reference . . . . . . . . . . . . . . . 16
11.2.2 Programmable full-scale. . . . . . . . . . . . . . . . . 18
11.2.3 Common-mode output voltage (VO(cm)) . . . . . 19
11.2.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 20
11.3.3 Duty cycl e stabilizer . . . . . . . . . . . . . . . . . . . . 21
11.3 .4 Clock input divider . . . . . . . . . . . . . . . . . . . . . 21
11.4 Digital outputs. . . . . . . . . . . . . . . . . . . . . . . . . 21
11.4.1 Serial output equivalent circuit . . . . . . . . . . . . 21
11.5 JESD204A serializer. . . . . . . . . . . . . . . . . . . . 22
11.5.1 Digital JESD204A formatter . . . . . . . . . . . . . . 22
11.5.2 ADC core output codes versus input voltage . 23
11.6 Serial Peripheral Interface (SPI). . . . . . . . . . . 24
11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 24
11.6.2 Channel control . . . . . . . . . . . . . . . . . . . . . . . 25
11.6.3 Register description . . . . . . . . . . . . . . . . . . . . 28
11.6.3.1 ADC control registers . . . . . . . . . . . . . . . . . . 28
11.6.4 JESD204A digital control registers. . . . . . . . . 30
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 39
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 40
15 Legal information . . . . . . . . . . . . . . . . . . . . . . 41
15.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 41
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42
16 Contact information . . . . . . . . . . . . . . . . . . . . 42
17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
