PERIPHERAL INTERFACE ADAPTER (PIA) The MC6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the M6800 family of microprocessors. This device is capable of interfacing the MPU to peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the overall operation of the interface. @ 8-Bit Bidirectional Data Bus for Communication with the MPU @ Two Bidirectional 8-Bit Buses for Interface to Peripherals @ Two Programmable Control Registers @ Two Programmable Data Direction Registers @ Four Individually-Controlled Interrupt Input Lines; Two *>~+s\~, *V$3 *&a `3, 3 Usable as Peripheral Control Outputs \; "`ik" ,J @ Handshake Control Logic for Input and Output Periphe~~~~`~~~~.~`~"` .h*+ .,`:# Kit\& Operation `i. High-Impedance Three-State and Direct Transis$r DriGe >@.`+ Peripheral Lines _ "& !a<$. Program Controlled Interrupt and InterruptV&$%$e Capability CMOS Drive Capability on Side A Peri~~~~~~~~~~~s Two TTL Drive Capability on All A a~~~~~~~e _' Buffers /;;;g>* *v* 0 TTL-Compatible ,A. ,*e .\+ x;<+ i "<& `\< ,V,&,, `~`": @ Static Operation vi, ,,;# *&p A IN-CHAN ERDIP PACKAGE PLASTIC PACKAGE CASE 711 PIN ASSIGNMENT INFORMATION Frequency (MHz) 1.0 1.0 1.5 1.5 2.0 1.0 1.0 1.5 1.5 2.0 1 Plastic P Suffix 1 1.0 1.0 1.5 1.5 2.0 Temperature OT to 70C - 40C to 85'C OT to 7OT - 40C to 85'C OT to 7OT ooc to 7OT - 4O'C to 85'C 0C to 70C - 40C to 85C OT to 70C ooc to 70C to 85OC 0C to 7OT - 40C to 85C - 40C 0C to 7ooc Order Number MC6821 L MC6821 CL MC68A21 L MC68A21 CL MC68B21 L MC6821 S MC6821 CS MC68A21 S MC68A21 CS MC68B21 S MC6821 P MC682lCP MC68A21 P MC68A21 CP MC68B21 P @MOTOROLA INC ,1985 DS9435R5 MAXIMUM RATINGS Characteristics Supply Symbol Voltage Input Voltage Operating Temperature Range MC6821, MC68A21, MC68B21 MC6821C. MC68A21C Storage Temperature Range THERMAL Value -0.3 -0.3 TL 0 -40 -55to "cc "in TA Tstg Unit to +7.0 to +7.0 to TH to 70 to +85 +150 This device contains clrcuttry to protect the inputs against damage due to high static voltages or electric fields, however, It IS advised that normal precautions be taken lo avoid applications of any voltage higher than v v T maxlmum Impedance recommended "C Symbol Value Unit appropriate Thermal Resistance Ceramic Plastic I Cerdip BJA I voltages For proper that V,, and logic voltage this highoperation It IS Vout be CQI?~. lev$@&*;f@ther ." `I_ \*<;g \*$ *& S?W 1 x':2$.\-"; "-$y$\ `kji>b 1. >kt,;,. " q,;pi VSS or VCC). 50 loo 60 to "b@ ,%i stralned to the range VSS 5 (V.,m,.`~~:$[` i"" ;.& `h <;g VrJut~~VCCUnused inputs must always ~-~~~~~~~~~n CHARACTERISTICS Characteristic rated circuit. T/W I `, POWER CONSIDERATIONS The average chip-junction temperature, TJ, in OC can be obtained from: (I) TJ=TA+(PD*BJA) Where: TA = Ambient Temperature, Package BJ,L,= Thermal `C Resistance, PD=PINT+ PPORT PINT= ICC x VCC, Watts PpDRT= Port Power - Dissipation, Chip ._`,\,,,P Junction-to-Ambient, Internal sC@$:, a>t+~+t,p *-$' ".TS~ "$~, Power User ,,`-,~ D~~~~i~~d `ix A$ For most applications PPoRT~PINT and can be neglected. P~~~~ `* may _drive Darlington bases or sink LED loads. **q An approximate relationship between PD and TJ (if PBQRT i$ neglected) `_ `y;, ":. PD = K + (T J + 273'C) "k\" Q `ST<.*. ". "$" _b *\ Solving equations 1 and 2 for K gives: ~-; \\ K = PD*iTA + 273%) + 0Jj@D2 Where K is a constant for a known TA. Using value of TA. DC ELECTRICAL pertaining this value ,~~~~~,~~~~ CHARAC@&dS INPlJ~~&&$ \- (V CC = 5.0 Vdc become RESET, significant f 5%, VSS = 0, TA= CSO, CSl, from equation (3) by measurtng by solving equations II) and TL to TH unless Cu'$= 0, TA= -- INTEF&&j"t"&dfTPUTS (IRQA, @@&$% VOltage (ILoad ?$$&&tput Leakage Current Caaacitance DATA (Vin 25OC, f = 1 .O MHz) to otherwise 1 Min (3) PD (at equlllbrium) (2) iteratively for any noted) ) Typ 1 Max I Unit CS2) "IH vss+2.0 - "IL VSS-0.3 - - lin Capacita& is configured is: ) Symbol RSO, RSl, if the device -) Characteristic Ehable, ,, - to the par;Q&,&r *>;>,v\,t:,"B part. K can be determined of K the ~~~~~~,~~ PD and TJ can be obtained _"rib\,, ,j , f I BUS CONTROL Watts Cin "cc VSS+O.8 V V 1.0 2.5 FA - 7.5 PF - - vss+o.4 v - 1.0 - - - IROB) = 3.2 mA) VOL IO2 = 0, Tn = 25OC. f = 1 .O MHz) cm It 10 5.0 @A PF BUS (DO-D71 Input High Voltage Input Low Voltage Hi-Z Input Leakage Current lVin=0.4 to 2.4 V) VIH vss+2.0 - VIL VSS-0.3 - `I2 Output High Voltage (ILoad = - 205 PA) VOH Output Low (lLoad= VOL Capacitance Voltage 1.6 mA) IVin = 0, TA = 25OC, f = 1 .O MHz) Cin - VSS+2.4 "cc VSS+O.8 2.0 10 - - - - - - vss+o.4 12.5 V V LtA V v PF ] DC ELECTRICAL CHARACTERISTICS (Continued) Characteristic PERIPHERAL BUS (PAO-PA7, Capacitance POWER 25"C, CAl, CA2, 1 Symbol CBl, 1 Min CB2) 1 f = 1 .O MHz) c I" REQUIREMENTS Internal I (Vin = 0, TA= PBO-PB7, Power Dissipation (Measured I"I111. I data bus output PlNT I Characteristic Number `The at TL=O"C) buffers are no longer.&k@hg &\ V,k< *i" _ `>*\>y,.\ .y<*:, <," ,>* or srnkrng current Notes: 1. Voltage levels shown are V~s0.4 V, VHr2.4 V, unless otherwise 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise 3 Symbol by tDHPmax specified. specified. Is (Hugh Impedance) 1 Typ 1 Max [ Unit ] PERIPHERAL TlMlNG CHARACTERISTICS (VW = 5 0 V * 5%. VSS = 0 V, TA= TI- to TH unless otherwlse speclfied) Characteristic FIGURE 3 - TTL EQUIVALENT TEST LOAD (PAD-PA7, PBO-PB7, CA2, CB2) P5.0v t Test RL=1.25 MM06150 or Equiv. Point MMD7000 or Equiv. C=3OpF, FIGURE (PAO-PA7, Test Point R=12 k 5 - NMOS EQUIVALENT TEST LOAD (IRQ CA2) Only) 5.0 v 1.5 kQ 7 eL I T 30 pF Test Point 4 100 PF T kht FIGURE 6 - PERIPHERAL DATA SETUP (Read Mode) AND HOLD TIMES (Read FIGURE 7 - CA2 DELAY TIME Mode; CRA-5= CRA3= 1, CRA-4= 0) CA2 Enable j+-/j- (Read a- FIGURE r *Assumes part was dese the previous E pulse. FIGURE 8 - CA2 DELAY Mode; CRAd= 1, CRA3= 10 - PERIPHERAL DATA (Write Mode; CRBd=CRB-3= AND TIME CRA-4= FIGURE 0) CB2 DELAY 1, CRB-4=0) TIMES ,& *A `SF\ "*,*< ".>l 9 - PERIPHERAL (Write Mode; (Write FIGURE Mode; CM CRA4= 0) 11 - CB2 DELAY TIME CRB-5= CRB-3= 1, CRB-4=0) Enable FIGURE CRB-3=CRB-4=0) 13 - INTERRUPT PULSE WIDTH IROA'6. j_ Note: Timing measurements was deselected E pulse. are referenced m RESPONSE tRs,*-L *Assumes *Assumes part any previous AND Interrupt Enable Bits are set. during to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted FIGURE 14 - IRQ RELEASE TIME FIGURE 15 - RESET LOW TIME -I Note: Timing measuremenrs are referenced to and from FIGURE IRQA 36 a low voltage 16 - of 0.8 volts and a high voltage EXPANDED BLOCK of 2.0 volts, unless otherwis6+~@$&~ A- \*J&/ * _ &q _ \ "5' DIAGRAM 4 . DO 33 01 32 02 31 40 CA1 39 CA2 -s-J--- Data BUS Buffers (DEB) D3 30 04 29 D5 28 D6 27 2 PA0 07 26 3 PA1 4 PAZ 5 PA3 6 PA4 7 PA5 --Jr 8 PA6 9 PA7 10 output Register (ORB) B Pertpheral lnlerface B c IRQB 37 4 Interrupt Control sratus B PBO 11 PBl 12 PB2 i3 PB3 14 PB4 15 PB5 16 PB6 17 PBJ -18 CBI -19 CB2 PIA INTERFACE The PIA interfaces to the M6800 bus with an 8-bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, a read/write line, an enable line and a reset line. To ensure proper operation with the MC6800, MC6802, or MC6808 microprocessors, VMA should be used as an active part of the address decoding. SIGNALS FOR MPU for the duration of the E pulse. The device is deselected when any of the chip selects are in the inactive state Register written Selects (RSO and RSI) - The two register or read. Bidirectional Data (DO-D71 - The bidirectional data lines (DO-D7) allow the transfer of data between the MPU and the PIA. The data bus output drivers are three-state devices that remain in the high-impedance (off) state except when the MPU performs a PIA read operation. The read/write line is in the read (high) state when the PIA is selected for a read operation. Enable (E) - The enable pulse, E, is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading and trailing edges of the E pulse. Read/Write (R/W) - This signal is generated by the MPU to control the direction of data transfers on the data bus. A low state on the PIA read/write line enables the input buffers and data is transferred from the MPU to the PIA on the E signal if the device has been selected. A high on the read/write line sets up the PIA for a transfer of data to the bus. The PIA output buffers are enabled when the proper address and the enable pulse E are present. RESET - The active low RESET line is used to re$${3all register bits in the PIA to a logical zero (low). This lin&Qar%e d$*h~bs ; `" used as a power-on reset and as a master rese@%nng system operation * " \~\\>;,~S*; Chip Selects (CSO, CSI, and cs2) ~~~%&$$e'three input signals are used to select the PIA. C&O'%<% CSI must be high and CS2 must be low for sel~~~~~~~he device. Data transfers are then performed und&h&ontrol of the enable $..+`at;_*a$,.` and read/write signals. The ct$p s@ect lines must be stable interrupt by the MPU may be accomplished routine that, on a prioritized basis, sequentially s and tests the two control registers in each PIA for inflag bits that are set. The interrupt flags are cleared (zeroed) as a result of an MPU Read Peripheral Data Operation of the corresponding data register. After being cleared, the interrupt flag bit cannot be enabled to be set until the PIA is deselected during an E pulse. The E pulse is used to condition the interrupt control lines (CAI, CA2, CBI, CB2). When these lines are used as interrupt inputs, at least one E pulse must occur from the inactive edge to the active edge of the interrupt input signal to condition the edge sense network. If the interrupt flag has been enabled and the edge sense circuit has been properly conditioned, the interrupt flag will be set on the next active transition of the interrupt input pin. PIA PERIPHERAL INTERFACE LINES The Pl~.~~~~~~s two 8-bit bidirectional data buses and four in~~m$&control lines for interfacing to peripheral de$sq&+ *\~,$\>\<Jt~>~\~ * ~~~~~on A Peripheral Data (PAO-PA71 - Each of the petrpheral data lines can be programmed to act as an input or output. This is accomplished by setting a "1" in the corresponding Data Direction Register bit for those lines which are to be outputs. A "0" in a bit of the Data Direction Register causes the corresponding peripheral data line to act as an input. During an MPU Read Peripheral Data Operation, the data on peripheral lines programmed to act as inputs appears directly on the corresponding MPU Data Bus lines. In the input mode, the internal pullup resistor on these lines represents a maximum of 1.5 standard TTL loads. The data in Output Register A will appear on the data lines that are programmed to be outputs. A logical "1" written into the register will cause -a "high" on the corresponding data line while a "0" results in a "low." Data in Output Register A may be read by an MPU "Read Peripheral Data A" operation when the corresponding lines are programmed as outputs. This data will be read properly if the voltage on the peripheral data lines is greater than 2.0 volts for a logic "I" output and less than 0.8 volt for a logic "0" output. Loading the output lines such that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a Read operation to differ from that contained in the respective bit of Output Register A. Section B Peripheral Data (PBO-PB7) - The peripheral data lines in the B Section of the PIA can be programmed to act as either inputs or outputs in a similar manner to PAOPA7. They have three-state capabiity, allowing them to enter a high-impedance state when the peripheral data line is used as an input. In addition, data on the peripheral data lines `BO-PB7 will be read properly from those lines programmed IS outputs even if the voltages are below 2.0 volts for a `high" or above 0.8 V for a "low". As outputs, these lines Ire compatible with standard TTL and may also be used as a source of at least 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. Interrupt Input (CA1 and CBI) - Peripheral input lines 3A1 and CBI are input only lines that set the interrupt flags If the control registers. The active transition for these ;ignals is also programmed by the two control registers. Peripheral Control (C/G!) - The peripheral control line CA2 can be programmed to act as an interrupt input or as a peripheral control output. As an output, this line is compatible with standard TTL; as an input the internal pullup resistor on this line represents 1.5 standard TTL loads. The function of this signal line is programmed with Control Register A. Peripheral Control (CB2) - Peripheral Control line CB2 may also be programmed to act as an interrupt input or peripheral control output. As an input, this line has higQnput impedance and is compatible with standard TT~.~~~~:~~ output it is compatible with standard TTL and rn~~~~~ be used as a source of up to 1 milliampere at 1.5 v~~~~~~~~ectly drive the base of a transistor switch. This line&QrQgrammed ??<>$ >tv; Xb& by Control Register B. " *& *f*.**s"\, INTERNAL Notice the diffe&r+c&between a Port A and Port B read INITIALIZATION operation whe~.~~~~~~~~utput mode. When reading Port A, A RESET has the effect of zeroing all PIA registers. This the actual pi~~~~~~~~, whereas the B side read comes from an NilI set PAO-PA7, PBO-PB7, CA2 and CB2 as inputs, and all output la@hk&$d of the actual pin. nterrupts disabled. The PIA must be configured during the restart program which follows the reset. COb$@Ol?kGISTERS (CRA and CRB) There are six locations within the PIA accessible to the ,~~~~~~~~~o Control Registers (CRA and CRB) allow the MPU MPU data bus: two Peripheral Registers, two Data Direction LsX,& c@trol the operation of the four peripheral control lines Registers, and two Control Registers. Selection of these -GC:?@?, CA2, CBI, and CB2. In addition they allow the MPU to locations is controlled by the RSO and RSl inputs together `q&..*, bs;&ehable the interrupt lines and monitor the status of the interGth bit 2 in the Control Register, as shown in Table 1. Details of possible configurations of the Data Direction<a< ,:& "rupt flags. Bits 0 through 5 of the two registers may be written or read by the MPU when the proper chip select and \.P'`-& 3nd Control Register are as follows: *$\ -+`S. register select signals are applied. Bits 6 and 7 of the two `FZ.. ,,*+\,.. ""pi:. `"\, ., \ registers are read only and are modified by external interrupts TABLE 1 - INTERNAL ADDRESSING ,~~~~~`~~~~~~~`~~~~ occurring on control lines CAI, CA2, CBI, or CB2. The format of the control words is shown in Figure 18. DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and CRB-2) Bit 2, in each Control Register lCRA and CRB), determines selection of either a Peripheral Output Register or the corresponding Data Direction E Register when the proper register select signals are applied to RSO and RSI. A "1" in bit 2 allows access of the Peripheral Interface Register, while a "0" causes the Data Direction Register to be addressed. PORT~$&&~ARDWARE CHARACTERISTICS ~~~~~~n in Figure 17, the MC6821 has a pair of I/O ports wh&$?haracteristics differ greatly. The A side is designed to drive CMOS logic to normal 30% to 70% levels, and incorporates an internal pullup device that remains connected even in the input mode. Because of this, the A side requires more drive current in the input mode than Port B. In contrast, the B side uses a normal three-state NMOS buffer which cannot pullup to CMOS levels without external resistors. The B side can drive extra loads such as Darlingtons without problem. When the PIA comes out of reset, the A port represents inputs with pullup resistors, whereas the B side (input mode also) will float high or low, depending upon the load connected to it. Interrupt Flags (CRAB, CRA-7, CRBB, and CRB-7) The four interrupt flag bits are set by active transitions of signals on the four Interrupt and Peripheral Control lines when those lines are programmed to be inputs. These bits cannot be set directly from the MPU Data Bus and are reset indirectly by a Read Peripheral Data Operation on the appropriate section. Control of CA2 and CB2 Peripheral Control Lines (CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, and CRB-5) - Bits 3,4, and 5 of the two control registers are used to control the CA2 and CB2 Peripheral Control lines. These bits determine if the control lines will be an interrupt input or an output control signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) is an interrupt input line similar to CA1 (CBI). When CRA-5 (CRB-5) is high, CA2 (CB2) becomes an output signal that may be used to control peripheral data transfers. When in the output mode, CA2 and CB2 have slightly different loading characteristics. Control of CA1 and CBI Interrupt Input Lines (CRA-0, CRB-1) - The two lowest-order bits of CRB-0, CRA-1, and the control registers lines CA1 and CBI. are used to control Bits CRA-0 and the interrupt input CRB-0 are used to FIGURE Port enable the MPU interrupt signals IRQA and Im, tively. Bits CRA-1 and CRB-1 determine the active of the interrupt input signals CA1 and CBI. 17 - PORT A AND A in PORT Port R Data DIrection B EQUIVALENT CIRCUITS DATA (I -Output (04nput To External Bus Pin1 PinI I I Read Data in Input A A= 1.5 MHz 8=2.0 MHz Device Designation In M6800 Famllv Temperature Range Blank=OO+70C C= -4O'=+85"C Package P = Plastic S = Cerdlp L = Ceram7lc BETTER Better suffix program processing IS available letters to part number. Level 1 add Level 1 "S" Level Level PROGRAM "S" Level 2 add on all types "D" Level Adc 1 llsted. 3 add = 10 Temp Cycles - (-25 to 150C); HI Temp testing at TA max 2 "D" = 168 Hour Burn-In at 125C 3 "DS" = Comblnatlon of Level 1 and 2 "DS" of B when Mode respectransition FIGURE Determine Active CA1 (Cl311 Transition for Setting Interrupt Flag IRQA(B)l - (bit 7) IRQA(B)l set by high-to-low transition on CA1 bl=O: (CBII set by low-to-high transition on CA1 bl = 1: IRQA(B)l (CBII. CA1 (CBI) bO=O: I I IRQA(B) 1 Interrupt bO= 1: I Flag (bit 7) Register IRQA(Bj2 Flag IRQA(B)l Flag CONTROL Interrupt Request WORD FORMAT Enable/Disable Disables IRQAIB) MPU Interrupt by CA1 (CBI) active transition.' Enable IRQA(BI MPU Interrupt by CA1 (CBli active transition. 1. IRQA(B) will occur on next (MPU generated) posmve transition of b0 if CA1 tCBl1 active transltion occurred while interrupt was disabled. Goes high on active transition of CA1 ICBI); Automatically cleared by MPU Read of Output Register A(B). May also be cleared by hardware Reset. Control 18 - CA2 lCB2) Control Access I IRQA(B)Z Interrupt Flag (bit 6) When CA2 (CB2) is an input, IRQAlBl goes high on active transition CA2 (CB21; Automatically cleared by MPU Read of Output Register AIB). May also be cleared by hardware Reset. CA2 2=0, (CB2) Established as Output (b5=1): not affected by CA2 (CB2) transitions. IRQA(B) L L I CA2 (CB2) b5 --_ b4 t Established as Output by b5= 1 INote that operation of CA2 and CB2 output functions are not identical) --e 1 0 CA2 b3 = 0: $3 Read Strobe with CA1 Restore -i"$ CA2 goes low on first high:t?kw E transition following an ~~~~ of Output Register A; re&&c&gh by next active CA1 ?~~~~~, as "~>*~~`$k"I specified by bit I+\ ,~+&% :; Read Strobe w&th &@&ore CA2 goes l~~`~~~~~~st high-to-low E transitio~~follr&ving an MPU read of Out~~~~~~er A; returned high by n,e&&$$to-low E transition dur,?~~~~~~ect, b3 = 1: + CB2 :*+ ">@ b3~&&&ite Strobe with CBI Restore ST,a,%,, `+@2 goes low on first low-to-high ?b<,~ "&&" sSF `V?h E transition following an MPU write .< k,\ 9 :QL& into Output Register 8; returned 6` f ;-i`; high by the next active CBl transi*$: ~<$P `&$S tion as specified by bit 1. CRB-b7 -\ \' `,Lk I_ `\&<?>, ,>d must first be cleared by a read of &$, %Q,\S "~@w~ " data. %$$ ?&#,, b3= 1: Write Strobe with E Restore $>, \`\* ;\*> <$:$* CB2 goes low on first low-to-high rt. E transition following an MPU write into Output Register B; returned b5 high by the next low-to-high E tran-- b4 b3 sition following an E pulse which occurred while the part was deselected. 1 1 Set/Reset CA2 (CB2) CA2 lCB2) goes low as MPU writes b3= 0 into Control Register. L CA2 lCB2) goes high as MPU b3= 1 into Control Register. writes :$.@ (CB2) Established as Input by b5= 0 CA2 (CB2) Interrupt Request Enable/Disable b3=0: Disables IRQA(B) MPU Interrupt by CA2 ICB2) active transition.* b3= 1: Enables IRQAlB) MPU Interrupt by CA2 lCB2) active transition. `IRQA(B) WIII occur on next (MPL! generatted) positive transition of b3 if CA2 lCB21 active transition occurred while interrupt was disabled. Determines Active CA2 (CB2) Transition for Setting Interrupt Flag IRQA(B)P - (Bit b6) b4=0: IRQA(B)2 set by high-to-low transition on CA2 (CB2). b4= 1: IRQA(B)Z set by low-to-high tion on CA2 (CB2). transi- PACKAGE DIMENSIONS 3501 ED BLUESTEIN BLVD, AUSTIN, TEXAS 78721 0 A SUBSIDIARY OF MOTOROLA INC -