PERIPHERAL INTERFACE ADAPTER (PIA)
The MC6821 Peripheral Interface Adapter provides the universal
means of interfacing peripheral equipment to the M6800 family of
microprocessors. This device is capable of interfacing the MPU to
peripherals through two 8-bit bidirectional peripheral data buses and
four control lines. No external logic is required for interfacing to most
peripheral devices.
The functional configuration of the PIA is programmed by the MPU
during system initialization. Each of the peripheral data lines can be pro-
grammed to act as an input or output, and each of the four con-
trol/interrupt lines may be programmed for one of several control
modes. This allows a high degree of flexibility in the overall operation of
the interface.
@ 8-Bit Bidirectional Data Bus for Communication with the
MPU
@ Two Bidirectional 8-Bit Buses for Interface to Peripherals
@ Two Programmable Control Registers
@ Two Programmable Data Direction Registers
@ Four Individually-Controlled Interrupt Input Lines; Two *>~+s\~, *V$3
Usable as Peripheral Control Outputs *&a ‘3,
“‘i
\; k“ 3
,J
@ Handshake Control Logic for Input and Output Periphe~~~~‘~~~~.~‘~“‘
Operation .h*+ .,‘:#
Kit\&
‘i.
High-Impedance Three-State and Direct Transis$r DriGe
Peripheral Lines >@. ‘+
!a<$.
_ “&
Program Controlled Interrupt and InterruptV&$%$e Capability
CMOS Drive Capability on Side A Peri~~~~~~~~~~~s
Two TTL Drive Capability on All A a~~~~~~~e Buffers
_’
0 TTL-Compatible ,A.
/ ;;;g>* *v*
@ Static Operation x;<+
,*e .\+
“<&
i ‘\<
,V,&,, ‘~‘“:
vi, A
,,;# *&p
1 Plastic
P Suffix
1
INFORMATION
Frequency
(MHz)
1.0
1.0
1.5
1.5
2.0
1.0
1.0
1.5
1.5
2.0
Temperature
OT to 70°C
- 40°C
to 85’C
OT to 7OT
- 40°C
to 85’C
OT to 7OT
ooc to 7OT
- 4O’C
to 85’C
0°C to 70°C
- 40°C
to 85°C
OT to 70°C
Order Number
MC6821 L
MC6821 CL
MC68A21 L
MC68A21 CL
MC68B21 L
MC6821 S
MC6821 CS
MC68A21 S
MC68A21 CS
MC68B21 S
1.0
1.0
1.5
1.5
2.0
ooc to 70°C
MC6821 P
- 40°C
to 85OC MC682lCP
0°C to 7OT MC68A21 P
- 40°C
to 85°C MC68A21 CP
0°C to 7ooc
MC68B21 P
IN-CHAN
ERDIP PACKAGE
PLASTIC PACKAGE
CASE 711
PIN ASSIGNMENT
@MOTOROLA INC ,1985 DS9435R5
MAXIMUM RATINGS
Characteristics Symbol Value Unit
Supply Voltage “cc -0.3 to +7.0 v
Input Voltage “in -0.3 to +7.0 v
Operating Temperature Range TL to TH
MC6821, MC68A21, MC68B21 T A 0 to 70 T
MC6821C. MC68A21C -40 to +85
Storage Temperature Range Tstg -55to +150 “C
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Ceramic
Plastic
Symbol
BJA
Value
50
loo
Unit
T/W
I Cerdip
I
60 I
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in OC can be obtained from:
TJ=TA+(PD*BJA)
Where:
This device contains clrcuttry to protect the
inputs against damage due to high static
voltages or electric fields, however, It IS ad-
vised that normal precautions be taken lo
avoid applications of any voltage higher than
maxlmum rated voltages to this high-
Impedance circuit. For proper operation It IS
recommended that V,, and Vout be CQI?~.
“b@ ,%i
stralned to the range VSS 5 (V.,m,.‘~~:$[‘
VrJut~~VCC- i”
<;g ;.& ‘h
Unused inputs must always ~-~~~~~~~~~n
appropriate logic voltage lev$@&*;f@ther
VSS or VCC). .” ‘I_ \*< ;g
\*$ *& S?W
1 x’:2$.\ -“;
“-$y$\ ‘kji>b
1.
>kt,;,.
‘, i
q,;p
(I)
TA = Ambient Temperature, ‘C
BJ,L,= Package Thermal Resistance, Junction-to-Ambient, sC@$:, ._ ‘,\,,,P
PD=PINT+ PPORT
PINT= ICC
x VCC, Watts - Chip Internal Power a>t+~+t,p
*-$’ “.TS~ “$~,
PpDRT= Port Power Dissipation, Watts - User D~~~~i~~d
For most applications PPoRT~PINT and can be neglected. ,,‘-,~ ‘ix A$
P~~~~ ‘* may become significant if the device is configured to
drive Darlington bases or sink LED loads. _-
**q
An approximate relationship between PD and TJ (if PBQRT i$ neglected) is:
PD = K + (T J + 273’C) ‘_ ‘y;,
“:.
“k\ Q
Solving equations 1 and 2 for K gives: ‘ST<.*. “.
~ -; “$” _ b *\
\\
K = PD*iTA + 273%) +
0Jj@D2 ,~~~~~,~~~~ -) (3)
Where K is a constant pertaining to the par;Q&,&r part. K can be determined from equation (3) by measurtng PD (at equlllbrium)
*>;>,v\,t:, “B
for a known TA. Using this value of K the ~~~~~~,~~ PD and TJ can be obtained by solving equations II) and (2) iteratively for any
value of TA.
DC ELECTRICAL CHARAC@&dS
(V CC = 5.0 Vdc f 5%, VSS = 0, TA= TL to TH unless otherwise noted)
I _” rib\,, , f
,j Characteristic ) Symbol 1 Min ) Typ 1 Max I Unit ]
BUS CONTROL INPlJ~~&&$ Ehable, RESET, RSO, RSl, CSO, CSl, CS2)
\- ,, “IH vss+2.0 - “cc V
“IL VSS-0.3 - VSS+O.8 V
lin - 1.0 2.5 FA
Capacita& Cu’$= 0, TA= 25OC, f = 1 .O MHz) Cin - - 7.5 PF
--
INTEF&&j”t”&dfTPUTS (IRQA, IROB)
@@&$% VOltage (ILoad = 3.2 mA) VOL - -
?$$&&tput Leakage Current vss+o.4 v
IO2 - 1.0 10 @A
Caaacitance (Vin = 0, Tn = 25OC. f = 1 .O MHz) cm It - - 5.0 PF
DATA BUS (DO-D71
Input High Voltage
Input Low Voltage
Hi-Z Input Leakage Current lVin=0.4 to 2.4 V)
Output High Voltage (ILoad = - 205 PA)
Output Low Voltage (lLoad= 1.6 mA)
Capacitance IVin = 0, TA = 25OC, f = 1 .O MHz)
VIH vss+2.0 - “cc V
VIL VSS-0.3 - VSS+O.8 V
‘I2 - 2.0 10 LtA
VOH VSS+2.4 - - V
VOL - - vss+o.4 v
Cin - - 12.5 PF
DC ELECTRICAL CHARACTERISTICS
(Continued)
Characteristic
PERIPHERAL BUS (PAO-PA7, PBO-PB7, CAl, CA2, CBl, CB2) 1 Symbol 1 Min 1 Typ 1 Max [ Unit ]
Capacitance (Vin = 0, TA= 25”C, f = 1 .O MHz)
POWER REQUIREMENTS
Internal Power Dissipation (Measured at TL=O”C)
1 c I”
PlNT
I Is
Symbol Characteristic
I”I111.
I I
Number
‘The data bus output buffers are no longer.&k@hg or srnkrng current by tDHPmax (Hugh Impedance)
&\ V,k< *i”
‘>*\>y,.\ <,- ,>*
_ .y<*:,
Notes:
1. Voltage levels shown are V~s0.4 V, VHr2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified.
3
PERIPHERAL TlMlNG CHARACTERISTICS
(VW = 5 0 V * 5%. VSS = 0 V, TA= TI- to TH unless otherwlse speclfied)
Characteristic
(PAO-PA7, CA2)
Test Point 7 eL 30 pF
I
T
FIGURE 3 - TTL EQUIVALENT
TEST LOAD
(PAD-PA7, PBO-PB7, CA2, CB2)
P 5.0v
t
RL=1.25 kht
Test Point
C=3OpF, R=12 k
MM06150
or Equiv.
MMD7000
or Equiv.
FIGURE 5 - NMOS EQUIVALENT
TEST LOAD
(IRQ Only)
5.0 v
Test Point
4
100 PF
T
1.5 kQ
a
-
FIGURE 6 - PERIPHERAL DATA SETUP AND HOLD TIMES FIGURE 7 - CA2 DELAY TIME
(Read Mode) (Read Mode; CRA-5= CRA3= 1, CRA-4= 0)
Enable j+-/j-
FIGURE 8 - CA2 DELAY TIME
(Read Mode; CRAd= 1, CRA3= CRA-4= 0)
FIGURE 10 - PERIPHERAL DATA AND CB2 DELAY TIMES
(Write Mode; CRBd=CRB-3= 1, CRB-4=0) ,&
*A “*,*<
‘SF\ “.>l
Enable
CRB-3=CRB-4=0)
CA2
r
*Assumes part was dese
the previous E pulse.
FIGURE 9 - PERIPHERAL CM
(Write Mode; CRA4= 0)
FIGURE 11 - CB2 DELAY TIME
(Write Mode; CRB-5= CRB-3= 1, CRB-4=0)
FIGURE 13 - INTERRUPT PULSE WIDTH AND m RESPONSE
IROA’6. j_ tRs,*-L
*Assumes Interrupt Enable Bits are set.
*Assumes part was deselected during
any previous E pulse.
Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted
FIGURE 14 - IRQ RELEASE TIME FIGURE 15 - RESET LOW TIME
-I
Note: Timing measuremenrs are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwis6+~@$&~
A- \*J& / *
_ &q “5’
_ \
FIGURE 16 - EXPANDED BLOCK DIAGRAM
IRQA 36 40 CA1
.
39 CA2
4
DO 33 -s-J---
01 32
02 31
D3 30 Data BUS
Buffers
04 29 (DEB)
D5 28
D6 27 2 PA0
3 PA1
4 PAZ
5 PA3
6 PA4
7 PA5
8 PA6
9 PA7
07 26
--Jr
10 PBO
11 PBl output
Register B
(ORB) Pertpheral
lnlerface
B
12 PB2
i3 PB3
14 PB4
15 PB5
16 PB6
17 PBJ
c -18 CBI
Interrupt sratus
IRQB 37 4 Control B -19 CB2
PIA INTERFACE SIGNALS FOR MPU
The PIA interfaces to the M6800 bus with an 8-bit bidirec-
tional data bus, three chip select lines, two register select
lines, two interrupt request lines, a read/write line, an enable
line and a reset line. To ensure proper operation with the
MC6800, MC6802, or MC6808 microprocessors, VMA
should be used as an active part of the address decoding.
Bidirectional Data (DO-D71 - The bidirectional data lines
(DO-D7) allow the transfer of data between the MPU and the
PIA. The data bus output drivers are three-state devices that
remain in the high-impedance (off) state except when the
MPU performs a PIA read operation. The read/write line is in
the read (high) state when the PIA is selected for a read
operation.
Enable (E) - The enable pulse, E, is the only timing
signal that is supplied to the PIA. Timing of all other signals
is referenced to the leading and trailing edges of the E pulse.
Read/Write (R/W) - This signal is generated by the
MPU to control the direction of data transfers on the data
bus. A low state on the PIA read/write line enables the input
buffers and data is transferred from the MPU to the PIA on
the E signal if the device has been selected. A high on the
read/write line sets up the PIA for a transfer of data to the
bus. The PIA output buffers are enabled when the proper ad-
dress and the enable pulse E are present.
RESET - The active low RESET line is used to re$${3all
register bits in the PIA to a logical zero (low). This lin&Qar%e
d$*h~bs ; ‘”
used as a power-on reset and as a master rese@%nng
system operation * \~\\>;,~S*;
Chip Selects (CSO, CSI, and cs2) ~~~%&$$e’three input
signals are used to select the PIA. C&O’%<% CSI must be
high and CS2 must be low for sel~~~~~~~he device. Data
transfers are then performed und&h&ontrol of the enable
$..+ ‘at; _ *a $,.‘
and read/write signals. The ct$p s@ect lines must be stable
for the duration of the E pulse. The device is deselected
when any of the chip selects are in the inactive state
Register Selects (RSO and RSI) - The two register
written or read.
interrupt by the MPU may be accomplished
routine that, on a prioritized basis, sequentially
s and tests the two control registers in each PIA for in-
flag bits that are set.
The interrupt flags are cleared (zeroed) as a result of an
MPU Read Peripheral Data Operation of the corresponding
data register. After being cleared, the interrupt flag bit can-
not be enabled to be set until the PIA is deselected during an
E pulse. The E pulse is used to condition the interrupt control
lines (CAI, CA2, CBI, CB2). When these lines are used as
interrupt inputs, at least one E pulse must occur from the in-
active edge to the active edge of the interrupt input signal to
condition the edge sense network. If the interrupt flag has
been enabled and the edge sense circuit has been properly
conditioned, the interrupt flag will be set on the next active
transition of the interrupt input pin.
PIA PERIPHERAL INTERFACE LINES
The Pl~.~~~~~~s two 8-bit bidirectional data buses and
four in~~m$&control lines for interfacing to peripheral
de$sq&+
*\~,$\>\<Jt~>~\~ *
~~~~~on A Peripheral Data (PAO-PA71 - Each of the
petrpheral data lines can be programmed to act as an input or
output. This is accomplished by setting a “1” in the cor-
responding Data Direction Register bit for those lines which
are to be outputs. A “0” in a bit of the Data Direction
Register causes the corresponding peripheral data line to act
as an input. During an MPU Read Peripheral Data Operation,
the data on peripheral lines programmed to act as inputs ap-
pears directly on the corresponding MPU Data Bus lines. In
the input mode, the internal pullup resistor on these lines
represents a maximum of 1.5 standard TTL loads.
The data in Output Register A will appear on the data lines
that are programmed to be outputs. A logical “1” written in-
to the register will cause a “high” on the corresponding data
-
line while a “0” results in a “low.” Data in Output Register A
may be read by an MPU “Read Peripheral Data A” operation
when the corresponding lines are programmed as outputs.
This data will be read properly if the voltage on the
peripheral data lines is greater than 2.0 volts for a logic “I”
output and less than 0.8 volt for a logic “0” output. Loading
the output lines such that the voltage on these lines does not
reach full voltage causes the data transferred into the MPU
on a Read operation to differ from that contained in the
respective bit of Output Register A.
Section B Peripheral Data (PBO-PB7) - The peripheral
data lines in the B Section of the PIA can be programmed to
act as either inputs or outputs in a similar manner to PAO-
PA7. They have three-state capabiity, allowing them to enter
a high-impedance state when the peripheral data line is used
as an input. In addition, data on the peripheral data lines